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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.29 95.74 93.96 97.54 92.52 98.23 98.06 98.00


Total test records in report: 1238
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T1069 /workspace/coverage/default/13.flash_ctrl_rw_evict.1104767083 Jun 11 03:09:00 PM PDT 24 Jun 11 03:09:33 PM PDT 24 83823900 ps
T1070 /workspace/coverage/default/3.flash_ctrl_ro_derr.2288866568 Jun 11 03:02:21 PM PDT 24 Jun 11 03:04:41 PM PDT 24 6356715900 ps
T1071 /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2098780646 Jun 11 02:58:53 PM PDT 24 Jun 11 02:59:08 PM PDT 24 44868200 ps
T1072 /workspace/coverage/default/4.flash_ctrl_invalid_op.2620853533 Jun 11 03:03:10 PM PDT 24 Jun 11 03:04:38 PM PDT 24 1956367100 ps
T1073 /workspace/coverage/default/47.flash_ctrl_alert_test.662992794 Jun 11 03:14:46 PM PDT 24 Jun 11 03:15:01 PM PDT 24 29910800 ps
T1074 /workspace/coverage/default/38.flash_ctrl_connect.1813614577 Jun 11 03:14:06 PM PDT 24 Jun 11 03:14:20 PM PDT 24 16484500 ps
T13 /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.713119369 Jun 11 03:02:38 PM PDT 24 Jun 11 03:02:54 PM PDT 24 25922600 ps
T1075 /workspace/coverage/default/46.flash_ctrl_alert_test.1556156925 Jun 11 03:14:45 PM PDT 24 Jun 11 03:14:59 PM PDT 24 52895400 ps
T1076 /workspace/coverage/default/4.flash_ctrl_mp_regions.968310257 Jun 11 03:03:04 PM PDT 24 Jun 11 03:20:25 PM PDT 24 31976126900 ps
T1077 /workspace/coverage/default/53.flash_ctrl_connect.220638007 Jun 11 03:15:02 PM PDT 24 Jun 11 03:15:19 PM PDT 24 139899900 ps
T1078 /workspace/coverage/default/36.flash_ctrl_connect.958978447 Jun 11 03:13:45 PM PDT 24 Jun 11 03:14:02 PM PDT 24 15597200 ps
T1079 /workspace/coverage/default/32.flash_ctrl_intr_rd.2881876018 Jun 11 03:13:19 PM PDT 24 Jun 11 03:15:27 PM PDT 24 513726700 ps
T234 /workspace/coverage/default/1.flash_ctrl_wr_intg.4093412396 Jun 11 03:00:03 PM PDT 24 Jun 11 03:00:19 PM PDT 24 44503400 ps
T137 /workspace/coverage/default/0.flash_ctrl_rma_err.987055507 Jun 11 02:58:52 PM PDT 24 Jun 11 03:16:15 PM PDT 24 157544442500 ps
T1080 /workspace/coverage/default/77.flash_ctrl_connect.3301159871 Jun 11 03:15:21 PM PDT 24 Jun 11 03:15:37 PM PDT 24 13117400 ps
T1081 /workspace/coverage/default/0.flash_ctrl_ro_serr.3202636306 Jun 11 02:58:08 PM PDT 24 Jun 11 03:00:24 PM PDT 24 6112412200 ps
T1082 /workspace/coverage/default/1.flash_ctrl_smoke_hw.586099021 Jun 11 02:59:13 PM PDT 24 Jun 11 02:59:38 PM PDT 24 232172300 ps
T1083 /workspace/coverage/default/16.flash_ctrl_rw.2401253679 Jun 11 03:10:13 PM PDT 24 Jun 11 03:21:56 PM PDT 24 9660456500 ps
T1084 /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1874793852 Jun 11 03:08:33 PM PDT 24 Jun 11 03:26:43 PM PDT 24 420249567500 ps
T1085 /workspace/coverage/default/59.flash_ctrl_connect.3866947782 Jun 11 03:15:02 PM PDT 24 Jun 11 03:15:17 PM PDT 24 48794400 ps
T1086 /workspace/coverage/default/40.flash_ctrl_disable.2362387107 Jun 11 03:14:15 PM PDT 24 Jun 11 03:14:38 PM PDT 24 29610000 ps
T1087 /workspace/coverage/default/22.flash_ctrl_connect.3065591810 Jun 11 03:11:46 PM PDT 24 Jun 11 03:12:00 PM PDT 24 22267600 ps
T1088 /workspace/coverage/default/18.flash_ctrl_ro.3651389680 Jun 11 03:10:56 PM PDT 24 Jun 11 03:12:39 PM PDT 24 1795449700 ps
T68 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.345863735 Jun 11 02:29:38 PM PDT 24 Jun 11 02:37:15 PM PDT 24 640214800 ps
T262 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2799166756 Jun 11 02:30:21 PM PDT 24 Jun 11 02:30:36 PM PDT 24 41691400 ps
T69 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3980411479 Jun 11 02:29:16 PM PDT 24 Jun 11 02:29:38 PM PDT 24 211024200 ps
T1089 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.966729410 Jun 11 02:28:45 PM PDT 24 Jun 11 02:28:59 PM PDT 24 14721700 ps
T70 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2634919889 Jun 11 02:28:56 PM PDT 24 Jun 11 02:43:56 PM PDT 24 927403100 ps
T263 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2653007876 Jun 11 02:29:18 PM PDT 24 Jun 11 02:29:32 PM PDT 24 49574400 ps
T201 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.597901523 Jun 11 02:28:46 PM PDT 24 Jun 11 02:29:06 PM PDT 24 158190800 ps
T259 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2019835962 Jun 11 02:29:02 PM PDT 24 Jun 11 02:30:33 PM PDT 24 4147420600 ps
T216 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.95098467 Jun 11 02:29:36 PM PDT 24 Jun 11 02:36:05 PM PDT 24 437271100 ps
T214 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1240108374 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:28 PM PDT 24 114179600 ps
T264 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.4198434341 Jun 11 02:28:44 PM PDT 24 Jun 11 02:29:23 PM PDT 24 96973500 ps
T334 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1802293542 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 16683700 ps
T219 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.508896019 Jun 11 02:29:37 PM PDT 24 Jun 11 02:29:54 PM PDT 24 32958400 ps
T256 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3814455296 Jun 11 02:30:00 PM PDT 24 Jun 11 02:30:36 PM PDT 24 289444300 ps
T1090 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.826458081 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:10 PM PDT 24 34861500 ps
T238 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1654621787 Jun 11 02:29:08 PM PDT 24 Jun 11 02:41:37 PM PDT 24 465518000 ps
T215 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2799012705 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:15 PM PDT 24 45278000 ps
T220 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3753272370 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:24 PM PDT 24 101124600 ps
T1091 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.295883372 Jun 11 02:29:36 PM PDT 24 Jun 11 02:29:53 PM PDT 24 42442500 ps
T217 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3430699772 Jun 11 02:29:21 PM PDT 24 Jun 11 02:36:53 PM PDT 24 272990100 ps
T1092 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.251097378 Jun 11 02:29:22 PM PDT 24 Jun 11 02:29:39 PM PDT 24 193173200 ps
T335 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3903387621 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:25 PM PDT 24 94494100 ps
T337 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2197046624 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 51975000 ps
T244 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1314309125 Jun 11 02:28:37 PM PDT 24 Jun 11 02:28:51 PM PDT 24 34056300 ps
T1093 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.981052515 Jun 11 02:28:34 PM PDT 24 Jun 11 02:28:47 PM PDT 24 42204700 ps
T1094 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.824815892 Jun 11 02:28:24 PM PDT 24 Jun 11 02:28:38 PM PDT 24 64025000 ps
T239 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.419879419 Jun 11 02:29:37 PM PDT 24 Jun 11 02:29:53 PM PDT 24 60463300 ps
T336 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2750352106 Jun 11 02:28:36 PM PDT 24 Jun 11 02:28:50 PM PDT 24 16944000 ps
T257 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2472924791 Jun 11 02:29:16 PM PDT 24 Jun 11 02:29:35 PM PDT 24 693174200 ps
T338 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2620098497 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:21 PM PDT 24 101964300 ps
T1095 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1595641909 Jun 11 02:28:35 PM PDT 24 Jun 11 02:28:51 PM PDT 24 42842300 ps
T1096 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2273218430 Jun 11 02:28:25 PM PDT 24 Jun 11 02:28:42 PM PDT 24 11609200 ps
T1097 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3280424385 Jun 11 02:28:36 PM PDT 24 Jun 11 02:28:52 PM PDT 24 53871500 ps
T339 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1580435408 Jun 11 02:29:26 PM PDT 24 Jun 11 02:29:40 PM PDT 24 53881400 ps
T1098 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2181900618 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:29 PM PDT 24 62690500 ps
T218 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2048161447 Jun 11 02:29:53 PM PDT 24 Jun 11 02:30:12 PM PDT 24 52640400 ps
T1099 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3926824160 Jun 11 02:30:10 PM PDT 24 Jun 11 02:30:25 PM PDT 24 59777800 ps
T298 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1215688761 Jun 11 02:28:35 PM PDT 24 Jun 11 02:28:52 PM PDT 24 144591500 ps
T1100 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.927943303 Jun 11 02:28:36 PM PDT 24 Jun 11 02:28:53 PM PDT 24 155423900 ps
T240 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1966944767 Jun 11 02:29:27 PM PDT 24 Jun 11 02:29:47 PM PDT 24 690401800 ps
T1101 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2524798481 Jun 11 02:28:47 PM PDT 24 Jun 11 02:29:22 PM PDT 24 849764300 ps
T1102 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2391281330 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:12 PM PDT 24 47867300 ps
T1103 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2929888395 Jun 11 02:30:10 PM PDT 24 Jun 11 02:30:25 PM PDT 24 41921000 ps
T1104 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.977668339 Jun 11 02:29:50 PM PDT 24 Jun 11 02:30:04 PM PDT 24 14949400 ps
T1105 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2326791970 Jun 11 02:29:50 PM PDT 24 Jun 11 02:30:06 PM PDT 24 28267300 ps
T1106 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.864650263 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:24 PM PDT 24 16939100 ps
T1107 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1190673289 Jun 11 02:30:07 PM PDT 24 Jun 11 02:30:22 PM PDT 24 29425900 ps
T1108 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2165283891 Jun 11 02:30:18 PM PDT 24 Jun 11 02:30:32 PM PDT 24 20024500 ps
T245 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1559827513 Jun 11 02:28:55 PM PDT 24 Jun 11 02:29:09 PM PDT 24 49991100 ps
T1109 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3769078852 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:24 PM PDT 24 169953900 ps
T1110 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1149555679 Jun 11 02:28:36 PM PDT 24 Jun 11 02:29:13 PM PDT 24 1277363900 ps
T241 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3918019216 Jun 11 02:28:44 PM PDT 24 Jun 11 02:29:03 PM PDT 24 47944300 ps
T1111 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2047203168 Jun 11 02:29:53 PM PDT 24 Jun 11 02:30:28 PM PDT 24 229934700 ps
T1112 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3504326005 Jun 11 02:29:18 PM PDT 24 Jun 11 02:29:32 PM PDT 24 45156100 ps
T1113 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.290975796 Jun 11 02:28:36 PM PDT 24 Jun 11 02:28:50 PM PDT 24 256811300 ps
T319 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1173083266 Jun 11 02:29:17 PM PDT 24 Jun 11 02:37:07 PM PDT 24 178059000 ps
T1114 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.645138903 Jun 11 02:29:16 PM PDT 24 Jun 11 02:29:30 PM PDT 24 81383400 ps
T297 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.309772229 Jun 11 02:29:48 PM PDT 24 Jun 11 02:30:04 PM PDT 24 367181600 ps
T1115 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2751261281 Jun 11 02:29:49 PM PDT 24 Jun 11 02:30:03 PM PDT 24 68585000 ps
T1116 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3334129923 Jun 11 02:28:57 PM PDT 24 Jun 11 02:29:37 PM PDT 24 69973900 ps
T1117 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1765220141 Jun 11 02:28:55 PM PDT 24 Jun 11 02:29:13 PM PDT 24 44357600 ps
T1118 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2941552817 Jun 11 02:28:45 PM PDT 24 Jun 11 02:28:58 PM PDT 24 39446300 ps
T1119 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1020630709 Jun 11 02:30:01 PM PDT 24 Jun 11 02:30:18 PM PDT 24 35381400 ps
T1120 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1855079335 Jun 11 02:28:44 PM PDT 24 Jun 11 02:28:58 PM PDT 24 160596100 ps
T274 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4112333165 Jun 11 02:29:07 PM PDT 24 Jun 11 02:35:27 PM PDT 24 395084200 ps
T246 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1786472815 Jun 11 02:28:35 PM PDT 24 Jun 11 02:28:49 PM PDT 24 43254600 ps
T1121 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.128919468 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:14 PM PDT 24 32576000 ps
T1122 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3342003019 Jun 11 02:29:53 PM PDT 24 Jun 11 02:30:10 PM PDT 24 18004800 ps
T1123 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.915830196 Jun 11 02:28:45 PM PDT 24 Jun 11 02:29:21 PM PDT 24 241646900 ps
T271 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1152586261 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:16 PM PDT 24 372785800 ps
T299 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4151147737 Jun 11 02:29:39 PM PDT 24 Jun 11 02:29:56 PM PDT 24 101549900 ps
T260 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3306284721 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:35 PM PDT 24 132397600 ps
T1124 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.195690541 Jun 11 02:30:06 PM PDT 24 Jun 11 02:30:21 PM PDT 24 50997400 ps
T1125 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2917318935 Jun 11 02:29:21 PM PDT 24 Jun 11 02:29:35 PM PDT 24 29262100 ps
T261 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2105861437 Jun 11 02:29:09 PM PDT 24 Jun 11 02:29:26 PM PDT 24 30451900 ps
T1126 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3445264319 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 77887300 ps
T360 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2444046436 Jun 11 02:30:33 PM PDT 24 Jun 11 02:38:17 PM PDT 24 193964900 ps
T1127 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4042198199 Jun 11 02:28:36 PM PDT 24 Jun 11 02:29:36 PM PDT 24 6668328700 ps
T1128 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.950272490 Jun 11 02:28:47 PM PDT 24 Jun 11 02:29:02 PM PDT 24 17063300 ps
T272 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1566927847 Jun 11 02:29:06 PM PDT 24 Jun 11 02:29:26 PM PDT 24 86430300 ps
T1129 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3165283129 Jun 11 02:29:27 PM PDT 24 Jun 11 02:29:48 PM PDT 24 64849600 ps
T1130 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.970758451 Jun 11 02:29:21 PM PDT 24 Jun 11 02:29:37 PM PDT 24 69761600 ps
T1131 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2816356614 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:22 PM PDT 24 18957800 ps
T302 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2679825869 Jun 11 02:29:47 PM PDT 24 Jun 11 02:30:06 PM PDT 24 97604300 ps
T276 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2784111537 Jun 11 02:30:00 PM PDT 24 Jun 11 02:37:44 PM PDT 24 429155400 ps
T1132 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2673091580 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:33 PM PDT 24 19862100 ps
T1133 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2216621832 Jun 11 02:29:57 PM PDT 24 Jun 11 02:30:14 PM PDT 24 17334400 ps
T277 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1867374298 Jun 11 02:28:45 PM PDT 24 Jun 11 02:36:21 PM PDT 24 955431300 ps
T1134 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1635010804 Jun 11 02:29:26 PM PDT 24 Jun 11 02:29:43 PM PDT 24 31472400 ps
T247 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1459016190 Jun 11 02:28:45 PM PDT 24 Jun 11 02:29:00 PM PDT 24 32526300 ps
T1135 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3400429969 Jun 11 02:29:36 PM PDT 24 Jun 11 02:29:50 PM PDT 24 57024500 ps
T265 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2917860240 Jun 11 02:29:25 PM PDT 24 Jun 11 02:29:45 PM PDT 24 59062700 ps
T1136 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3660021844 Jun 11 02:29:37 PM PDT 24 Jun 11 02:29:52 PM PDT 24 72689900 ps
T1137 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3848143760 Jun 11 02:29:16 PM PDT 24 Jun 11 02:29:33 PM PDT 24 12293000 ps
T1138 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1873799107 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 23043400 ps
T1139 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2879879381 Jun 11 02:30:20 PM PDT 24 Jun 11 02:30:35 PM PDT 24 18711600 ps
T303 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.719374496 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:25 PM PDT 24 360925000 ps
T270 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3926648229 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:20 PM PDT 24 111342900 ps
T1140 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4113771759 Jun 11 02:29:56 PM PDT 24 Jun 11 02:30:13 PM PDT 24 61521400 ps
T273 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4173280206 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:34 PM PDT 24 82166400 ps
T1141 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3417753471 Jun 11 02:29:25 PM PDT 24 Jun 11 02:29:41 PM PDT 24 36260800 ps
T1142 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.674198519 Jun 11 02:29:36 PM PDT 24 Jun 11 02:29:50 PM PDT 24 27874900 ps
T266 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.833349199 Jun 11 02:29:20 PM PDT 24 Jun 11 02:29:39 PM PDT 24 203693100 ps
T1143 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2292405754 Jun 11 02:29:51 PM PDT 24 Jun 11 02:30:07 PM PDT 24 51624100 ps
T1144 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.178229390 Jun 11 02:28:55 PM PDT 24 Jun 11 02:29:14 PM PDT 24 247130000 ps
T1145 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2401696971 Jun 11 02:28:24 PM PDT 24 Jun 11 02:28:38 PM PDT 24 14549700 ps
T1146 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3381741595 Jun 11 02:29:26 PM PDT 24 Jun 11 02:29:41 PM PDT 24 16900000 ps
T1147 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2914588259 Jun 11 02:28:45 PM PDT 24 Jun 11 02:29:02 PM PDT 24 11695100 ps
T1148 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.545387596 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 99895100 ps
T268 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.123729314 Jun 11 02:28:26 PM PDT 24 Jun 11 02:28:46 PM PDT 24 220600400 ps
T267 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3665774240 Jun 11 02:29:48 PM PDT 24 Jun 11 02:30:07 PM PDT 24 47403600 ps
T1149 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1274086394 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:16 PM PDT 24 48080600 ps
T1150 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1894164955 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 25869200 ps
T1151 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2956008050 Jun 11 02:29:51 PM PDT 24 Jun 11 02:30:08 PM PDT 24 11386600 ps
T1152 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2386229013 Jun 11 02:29:35 PM PDT 24 Jun 11 02:29:52 PM PDT 24 12676100 ps
T269 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2755142436 Jun 11 02:28:46 PM PDT 24 Jun 11 02:29:04 PM PDT 24 63114700 ps
T1153 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4209540242 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 25008700 ps
T1154 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.536062696 Jun 11 02:29:38 PM PDT 24 Jun 11 02:29:58 PM PDT 24 582371900 ps
T1155 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.306426361 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:31 PM PDT 24 39178800 ps
T1156 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2202035175 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:27 PM PDT 24 21269900 ps
T1157 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3547143065 Jun 11 02:28:37 PM PDT 24 Jun 11 02:28:57 PM PDT 24 227772900 ps
T363 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3588602992 Jun 11 02:29:50 PM PDT 24 Jun 11 02:36:10 PM PDT 24 1025498900 ps
T300 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.171392047 Jun 11 02:29:51 PM PDT 24 Jun 11 02:44:37 PM PDT 24 3129138700 ps
T356 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2905612477 Jun 11 02:29:26 PM PDT 24 Jun 11 02:29:45 PM PDT 24 57225000 ps
T1158 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.994651794 Jun 11 02:29:27 PM PDT 24 Jun 11 02:29:44 PM PDT 24 29257000 ps
T1159 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.699444371 Jun 11 02:29:28 PM PDT 24 Jun 11 02:29:45 PM PDT 24 67883300 ps
T1160 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1659088974 Jun 11 02:29:50 PM PDT 24 Jun 11 02:30:04 PM PDT 24 11729700 ps
T1161 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2425868351 Jun 11 02:29:50 PM PDT 24 Jun 11 02:30:04 PM PDT 24 14515500 ps
T358 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1544092468 Jun 11 02:29:26 PM PDT 24 Jun 11 02:37:01 PM PDT 24 369158200 ps
T1162 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.807214379 Jun 11 02:29:09 PM PDT 24 Jun 11 02:29:26 PM PDT 24 11814500 ps
T1163 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.550307378 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:19 PM PDT 24 73769600 ps
T301 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1465297232 Jun 11 02:28:46 PM PDT 24 Jun 11 02:30:21 PM PDT 24 12415358900 ps
T357 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3935481649 Jun 11 02:29:39 PM PDT 24 Jun 11 02:29:56 PM PDT 24 34097200 ps
T1164 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.55712888 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:24 PM PDT 24 70767400 ps
T364 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1268566256 Jun 11 02:28:35 PM PDT 24 Jun 11 02:41:08 PM PDT 24 1915736900 ps
T1165 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2190090445 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:30 PM PDT 24 1220517600 ps
T1166 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3470082630 Jun 11 02:28:46 PM PDT 24 Jun 11 02:29:04 PM PDT 24 126277600 ps
T361 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.524294812 Jun 11 02:28:22 PM PDT 24 Jun 11 02:43:23 PM PDT 24 1421073200 ps
T1167 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3559776214 Jun 11 02:29:06 PM PDT 24 Jun 11 02:29:20 PM PDT 24 31264200 ps
T1168 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1539317157 Jun 11 02:30:19 PM PDT 24 Jun 11 02:30:34 PM PDT 24 50414200 ps
T1169 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4195836397 Jun 11 02:30:10 PM PDT 24 Jun 11 02:30:25 PM PDT 24 27339900 ps
T1170 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1444741036 Jun 11 02:29:50 PM PDT 24 Jun 11 02:30:05 PM PDT 24 26860600 ps
T1171 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1345949299 Jun 11 02:28:58 PM PDT 24 Jun 11 02:29:17 PM PDT 24 96093800 ps
T1172 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3782223779 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:36 PM PDT 24 236739600 ps
T1173 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3818862992 Jun 11 02:29:49 PM PDT 24 Jun 11 02:30:08 PM PDT 24 97131400 ps
T1174 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2473276141 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:14 PM PDT 24 114850200 ps
T1175 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2656305404 Jun 11 02:28:56 PM PDT 24 Jun 11 02:30:04 PM PDT 24 5075712200 ps
T1176 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2987312057 Jun 11 02:29:24 PM PDT 24 Jun 11 02:29:41 PM PDT 24 90147500 ps
T1177 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1577104469 Jun 11 02:28:36 PM PDT 24 Jun 11 02:29:25 PM PDT 24 439550200 ps
T1178 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2169263947 Jun 11 02:29:38 PM PDT 24 Jun 11 02:29:54 PM PDT 24 56088000 ps
T1179 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2859240146 Jun 11 02:28:36 PM PDT 24 Jun 11 02:29:59 PM PDT 24 6431669300 ps
T1180 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3238801617 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:25 PM PDT 24 17702800 ps
T1181 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3928939767 Jun 11 02:28:35 PM PDT 24 Jun 11 02:29:21 PM PDT 24 88198000 ps
T359 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4227311379 Jun 11 02:29:26 PM PDT 24 Jun 11 02:37:06 PM PDT 24 340780200 ps
T1182 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3248731157 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:14 PM PDT 24 17186400 ps
T1183 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3612185064 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 15230700 ps
T362 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3169432713 Jun 11 02:29:57 PM PDT 24 Jun 11 02:37:39 PM PDT 24 2061057800 ps
T1184 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1194470179 Jun 11 02:29:05 PM PDT 24 Jun 11 02:29:20 PM PDT 24 15873100 ps
T1185 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.60411028 Jun 11 02:30:10 PM PDT 24 Jun 11 02:30:25 PM PDT 24 20300500 ps
T1186 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.775559741 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 17882000 ps
T1187 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1174585027 Jun 11 02:29:05 PM PDT 24 Jun 11 02:29:22 PM PDT 24 43308900 ps
T1188 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.73411676 Jun 11 02:28:37 PM PDT 24 Jun 11 02:29:09 PM PDT 24 39837800 ps
T1189 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.615073279 Jun 11 02:29:57 PM PDT 24 Jun 11 02:30:11 PM PDT 24 10942200 ps
T1190 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.580066421 Jun 11 02:29:25 PM PDT 24 Jun 11 02:29:43 PM PDT 24 103273100 ps
T1191 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2515333502 Jun 11 02:29:51 PM PDT 24 Jun 11 02:30:07 PM PDT 24 14327700 ps
T1192 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4228422463 Jun 11 02:28:45 PM PDT 24 Jun 11 02:29:03 PM PDT 24 292849900 ps
T1193 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.853520172 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:26 PM PDT 24 30722800 ps
T1194 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2334795906 Jun 11 02:29:57 PM PDT 24 Jun 11 02:30:16 PM PDT 24 85604100 ps
T1195 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4219883658 Jun 11 02:29:17 PM PDT 24 Jun 11 02:29:36 PM PDT 24 54344900 ps
T1196 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3704438262 Jun 11 02:29:48 PM PDT 24 Jun 11 02:30:02 PM PDT 24 19504700 ps
T1197 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1249322793 Jun 11 02:29:48 PM PDT 24 Jun 11 02:30:05 PM PDT 24 34541200 ps
T1198 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2203320765 Jun 11 02:28:57 PM PDT 24 Jun 11 02:29:11 PM PDT 24 17183200 ps
T1199 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.448786128 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 44365800 ps
T1200 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3918957428 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:11 PM PDT 24 51208000 ps
T1201 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1676581935 Jun 11 02:29:36 PM PDT 24 Jun 11 02:29:52 PM PDT 24 55275000 ps
T1202 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.398762088 Jun 11 02:29:27 PM PDT 24 Jun 11 02:29:44 PM PDT 24 12028700 ps
T1203 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3776498489 Jun 11 02:28:59 PM PDT 24 Jun 11 02:29:15 PM PDT 24 19673300 ps
T1204 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.968905760 Jun 11 02:28:57 PM PDT 24 Jun 11 02:29:11 PM PDT 24 30167100 ps
T1205 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1350277329 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:28 PM PDT 24 601041700 ps
T1206 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1171170187 Jun 11 02:28:57 PM PDT 24 Jun 11 02:29:55 PM PDT 24 2530263600 ps
T1207 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3710673406 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:44 PM PDT 24 1247912500 ps
T1208 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4266027037 Jun 11 02:29:23 PM PDT 24 Jun 11 02:29:40 PM PDT 24 29504300 ps
T1209 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1838406613 Jun 11 02:29:25 PM PDT 24 Jun 11 02:29:42 PM PDT 24 78938000 ps
T1210 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3606587943 Jun 11 02:29:25 PM PDT 24 Jun 11 02:29:42 PM PDT 24 15242200 ps
T366 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2662262415 Jun 11 02:29:58 PM PDT 24 Jun 11 02:37:38 PM PDT 24 855336900 ps
T1211 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.364834845 Jun 11 02:29:37 PM PDT 24 Jun 11 02:29:56 PM PDT 24 83652000 ps
T1212 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1419299099 Jun 11 02:29:38 PM PDT 24 Jun 11 02:29:56 PM PDT 24 37025400 ps
T1213 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2675825631 Jun 11 02:29:06 PM PDT 24 Jun 11 02:29:21 PM PDT 24 34133700 ps
T367 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3155955321 Jun 11 02:29:24 PM PDT 24 Jun 11 02:35:47 PM PDT 24 355507100 ps
T1214 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2097839396 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:22 PM PDT 24 16504000 ps
T1215 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3426266640 Jun 11 02:29:47 PM PDT 24 Jun 11 02:30:07 PM PDT 24 199707500 ps
T1216 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1909420830 Jun 11 02:28:55 PM PDT 24 Jun 11 02:29:41 PM PDT 24 45451400 ps
T1217 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1928418793 Jun 11 02:29:18 PM PDT 24 Jun 11 02:29:35 PM PDT 24 83549000 ps
T1218 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2829679904 Jun 11 02:29:20 PM PDT 24 Jun 11 02:29:36 PM PDT 24 234054300 ps
T1219 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3379594027 Jun 11 02:29:38 PM PDT 24 Jun 11 02:29:54 PM PDT 24 24204400 ps
T1220 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.452048121 Jun 11 02:29:06 PM PDT 24 Jun 11 02:29:24 PM PDT 24 70998900 ps
T1221 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2704369953 Jun 11 02:29:07 PM PDT 24 Jun 11 02:29:21 PM PDT 24 46688600 ps
T1222 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.307423701 Jun 11 02:30:00 PM PDT 24 Jun 11 02:30:17 PM PDT 24 14673100 ps
T1223 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.523547993 Jun 11 02:29:06 PM PDT 24 Jun 11 02:29:20 PM PDT 24 42218200 ps
T1224 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2692292068 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 14143300 ps
T1225 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.228593002 Jun 11 02:28:36 PM PDT 24 Jun 11 02:28:56 PM PDT 24 109180800 ps
T1226 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3889363596 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 45474000 ps
T1227 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2510188097 Jun 11 02:29:59 PM PDT 24 Jun 11 02:30:21 PM PDT 24 579206100 ps
T1228 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1711553985 Jun 11 02:30:11 PM PDT 24 Jun 11 02:30:25 PM PDT 24 48416000 ps
T1229 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.935379437 Jun 11 02:30:09 PM PDT 24 Jun 11 02:30:24 PM PDT 24 77119200 ps
T1230 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1134949837 Jun 11 02:28:56 PM PDT 24 Jun 11 02:29:36 PM PDT 24 791614700 ps
T1231 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.431558771 Jun 11 02:28:37 PM PDT 24 Jun 11 02:28:56 PM PDT 24 353965800 ps
T1232 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.755339699 Jun 11 02:28:46 PM PDT 24 Jun 11 02:29:03 PM PDT 24 22380000 ps
T1233 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.132772766 Jun 11 02:28:23 PM PDT 24 Jun 11 02:28:39 PM PDT 24 66102100 ps
T1234 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.673092300 Jun 11 02:29:15 PM PDT 24 Jun 11 02:29:33 PM PDT 24 84847200 ps
T365 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1794615559 Jun 11 02:28:44 PM PDT 24 Jun 11 02:43:56 PM PDT 24 349082200 ps
T1235 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2991889489 Jun 11 02:29:58 PM PDT 24 Jun 11 02:30:13 PM PDT 24 59855800 ps
T1236 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1282865225 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 93286600 ps
T1237 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.856762743 Jun 11 02:30:08 PM PDT 24 Jun 11 02:30:23 PM PDT 24 52523500 ps
T1238 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2552993956 Jun 11 02:30:10 PM PDT 24 Jun 11 02:30:27 PM PDT 24 87199800 ps

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2506855871
Short name T16
Test name
Test status
Simulation time 21946433700 ps
CPU time 173.97 seconds
Started Jun 11 02:59:22 PM PDT 24
Finished Jun 11 03:02:18 PM PDT 24
Peak memory 265444 kb
Host smart-f7a229bd-4c09-45a8-b855-70773d121cd9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506855871 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2506855871
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.2061607093
Short name T18
Test name
Test status
Simulation time 3329416300 ps
CPU time 147.72 seconds
Started Jun 11 03:08:32 PM PDT 24
Finished Jun 11 03:11:01 PM PDT 24
Peak memory 291692 kb
Host smart-8da4e2b0-a8d2-4c45-a1ac-42a7e4800308
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061607093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.2061607093
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2634919889
Short name T70
Test name
Test status
Simulation time 927403100 ps
CPU time 898.78 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:43:56 PM PDT 24
Peak memory 263784 kb
Host smart-eba70a49-2b80-48b2-a025-3fc1b10d5985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634919889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2634919889
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.483431303
Short name T24
Test name
Test status
Simulation time 130159692800 ps
CPU time 869.3 seconds
Started Jun 11 03:10:47 PM PDT 24
Finished Jun 11 03:25:17 PM PDT 24
Peak memory 264636 kb
Host smart-f0560699-90bf-4400-8170-034f68e963e3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483431303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.483431303
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.3623763292
Short name T7
Test name
Test status
Simulation time 17400299200 ps
CPU time 759.61 seconds
Started Jun 11 02:58:17 PM PDT 24
Finished Jun 11 03:10:58 PM PDT 24
Peak memory 343592 kb
Host smart-7eca26f2-a67b-4ed3-9838-3796c8e59d61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623763292 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.3623763292
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.1015204577
Short name T27
Test name
Test status
Simulation time 131469800 ps
CPU time 130 seconds
Started Jun 11 03:12:19 PM PDT 24
Finished Jun 11 03:14:30 PM PDT 24
Peak memory 265552 kb
Host smart-24d87139-d93b-4be2-823b-a22f6ca03a5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015204577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.1015204577
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1638705096
Short name T14
Test name
Test status
Simulation time 2144724900 ps
CPU time 6161.9 seconds
Started Jun 11 03:02:25 PM PDT 24
Finished Jun 11 04:45:09 PM PDT 24
Peak memory 295428 kb
Host smart-502636fd-580c-48c7-bb41-fb0badd714aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638705096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1638705096
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1966944767
Short name T240
Test name
Test status
Simulation time 690401800 ps
CPU time 19.47 seconds
Started Jun 11 02:29:27 PM PDT 24
Finished Jun 11 02:29:47 PM PDT 24
Peak memory 270504 kb
Host smart-d7c382b1-bb45-46e0-b894-e7e634bef97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966944767 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1966944767
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.4168604377
Short name T3
Test name
Test status
Simulation time 673075300 ps
CPU time 73.07 seconds
Started Jun 11 03:03:10 PM PDT 24
Finished Jun 11 03:04:24 PM PDT 24
Peak memory 260724 kb
Host smart-09b8a9b0-a033-4b8e-a456-d3e56190fc5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168604377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4168604377
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.179907490
Short name T195
Test name
Test status
Simulation time 4239758300 ps
CPU time 49.16 seconds
Started Jun 11 03:13:56 PM PDT 24
Finished Jun 11 03:14:47 PM PDT 24
Peak memory 263468 kb
Host smart-8ebb2551-b6ba-4e4e-a496-1c55f797d84a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179907490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.179907490
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1199117869
Short name T154
Test name
Test status
Simulation time 3080470900 ps
CPU time 305.22 seconds
Started Jun 11 03:00:30 PM PDT 24
Finished Jun 11 03:05:37 PM PDT 24
Peak memory 263812 kb
Host smart-b14a9c92-8876-4d1f-85a3-b9aacba7cd73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199117869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1199117869
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.4221838743
Short name T12
Test name
Test status
Simulation time 125530100 ps
CPU time 14.15 seconds
Started Jun 11 03:03:46 PM PDT 24
Finished Jun 11 03:04:02 PM PDT 24
Peak memory 265372 kb
Host smart-a070861e-50df-4237-a7c5-1700a8d1f83b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221838743 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.4221838743
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.4080927903
Short name T78
Test name
Test status
Simulation time 122998007000 ps
CPU time 997.31 seconds
Started Jun 11 03:01:24 PM PDT 24
Finished Jun 11 03:18:02 PM PDT 24
Peak memory 263736 kb
Host smart-92c4bd16-eec4-49a1-8cd9-8429e1b838f4
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080927903 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.4080927903
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3264893114
Short name T123
Test name
Test status
Simulation time 10012631400 ps
CPU time 319.1 seconds
Started Jun 11 03:09:15 PM PDT 24
Finished Jun 11 03:14:35 PM PDT 24
Peak memory 315492 kb
Host smart-54f16545-ddc3-4b62-bf0e-7d5afe419220
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264893114 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3264893114
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1310821150
Short name T1
Test name
Test status
Simulation time 67586000 ps
CPU time 13.54 seconds
Started Jun 11 03:01:30 PM PDT 24
Finished Jun 11 03:01:45 PM PDT 24
Peak memory 260136 kb
Host smart-7b383d7b-fc18-4e45-9bc7-ba0cd93c87b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310821150 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1310821150
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1802293542
Short name T334
Test name
Test status
Simulation time 16683700 ps
CPU time 13.46 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 260960 kb
Host smart-ed812d29-3204-45eb-8777-11efce6dd449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802293542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1802293542
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.3672366501
Short name T128
Test name
Test status
Simulation time 37551700 ps
CPU time 133.4 seconds
Started Jun 11 03:15:19 PM PDT 24
Finished Jun 11 03:17:34 PM PDT 24
Peak memory 265832 kb
Host smart-2dbc52d7-4bfe-4d63-92c4-dc4255a7fddd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672366501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.3672366501
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1619765048
Short name T35
Test name
Test status
Simulation time 74441078400 ps
CPU time 466.72 seconds
Started Jun 11 03:07:32 PM PDT 24
Finished Jun 11 03:15:20 PM PDT 24
Peak memory 275444 kb
Host smart-4e3132e9-5715-4f4d-bf36-5427b1270200
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619765048 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1619765048
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3648969632
Short name T728
Test name
Test status
Simulation time 133303400 ps
CPU time 129.35 seconds
Started Jun 11 03:15:10 PM PDT 24
Finished Jun 11 03:17:20 PM PDT 24
Peak memory 261372 kb
Host smart-cbeae02d-c69f-4d32-90e6-86c7c80ccddc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648969632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3648969632
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3918019216
Short name T241
Test name
Test status
Simulation time 47944300 ps
CPU time 18.33 seconds
Started Jun 11 02:28:44 PM PDT 24
Finished Jun 11 02:29:03 PM PDT 24
Peak memory 263772 kb
Host smart-44bd9822-1ca5-4b7c-b126-8e9f77b021d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918019216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
918019216
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3584260764
Short name T64
Test name
Test status
Simulation time 2234647800 ps
CPU time 29.87 seconds
Started Jun 11 03:02:00 PM PDT 24
Finished Jun 11 03:02:31 PM PDT 24
Peak memory 263856 kb
Host smart-ac76afca-e7de-4f60-bbae-fadf98228286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584260764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3584260764
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1393836618
Short name T9
Test name
Test status
Simulation time 171299700 ps
CPU time 14.81 seconds
Started Jun 11 03:01:27 PM PDT 24
Finished Jun 11 03:01:43 PM PDT 24
Peak memory 261312 kb
Host smart-51dbe6b6-0b09-40fa-bf34-cbf9c0c162c3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393836618 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1393836618
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.530596671
Short name T391
Test name
Test status
Simulation time 1911202400 ps
CPU time 78.87 seconds
Started Jun 11 03:01:14 PM PDT 24
Finished Jun 11 03:02:34 PM PDT 24
Peak memory 265172 kb
Host smart-cb66f32e-c4ba-4ac2-9acb-10532d3c003e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530596671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.530596671
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.43586524
Short name T148
Test name
Test status
Simulation time 27602600 ps
CPU time 13.45 seconds
Started Jun 11 03:09:44 PM PDT 24
Finished Jun 11 03:10:00 PM PDT 24
Peak memory 265448 kb
Host smart-144de361-2716-412e-8f32-24061ad261e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43586524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.43586524
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1290855319
Short name T45
Test name
Test status
Simulation time 24184600 ps
CPU time 14.28 seconds
Started Jun 11 03:02:36 PM PDT 24
Finished Jun 11 03:02:51 PM PDT 24
Peak memory 280032 kb
Host smart-0d8fa322-811e-47ce-a058-17f7f5918b05
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1290855319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1290855319
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.1437057074
Short name T134
Test name
Test status
Simulation time 81679200 ps
CPU time 131.71 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:17:15 PM PDT 24
Peak memory 260272 kb
Host smart-a7bc811d-7934-4ad4-8376-a1ea3b94c31a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437057074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.1437057074
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.165527509
Short name T136
Test name
Test status
Simulation time 298231958400 ps
CPU time 1983.16 seconds
Started Jun 11 03:03:01 PM PDT 24
Finished Jun 11 03:36:05 PM PDT 24
Peak memory 264300 kb
Host smart-d324f82a-7553-41fb-a5b5-621c99b621fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165527509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_host_ctrl_arb.165527509
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.2699939833
Short name T149
Test name
Test status
Simulation time 2583325800 ps
CPU time 78.26 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:01:00 PM PDT 24
Peak memory 260728 kb
Host smart-9f8d7aed-eaed-4033-b43e-c5f4a7c3eff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699939833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.2699939833
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2494684288
Short name T6
Test name
Test status
Simulation time 48215783800 ps
CPU time 314.77 seconds
Started Jun 11 03:02:26 PM PDT 24
Finished Jun 11 03:07:42 PM PDT 24
Peak memory 292292 kb
Host smart-0b7c2c51-96a8-4986-835e-7bca35da11db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494684288 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.2494684288
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.2110896118
Short name T229
Test name
Test status
Simulation time 85879900 ps
CPU time 37.03 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:45 PM PDT 24
Peak memory 275796 kb
Host smart-7e16311a-274e-45f3-a148-72e5b6c29687
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110896118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.2110896118
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2917860240
Short name T265
Test name
Test status
Simulation time 59062700 ps
CPU time 18.99 seconds
Started Jun 11 02:29:25 PM PDT 24
Finished Jun 11 02:29:45 PM PDT 24
Peak memory 263716 kb
Host smart-7cb5eb0e-c696-44f0-8857-3ba7b57b534f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917860240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2917860240
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.291283429
Short name T44
Test name
Test status
Simulation time 7939030800 ps
CPU time 64.2 seconds
Started Jun 11 03:04:04 PM PDT 24
Finished Jun 11 03:05:09 PM PDT 24
Peak memory 263860 kb
Host smart-fa9da92b-2abc-4917-b52d-7c38db002891
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291283429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.291283429
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1654621787
Short name T238
Test name
Test status
Simulation time 465518000 ps
CPU time 748.57 seconds
Started Jun 11 02:29:08 PM PDT 24
Finished Jun 11 02:41:37 PM PDT 24
Peak memory 263776 kb
Host smart-08718bf7-ca3c-4076-a0cd-3906e248588d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654621787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.1654621787
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1314309125
Short name T244
Test name
Test status
Simulation time 34056300 ps
CPU time 13.55 seconds
Started Jun 11 02:28:37 PM PDT 24
Finished Jun 11 02:28:51 PM PDT 24
Peak memory 262860 kb
Host smart-af7a9db9-d5d3-405b-9be2-6ebc8aa62c60
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314309125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1314309125
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.493781729
Short name T160
Test name
Test status
Simulation time 10038897300 ps
CPU time 53.22 seconds
Started Jun 11 03:10:46 PM PDT 24
Finished Jun 11 03:11:40 PM PDT 24
Peak memory 287296 kb
Host smart-999acd87-c00f-4bf8-85fa-427280530f54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493781729 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.493781729
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.1610664674
Short name T342
Test name
Test status
Simulation time 3459157600 ps
CPU time 190.71 seconds
Started Jun 11 03:11:52 PM PDT 24
Finished Jun 11 03:15:04 PM PDT 24
Peak memory 294468 kb
Host smart-78e1b245-9d42-4f67-8f40-8448602382c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610664674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.1610664674
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3265753463
Short name T164
Test name
Test status
Simulation time 1035541300 ps
CPU time 747.61 seconds
Started Jun 11 02:57:50 PM PDT 24
Finished Jun 11 03:10:18 PM PDT 24
Peak memory 265296 kb
Host smart-b793d27b-e8c9-437c-847d-7ab3a1457926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265753463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3265753463
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3240026767
Short name T307
Test name
Test status
Simulation time 8161219600 ps
CPU time 132.67 seconds
Started Jun 11 03:14:03 PM PDT 24
Finished Jun 11 03:16:16 PM PDT 24
Peak memory 263464 kb
Host smart-00b6b6fc-db3b-48c1-a6ee-8baa315dd57b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240026767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3240026767
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.713119369
Short name T13
Test name
Test status
Simulation time 25922600 ps
CPU time 14.36 seconds
Started Jun 11 03:02:38 PM PDT 24
Finished Jun 11 03:02:54 PM PDT 24
Peak memory 263096 kb
Host smart-df278280-f2e9-406e-b5d9-2c02fff2bb21
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713119369 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.713119369
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3943616413
Short name T819
Test name
Test status
Simulation time 89583400 ps
CPU time 13.63 seconds
Started Jun 11 03:11:14 PM PDT 24
Finished Jun 11 03:11:28 PM PDT 24
Peak memory 265300 kb
Host smart-f064b328-0123-48b4-92b2-538b5e560a35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943616413 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3943616413
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1580435408
Short name T339
Test name
Test status
Simulation time 53881400 ps
CPU time 13.31 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:29:40 PM PDT 24
Peak memory 261044 kb
Host smart-a4940f61-cfee-4d72-9002-2752040d0839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580435408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1580435408
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.951804754
Short name T324
Test name
Test status
Simulation time 17276662300 ps
CPU time 623.33 seconds
Started Jun 11 03:04:46 PM PDT 24
Finished Jun 11 03:15:10 PM PDT 24
Peak memory 314524 kb
Host smart-83eca938-00c2-4adc-a4a9-d1d628723d70
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951804754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.951804754
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.1088017797
Short name T74
Test name
Test status
Simulation time 774112000 ps
CPU time 18.26 seconds
Started Jun 11 03:01:25 PM PDT 24
Finished Jun 11 03:01:44 PM PDT 24
Peak memory 265456 kb
Host smart-b1fb1712-3a5b-4d55-a7e1-29de1e8e2ff7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088017797 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1088017797
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.123729314
Short name T268
Test name
Test status
Simulation time 220600400 ps
CPU time 19.78 seconds
Started Jun 11 02:28:26 PM PDT 24
Finished Jun 11 02:28:46 PM PDT 24
Peak memory 263620 kb
Host smart-373e9b83-e35f-49ed-8ce3-cc9420b876e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123729314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.123729314
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.3303901677
Short name T180
Test name
Test status
Simulation time 13092846900 ps
CPU time 525.34 seconds
Started Jun 11 03:06:26 PM PDT 24
Finished Jun 11 03:15:13 PM PDT 24
Peak memory 309644 kb
Host smart-637cfd5e-73c7-4d46-ac7a-157000d31392
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303901677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.3303901677
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.635775571
Short name T48
Test name
Test status
Simulation time 3118082400 ps
CPU time 26.02 seconds
Started Jun 11 02:59:24 PM PDT 24
Finished Jun 11 02:59:51 PM PDT 24
Peak memory 262756 kb
Host smart-f231ac2a-2e35-479e-97c9-a312d375f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635775571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.635775571
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.683527310
Short name T119
Test name
Test status
Simulation time 41742300 ps
CPU time 130.26 seconds
Started Jun 11 03:13:31 PM PDT 24
Finished Jun 11 03:15:42 PM PDT 24
Peak memory 265316 kb
Host smart-121148d9-3497-4b57-999b-a82afc9f07b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683527310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ot
p_reset.683527310
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.95098467
Short name T216
Test name
Test status
Simulation time 437271100 ps
CPU time 388.33 seconds
Started Jun 11 02:29:36 PM PDT 24
Finished Jun 11 02:36:05 PM PDT 24
Peak memory 263776 kb
Host smart-29826062-01ce-468c-a167-71d8d8f8eaca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95098467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
tl_intg_err.95098467
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.2562074859
Short name T197
Test name
Test status
Simulation time 42549600 ps
CPU time 22.29 seconds
Started Jun 11 03:13:31 PM PDT 24
Finished Jun 11 03:13:54 PM PDT 24
Peak memory 265760 kb
Host smart-41a1ed69-f872-45e8-a64b-b4c57565a542
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562074859 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.2562074859
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2138672185
Short name T191
Test name
Test status
Simulation time 723953200 ps
CPU time 2367.32 seconds
Started Jun 11 02:57:51 PM PDT 24
Finished Jun 11 03:37:19 PM PDT 24
Peak memory 263916 kb
Host smart-fa00f41f-8335-413c-b899-571e353fef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138672185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2138672185
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1786472815
Short name T246
Test name
Test status
Simulation time 43254600 ps
CPU time 13.29 seconds
Started Jun 11 02:28:35 PM PDT 24
Finished Jun 11 02:28:49 PM PDT 24
Peak memory 262012 kb
Host smart-dda9f07e-e34e-4e11-91b5-9896fea7ddca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786472815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.1786472815
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1867374298
Short name T277
Test name
Test status
Simulation time 955431300 ps
CPU time 455.07 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:36:21 PM PDT 24
Peak memory 263768 kb
Host smart-b7bf0cc5-6fbb-4b09-932a-aee47bdcbf94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867374298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1867374298
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.102203576
Short name T851
Test name
Test status
Simulation time 48553200 ps
CPU time 14.18 seconds
Started Jun 11 03:07:46 PM PDT 24
Finished Jun 11 03:08:01 PM PDT 24
Peak memory 259672 kb
Host smart-a9739ab8-f4b5-4923-a8a9-0644e497cba1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102203576 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.102203576
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.2557373343
Short name T406
Test name
Test status
Simulation time 11952856800 ps
CPU time 71.39 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:10:56 PM PDT 24
Peak memory 263392 kb
Host smart-85ad2602-9f12-456d-a077-dc0db1797a25
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557373343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2
557373343
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.3856397398
Short name T50
Test name
Test status
Simulation time 94777500 ps
CPU time 31.25 seconds
Started Jun 11 03:07:15 PM PDT 24
Finished Jun 11 03:07:47 PM PDT 24
Peak memory 275804 kb
Host smart-f44dcc66-7b05-4c1d-a6a0-e1dd93056546
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856397398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.3856397398
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1624108288
Short name T203
Test name
Test status
Simulation time 25002100 ps
CPU time 13.88 seconds
Started Jun 11 03:12:17 PM PDT 24
Finished Jun 11 03:12:32 PM PDT 24
Peak memory 274980 kb
Host smart-3c0d5a71-7669-4e33-b7be-2127ec649f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624108288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1624108288
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.709409358
Short name T323
Test name
Test status
Simulation time 138825400 ps
CPU time 31.15 seconds
Started Jun 11 03:07:41 PM PDT 24
Finished Jun 11 03:08:13 PM PDT 24
Peak memory 275816 kb
Host smart-60d05ecf-b898-4563-96d2-f39f767b1ac7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709409358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.709409358
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.3481301392
Short name T738
Test name
Test status
Simulation time 422051900 ps
CPU time 122.39 seconds
Started Jun 11 03:10:58 PM PDT 24
Finished Jun 11 03:13:02 PM PDT 24
Peak memory 294368 kb
Host smart-6e3a8b74-dc2b-4ce5-bfab-9b6f65ab0ba6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481301392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.3481301392
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3831944086
Short name T278
Test name
Test status
Simulation time 1967864600 ps
CPU time 134.97 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:14:53 PM PDT 24
Peak memory 294428 kb
Host smart-3ba6c99e-9e62-456f-b2a3-a12f63f78799
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831944086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3831944086
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2617640203
Short name T155
Test name
Test status
Simulation time 24744300 ps
CPU time 13.87 seconds
Started Jun 11 03:01:27 PM PDT 24
Finished Jun 11 03:01:42 PM PDT 24
Peak memory 265920 kb
Host smart-c0a6a80a-3fc0-4543-8021-371c35bd5b37
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617640203 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2617640203
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3306284721
Short name T260
Test name
Test status
Simulation time 132397600 ps
CPU time 16.95 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:35 PM PDT 24
Peak memory 263700 kb
Host smart-7530bbbb-26de-4518-8a16-e39d15c62e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306284721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
3306284721
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.3112011407
Short name T15
Test name
Test status
Simulation time 2176531700 ps
CPU time 6275.31 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 04:44:39 PM PDT 24
Peak memory 293240 kb
Host smart-cef2e362-3b68-4134-aaff-e0dff08a2a22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112011407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3112011407
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1103410888
Short name T17
Test name
Test status
Simulation time 25505000 ps
CPU time 13.73 seconds
Started Jun 11 02:58:52 PM PDT 24
Finished Jun 11 02:59:07 PM PDT 24
Peak memory 258888 kb
Host smart-2280d7af-d1ad-4e59-a665-40757057e535
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103410888 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1103410888
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.866145488
Short name T163
Test name
Test status
Simulation time 10033590400 ps
CPU time 52.73 seconds
Started Jun 11 03:09:53 PM PDT 24
Finished Jun 11 03:10:47 PM PDT 24
Peak memory 274316 kb
Host smart-19de6919-8ff8-4456-a29a-690694e777ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866145488 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.866145488
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2662262415
Short name T366
Test name
Test status
Simulation time 855336900 ps
CPU time 458.24 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:37:38 PM PDT 24
Peak memory 263788 kb
Host smart-152d617b-438a-482f-980d-77bf96ee5c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662262415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2662262415
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1794615559
Short name T365
Test name
Test status
Simulation time 349082200 ps
CPU time 911.48 seconds
Started Jun 11 02:28:44 PM PDT 24
Finished Jun 11 02:43:56 PM PDT 24
Peak memory 263720 kb
Host smart-254ad102-d975-4d5f-9357-dd417e9ffe17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794615559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.1794615559
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2374702624
Short name T320
Test name
Test status
Simulation time 82056200 ps
CPU time 30.5 seconds
Started Jun 11 03:08:13 PM PDT 24
Finished Jun 11 03:08:45 PM PDT 24
Peak memory 275188 kb
Host smart-be4436ba-5bbf-4ab9-9828-37271ba0ec3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374702624 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2374702624
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1013755082
Short name T395
Test name
Test status
Simulation time 1365075000 ps
CPU time 73.08 seconds
Started Jun 11 03:08:25 PM PDT 24
Finished Jun 11 03:09:39 PM PDT 24
Peak memory 265520 kb
Host smart-f0de4edc-7a29-4b2b-9c65-63b6244b801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013755082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1013755082
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1746835425
Short name T275
Test name
Test status
Simulation time 1488060400 ps
CPU time 67.44 seconds
Started Jun 11 03:11:51 PM PDT 24
Finished Jun 11 03:12:59 PM PDT 24
Peak memory 263896 kb
Host smart-c180a729-bdaa-4082-9648-7cd8f7426dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746835425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1746835425
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2872665280
Short name T386
Test name
Test status
Simulation time 827575400 ps
CPU time 70.82 seconds
Started Jun 11 03:13:09 PM PDT 24
Finished Jun 11 03:14:21 PM PDT 24
Peak memory 263972 kb
Host smart-a5ecc44a-65ba-410a-80dc-07749f74ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872665280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2872665280
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2335099713
Short name T321
Test name
Test status
Simulation time 34331000 ps
CPU time 30.89 seconds
Started Jun 11 03:13:45 PM PDT 24
Finished Jun 11 03:14:16 PM PDT 24
Peak memory 270580 kb
Host smart-ea8bd1f2-4fa6-48f2-8ffe-f2eb2d57bf01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335099713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2335099713
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.733948512
Short name T281
Test name
Test status
Simulation time 77632900 ps
CPU time 27.4 seconds
Started Jun 11 03:14:06 PM PDT 24
Finished Jun 11 03:14:34 PM PDT 24
Peak memory 275216 kb
Host smart-b86b3aec-6567-4934-bbb8-1f8b8cf0aeba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733948512 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.733948512
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1517731014
Short name T387
Test name
Test status
Simulation time 3237192200 ps
CPU time 71.18 seconds
Started Jun 11 03:14:33 PM PDT 24
Finished Jun 11 03:15:45 PM PDT 24
Peak memory 263932 kb
Host smart-91b0561e-8e98-46fb-a3b0-1f333972812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517731014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1517731014
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1195236691
Short name T90
Test name
Test status
Simulation time 42963337200 ps
CPU time 680.72 seconds
Started Jun 11 02:57:54 PM PDT 24
Finished Jun 11 03:09:16 PM PDT 24
Peak memory 274856 kb
Host smart-6e3eef31-f44b-4ded-bba7-cb54bab1396d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195236691 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1195236691
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.53159667
Short name T63
Test name
Test status
Simulation time 1692771600 ps
CPU time 196.24 seconds
Started Jun 11 03:03:29 PM PDT 24
Finished Jun 11 03:06:46 PM PDT 24
Peak memory 282184 kb
Host smart-6ad90e5a-2ffc-4d85-b7e0-b7d9eebe748a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53159667 -assert nopo
stproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.53159667
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.467160091
Short name T75
Test name
Test status
Simulation time 815512100 ps
CPU time 17.16 seconds
Started Jun 11 03:00:15 PM PDT 24
Finished Jun 11 03:00:33 PM PDT 24
Peak memory 262156 kb
Host smart-2949cc83-5087-4cec-831a-c9e630f4deba
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467160091 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.467160091
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3205233070
Short name T72
Test name
Test status
Simulation time 825779000 ps
CPU time 18.54 seconds
Started Jun 11 03:02:36 PM PDT 24
Finished Jun 11 03:02:55 PM PDT 24
Peak memory 263600 kb
Host smart-340beb3a-703a-4f5f-b225-70b0afd5249c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205233070 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3205233070
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1088715578
Short name T374
Test name
Test status
Simulation time 14186400 ps
CPU time 21.96 seconds
Started Jun 11 03:12:39 PM PDT 24
Finished Jun 11 03:13:02 PM PDT 24
Peak memory 273976 kb
Host smart-38b2c5d9-1d39-4bbb-b8e3-3bdd095e498b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088715578 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1088715578
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.4271738847
Short name T284
Test name
Test status
Simulation time 619520800 ps
CPU time 138.34 seconds
Started Jun 11 03:08:05 PM PDT 24
Finished Jun 11 03:10:25 PM PDT 24
Peak memory 294660 kb
Host smart-f9035978-f80c-4a18-8ed2-732c3d687156
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271738847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.4271738847
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.1942429809
Short name T340
Test name
Test status
Simulation time 7606907800 ps
CPU time 260.51 seconds
Started Jun 11 03:11:23 PM PDT 24
Finished Jun 11 03:15:45 PM PDT 24
Peak memory 285104 kb
Host smart-8fd8e023-aa47-4e14-8de8-7d47a37a4386
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942429809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.1942429809
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.1263311715
Short name T178
Test name
Test status
Simulation time 20500100 ps
CPU time 14.04 seconds
Started Jun 11 03:02:34 PM PDT 24
Finished Jun 11 03:02:49 PM PDT 24
Peak memory 261620 kb
Host smart-47066a37-2f3a-4a63-9474-dec2a9cc2e3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263311715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.1263311715
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.2907048550
Short name T507
Test name
Test status
Simulation time 1811247400 ps
CPU time 65.44 seconds
Started Jun 11 02:59:49 PM PDT 24
Finished Jun 11 03:00:55 PM PDT 24
Peak memory 260808 kb
Host smart-762de9ff-0b29-43a7-81f3-91d7872d24bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907048550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.2907048550
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1345077123
Short name T168
Test name
Test status
Simulation time 2060659000 ps
CPU time 129.73 seconds
Started Jun 11 03:01:06 PM PDT 24
Finished Jun 11 03:03:16 PM PDT 24
Peak memory 282260 kb
Host smart-c707d5a1-b779-4f78-a6c5-24c52e31d30c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1345077123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1345077123
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.524294812
Short name T361
Test name
Test status
Simulation time 1421073200 ps
CPU time 899.33 seconds
Started Jun 11 02:28:22 PM PDT 24
Finished Jun 11 02:43:23 PM PDT 24
Peak memory 263780 kb
Host smart-4dea233f-c7ac-49b3-b3fb-477ec74e3762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524294812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.524294812
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3053087467
Short name T770
Test name
Test status
Simulation time 11101400 ps
CPU time 22.02 seconds
Started Jun 11 02:58:36 PM PDT 24
Finished Jun 11 02:58:59 PM PDT 24
Peak memory 274092 kb
Host smart-d753a64d-69d5-494e-bd6c-85df21b73a2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053087467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3053087467
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1990946937
Short name T326
Test name
Test status
Simulation time 82809500 ps
CPU time 28.4 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 03:00:31 PM PDT 24
Peak memory 268364 kb
Host smart-17ceb041-7ffa-4ee8-862b-177783cca4ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990946937 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1990946937
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.1490279954
Short name T11
Test name
Test status
Simulation time 39626300 ps
CPU time 21.86 seconds
Started Jun 11 03:07:42 PM PDT 24
Finished Jun 11 03:08:05 PM PDT 24
Peak memory 274080 kb
Host smart-0fdae7a6-0874-4585-9bdf-c913b55d9d95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490279954 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.1490279954
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.975761037
Short name T25
Test name
Test status
Simulation time 160153874100 ps
CPU time 857.78 seconds
Started Jun 11 03:07:30 PM PDT 24
Finished Jun 11 03:21:49 PM PDT 24
Peak memory 264608 kb
Host smart-6f3d1a41-c53b-4a28-892d-19d1e30a9091
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975761037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.975761037
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.96058266
Short name T167
Test name
Test status
Simulation time 27665100 ps
CPU time 28.43 seconds
Started Jun 11 03:08:40 PM PDT 24
Finished Jun 11 03:09:09 PM PDT 24
Peak memory 268192 kb
Host smart-4139a267-26c4-4bf6-9656-1c51b9fd5e31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96058266 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.96058266
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2110326023
Short name T394
Test name
Test status
Simulation time 2169798800 ps
CPU time 60.64 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:12:35 PM PDT 24
Peak memory 264652 kb
Host smart-09a79b56-627c-4025-adbb-77d5d752007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110326023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2110326023
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2481237859
Short name T371
Test name
Test status
Simulation time 12855900 ps
CPU time 21.73 seconds
Started Jun 11 03:11:51 PM PDT 24
Finished Jun 11 03:12:13 PM PDT 24
Peak memory 273972 kb
Host smart-0aa73230-b07d-4bbe-860c-27b6edd9b25d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481237859 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2481237859
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3392975435
Short name T839
Test name
Test status
Simulation time 10947400 ps
CPU time 21.66 seconds
Started Jun 11 03:12:51 PM PDT 24
Finished Jun 11 03:13:14 PM PDT 24
Peak memory 273996 kb
Host smart-f4f2d469-f592-4c9a-af4d-97876580e55a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392975435 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3392975435
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3304761557
Short name T400
Test name
Test status
Simulation time 1689200400 ps
CPU time 69.85 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:06:18 PM PDT 24
Peak memory 263612 kb
Host smart-b3ad7efb-90fa-463d-af08-e4ac223ed208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304761557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3304761557
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1426431875
Short name T376
Test name
Test status
Simulation time 15494600 ps
CPU time 20.56 seconds
Started Jun 11 03:06:44 PM PDT 24
Finished Jun 11 03:07:07 PM PDT 24
Peak memory 265900 kb
Host smart-f8de8d65-8966-47e0-a803-0d25614cbb24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426431875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1426431875
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2746754671
Short name T120
Test name
Test status
Simulation time 75332200 ps
CPU time 131.15 seconds
Started Jun 11 03:11:45 PM PDT 24
Finished Jun 11 03:13:56 PM PDT 24
Peak memory 265412 kb
Host smart-08728696-f655-46bb-8f50-7ca8237ecfa0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746754671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2746754671
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3808960867
Short name T22
Test name
Test status
Simulation time 24253200 ps
CPU time 14.06 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 02:59:00 PM PDT 24
Peak memory 265712 kb
Host smart-8e1321f5-1f6a-4052-9c5b-951d534415f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808960867 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3808960867
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1772815767
Short name T20
Test name
Test status
Simulation time 15017000 ps
CPU time 13.43 seconds
Started Jun 11 03:01:29 PM PDT 24
Finished Jun 11 03:01:43 PM PDT 24
Peak memory 261488 kb
Host smart-f14a3ae0-f7d3-4221-ade0-e7006c0165e8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1772815767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1772815767
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4155033309
Short name T4
Test name
Test status
Simulation time 56274000 ps
CPU time 31.23 seconds
Started Jun 11 03:08:57 PM PDT 24
Finished Jun 11 03:09:29 PM PDT 24
Peak memory 276044 kb
Host smart-139abe6a-d093-4c87-931d-d0e03617ccf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155033309 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4155033309
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3547143065
Short name T1157
Test name
Test status
Simulation time 227772900 ps
CPU time 19.2 seconds
Started Jun 11 02:28:37 PM PDT 24
Finished Jun 11 02:28:57 PM PDT 24
Peak memory 263784 kb
Host smart-b1fcaf7b-37f4-417d-b5f3-03f294e0b2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547143065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
547143065
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2784111537
Short name T276
Test name
Test status
Simulation time 429155400 ps
CPU time 462.72 seconds
Started Jun 11 02:30:00 PM PDT 24
Finished Jun 11 02:37:44 PM PDT 24
Peak memory 263764 kb
Host smart-2431e73d-25ae-46a4-9973-77aaa332f275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784111537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.2784111537
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2525009013
Short name T89
Test name
Test status
Simulation time 3707306800 ps
CPU time 2334.69 seconds
Started Jun 11 02:57:58 PM PDT 24
Finished Jun 11 03:36:54 PM PDT 24
Peak memory 265460 kb
Host smart-631e389a-a501-49b0-9ff4-0d1e29b487b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525009013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2525009013
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.1952442512
Short name T66
Test name
Test status
Simulation time 536177800 ps
CPU time 24.49 seconds
Started Jun 11 02:57:50 PM PDT 24
Finished Jun 11 02:58:15 PM PDT 24
Peak memory 263916 kb
Host smart-8cda02ba-04bd-4726-ba13-a2b094ff4f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952442512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.1952442512
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2336120686
Short name T193
Test name
Test status
Simulation time 104893203200 ps
CPU time 327.66 seconds
Started Jun 11 02:58:26 PM PDT 24
Finished Jun 11 03:03:54 PM PDT 24
Peak memory 293476 kb
Host smart-d183513b-fea3-4b07-b27d-d02d4e53e6f4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336120686 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2336120686
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1145795055
Short name T73
Test name
Test status
Simulation time 856036000 ps
CPU time 22.88 seconds
Started Jun 11 02:58:54 PM PDT 24
Finished Jun 11 02:59:18 PM PDT 24
Peak memory 265952 kb
Host smart-72d09b21-008b-450c-a78f-0a5e48e88260
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145795055 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1145795055
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1577774036
Short name T233
Test name
Test status
Simulation time 1465931700 ps
CPU time 150.09 seconds
Started Jun 11 02:57:31 PM PDT 24
Finished Jun 11 03:00:02 PM PDT 24
Peak memory 263036 kb
Host smart-60a53503-5adc-4f5d-8b15-c2524c19a199
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577774036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1577774036
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.3120702148
Short name T107
Test name
Test status
Simulation time 48915990800 ps
CPU time 4207.81 seconds
Started Jun 11 02:59:23 PM PDT 24
Finished Jun 11 04:09:33 PM PDT 24
Peak memory 265488 kb
Host smart-bbfac8c2-4c7e-4c39-9492-1493441b9db4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120702148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.3120702148
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.1527671452
Short name T221
Test name
Test status
Simulation time 73818800 ps
CPU time 129.59 seconds
Started Jun 11 03:03:54 PM PDT 24
Finished Jun 11 03:06:05 PM PDT 24
Peak memory 260440 kb
Host smart-1c3a699f-b9e7-4d25-b051-975f6e60c4c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527671452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.1527671452
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4042198199
Short name T1127
Test name
Test status
Simulation time 6668328700 ps
CPU time 59 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 261288 kb
Host smart-885fbc2b-0eec-402f-b4be-9ef59269a21c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042198199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.4042198199
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2859240146
Short name T1179
Test name
Test status
Simulation time 6431669300 ps
CPU time 81.88 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:29:59 PM PDT 24
Peak memory 261224 kb
Host smart-3cd3f9c9-3c4d-4bc1-a369-ad1ef9a92634
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859240146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.2859240146
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3928939767
Short name T1181
Test name
Test status
Simulation time 88198000 ps
CPU time 45.02 seconds
Started Jun 11 02:28:35 PM PDT 24
Finished Jun 11 02:29:21 PM PDT 24
Peak memory 261276 kb
Host smart-8a82ba0a-0cfc-4e96-8c4a-4aa67e550760
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928939767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.3928939767
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.228593002
Short name T1225
Test name
Test status
Simulation time 109180800 ps
CPU time 19.12 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:28:56 PM PDT 24
Peak memory 277620 kb
Host smart-8c32e219-5dba-4c5a-b0b2-07a200f11507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228593002 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.228593002
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3280424385
Short name T1097
Test name
Test status
Simulation time 53871500 ps
CPU time 14.63 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:28:52 PM PDT 24
Peak memory 263772 kb
Host smart-fb7c8a38-98f3-49e0-a66c-aa4db954b47b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280424385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3280424385
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2401696971
Short name T1145
Test name
Test status
Simulation time 14549700 ps
CPU time 13.58 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:28:38 PM PDT 24
Peak memory 261056 kb
Host smart-a9912610-5d57-408b-8694-76c8d699e8da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401696971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2
401696971
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.824815892
Short name T1094
Test name
Test status
Simulation time 64025000 ps
CPU time 13.48 seconds
Started Jun 11 02:28:24 PM PDT 24
Finished Jun 11 02:28:38 PM PDT 24
Peak memory 261116 kb
Host smart-5e800042-a5f0-4259-923d-b05cd8ed6992
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824815892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem
_walk.824815892
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.927943303
Short name T1100
Test name
Test status
Simulation time 155423900 ps
CPU time 16.39 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:28:53 PM PDT 24
Peak memory 262444 kb
Host smart-89a4c379-66aa-4ba7-a132-f29555ef3650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927943303 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.927943303
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2273218430
Short name T1096
Test name
Test status
Simulation time 11609200 ps
CPU time 16.03 seconds
Started Jun 11 02:28:25 PM PDT 24
Finished Jun 11 02:28:42 PM PDT 24
Peak memory 252956 kb
Host smart-1b9afbe2-e8ee-474a-a138-c406f26b860e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273218430 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2273218430
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.132772766
Short name T1233
Test name
Test status
Simulation time 66102100 ps
CPU time 15.65 seconds
Started Jun 11 02:28:23 PM PDT 24
Finished Jun 11 02:28:39 PM PDT 24
Peak memory 252880 kb
Host smart-e7563360-2c79-4d89-9260-9e6992c7eedd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132772766 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.132772766
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1577104469
Short name T1177
Test name
Test status
Simulation time 439550200 ps
CPU time 48.11 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:29:25 PM PDT 24
Peak memory 261288 kb
Host smart-47536d76-f3d5-431d-9052-b559c86a329d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577104469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1577104469
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1149555679
Short name T1110
Test name
Test status
Simulation time 1277363900 ps
CPU time 36.05 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:29:13 PM PDT 24
Peak memory 261284 kb
Host smart-f13c1439-8128-4c0c-9f28-97a0d7554f37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149555679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1149555679
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.73411676
Short name T1188
Test name
Test status
Simulation time 39837800 ps
CPU time 31.02 seconds
Started Jun 11 02:28:37 PM PDT 24
Finished Jun 11 02:29:09 PM PDT 24
Peak memory 261216 kb
Host smart-577664fb-ceaf-4c9c-942b-4131d66730dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73411676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_csr_hw_reset.73411676
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.597901523
Short name T201
Test name
Test status
Simulation time 158190800 ps
CPU time 19.13 seconds
Started Jun 11 02:28:46 PM PDT 24
Finished Jun 11 02:29:06 PM PDT 24
Peak memory 278088 kb
Host smart-d0e95407-d090-4d5f-bfef-1cf4f3122780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597901523 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.597901523
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1215688761
Short name T298
Test name
Test status
Simulation time 144591500 ps
CPU time 16.64 seconds
Started Jun 11 02:28:35 PM PDT 24
Finished Jun 11 02:28:52 PM PDT 24
Peak memory 263744 kb
Host smart-e32c9ae7-b067-4286-986c-f572de40a5e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215688761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1215688761
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2750352106
Short name T336
Test name
Test status
Simulation time 16944000 ps
CPU time 13.36 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:28:50 PM PDT 24
Peak memory 260952 kb
Host smart-ebeef610-a088-4b7d-ac0d-627ed8a148e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750352106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2
750352106
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.290975796
Short name T1113
Test name
Test status
Simulation time 256811300 ps
CPU time 13.27 seconds
Started Jun 11 02:28:36 PM PDT 24
Finished Jun 11 02:28:50 PM PDT 24
Peak memory 261152 kb
Host smart-efe172ff-bb8e-4888-b203-315cc0baa855
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290975796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.290975796
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.431558771
Short name T1231
Test name
Test status
Simulation time 353965800 ps
CPU time 18.43 seconds
Started Jun 11 02:28:37 PM PDT 24
Finished Jun 11 02:28:56 PM PDT 24
Peak memory 262940 kb
Host smart-9c9a3de3-560d-4169-99c2-681fccdcc692
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431558771 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.431558771
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.981052515
Short name T1093
Test name
Test status
Simulation time 42204700 ps
CPU time 13.13 seconds
Started Jun 11 02:28:34 PM PDT 24
Finished Jun 11 02:28:47 PM PDT 24
Peak memory 253032 kb
Host smart-ecfe5692-3a18-4fbb-9dac-6c58e5b4d29b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981052515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.981052515
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1595641909
Short name T1095
Test name
Test status
Simulation time 42842300 ps
CPU time 16.06 seconds
Started Jun 11 02:28:35 PM PDT 24
Finished Jun 11 02:28:51 PM PDT 24
Peak memory 252888 kb
Host smart-43ac73c9-a99a-4e03-a520-0646a58b5c46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595641909 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1595641909
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1268566256
Short name T364
Test name
Test status
Simulation time 1915736900 ps
CPU time 752.26 seconds
Started Jun 11 02:28:35 PM PDT 24
Finished Jun 11 02:41:08 PM PDT 24
Peak memory 263768 kb
Host smart-4b961a30-907c-42ae-a465-40168cb51000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268566256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1268566256
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.580066421
Short name T1190
Test name
Test status
Simulation time 103273100 ps
CPU time 16.53 seconds
Started Jun 11 02:29:25 PM PDT 24
Finished Jun 11 02:29:43 PM PDT 24
Peak memory 272008 kb
Host smart-14eded88-ff23-4c03-a462-1f1c5b571489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580066421 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.580066421
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1838406613
Short name T1209
Test name
Test status
Simulation time 78938000 ps
CPU time 16.76 seconds
Started Jun 11 02:29:25 PM PDT 24
Finished Jun 11 02:29:42 PM PDT 24
Peak memory 261196 kb
Host smart-4ed7449c-f14f-4ce8-8894-5d5762f7e6de
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838406613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.1838406613
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3381741595
Short name T1146
Test name
Test status
Simulation time 16900000 ps
CPU time 13.87 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:29:41 PM PDT 24
Peak memory 261096 kb
Host smart-e9d7c96f-b630-429e-a193-cac536b1a1f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381741595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
3381741595
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3165283129
Short name T1129
Test name
Test status
Simulation time 64849600 ps
CPU time 20.26 seconds
Started Jun 11 02:29:27 PM PDT 24
Finished Jun 11 02:29:48 PM PDT 24
Peak memory 263076 kb
Host smart-cfcb77de-3099-4f32-92b4-bfa05268710a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165283129 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3165283129
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3417753471
Short name T1141
Test name
Test status
Simulation time 36260800 ps
CPU time 15.49 seconds
Started Jun 11 02:29:25 PM PDT 24
Finished Jun 11 02:29:41 PM PDT 24
Peak memory 252996 kb
Host smart-e0af1f76-a828-49d1-80af-df241d5bdfc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417753471 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3417753471
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.398762088
Short name T1202
Test name
Test status
Simulation time 12028700 ps
CPU time 15.89 seconds
Started Jun 11 02:29:27 PM PDT 24
Finished Jun 11 02:29:44 PM PDT 24
Peak memory 252956 kb
Host smart-be3f29e2-f607-4f9b-9b09-d2041acef377
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398762088 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.398762088
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4227311379
Short name T359
Test name
Test status
Simulation time 340780200 ps
CPU time 459.3 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:37:06 PM PDT 24
Peak memory 263740 kb
Host smart-66a1f5d1-5a87-4c5c-89d6-a037a2c59d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227311379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.4227311379
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.994651794
Short name T1158
Test name
Test status
Simulation time 29257000 ps
CPU time 16.58 seconds
Started Jun 11 02:29:27 PM PDT 24
Finished Jun 11 02:29:44 PM PDT 24
Peak memory 263732 kb
Host smart-8aea28c4-f60f-4bb7-a397-d22a72f14ea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994651794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.994651794
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.699444371
Short name T1159
Test name
Test status
Simulation time 67883300 ps
CPU time 16.8 seconds
Started Jun 11 02:29:28 PM PDT 24
Finished Jun 11 02:29:45 PM PDT 24
Peak memory 262972 kb
Host smart-49ec414b-8a2d-4e82-9292-9eff20e75e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699444371 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.699444371
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1635010804
Short name T1134
Test name
Test status
Simulation time 31472400 ps
CPU time 15.58 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:29:43 PM PDT 24
Peak memory 252876 kb
Host smart-7bebdc02-5f86-4b51-8df8-d9f9e3e86267
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635010804 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.1635010804
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3606587943
Short name T1210
Test name
Test status
Simulation time 15242200 ps
CPU time 16.01 seconds
Started Jun 11 02:29:25 PM PDT 24
Finished Jun 11 02:29:42 PM PDT 24
Peak memory 252948 kb
Host smart-4171e896-95b1-49d4-8bad-17ff119f5f58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606587943 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3606587943
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3155955321
Short name T367
Test name
Test status
Simulation time 355507100 ps
CPU time 382.44 seconds
Started Jun 11 02:29:24 PM PDT 24
Finished Jun 11 02:35:47 PM PDT 24
Peak memory 263792 kb
Host smart-a39a19bd-3a0c-40f8-99cc-1df25857fbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155955321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.3155955321
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4151147737
Short name T299
Test name
Test status
Simulation time 101549900 ps
CPU time 16.97 seconds
Started Jun 11 02:29:39 PM PDT 24
Finished Jun 11 02:29:56 PM PDT 24
Peak memory 277600 kb
Host smart-0e16a0e3-88ff-47ed-983a-0a5bbdd4e3a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151147737 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.4151147737
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.508896019
Short name T219
Test name
Test status
Simulation time 32958400 ps
CPU time 16.82 seconds
Started Jun 11 02:29:37 PM PDT 24
Finished Jun 11 02:29:54 PM PDT 24
Peak memory 263688 kb
Host smart-710d412f-6c76-42da-aada-289ec13a578f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508896019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_csr_rw.508896019
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3400429969
Short name T1135
Test name
Test status
Simulation time 57024500 ps
CPU time 13.49 seconds
Started Jun 11 02:29:36 PM PDT 24
Finished Jun 11 02:29:50 PM PDT 24
Peak memory 261084 kb
Host smart-d690b151-d201-4f97-8434-c508122b22f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400429969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3400429969
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1419299099
Short name T1212
Test name
Test status
Simulation time 37025400 ps
CPU time 17.84 seconds
Started Jun 11 02:29:38 PM PDT 24
Finished Jun 11 02:29:56 PM PDT 24
Peak memory 263480 kb
Host smart-1e11ccac-c5c2-4b98-8d48-67dcd06e2bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419299099 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.1419299099
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3660021844
Short name T1136
Test name
Test status
Simulation time 72689900 ps
CPU time 13.58 seconds
Started Jun 11 02:29:37 PM PDT 24
Finished Jun 11 02:29:52 PM PDT 24
Peak memory 252976 kb
Host smart-194ee6ea-daa5-48a7-8a3b-b5579988bfc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660021844 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3660021844
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2169263947
Short name T1178
Test name
Test status
Simulation time 56088000 ps
CPU time 15.49 seconds
Started Jun 11 02:29:38 PM PDT 24
Finished Jun 11 02:29:54 PM PDT 24
Peak memory 252964 kb
Host smart-51ed69bc-c049-4ac0-ad39-1efb410a6be1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169263947 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2169263947
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2905612477
Short name T356
Test name
Test status
Simulation time 57225000 ps
CPU time 18.02 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:29:45 PM PDT 24
Peak memory 263708 kb
Host smart-33239918-75d6-45e7-a985-c579ba378ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905612477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2905612477
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1544092468
Short name T358
Test name
Test status
Simulation time 369158200 ps
CPU time 454.37 seconds
Started Jun 11 02:29:26 PM PDT 24
Finished Jun 11 02:37:01 PM PDT 24
Peak memory 263700 kb
Host smart-08747ab0-fe09-4cc6-8360-07f94431b23a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544092468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1544092468
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.419879419
Short name T239
Test name
Test status
Simulation time 60463300 ps
CPU time 15.81 seconds
Started Jun 11 02:29:37 PM PDT 24
Finished Jun 11 02:29:53 PM PDT 24
Peak memory 270392 kb
Host smart-0dccd991-4d3a-4c6d-b2c0-c04e1098c1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419879419 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.419879419
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1676581935
Short name T1201
Test name
Test status
Simulation time 55275000 ps
CPU time 14.86 seconds
Started Jun 11 02:29:36 PM PDT 24
Finished Jun 11 02:29:52 PM PDT 24
Peak memory 263776 kb
Host smart-085bde4e-3fd6-4da3-a6ac-8650d27ea89f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676581935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.1676581935
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.674198519
Short name T1142
Test name
Test status
Simulation time 27874900 ps
CPU time 13.4 seconds
Started Jun 11 02:29:36 PM PDT 24
Finished Jun 11 02:29:50 PM PDT 24
Peak memory 261156 kb
Host smart-02329847-146a-49f3-91e2-436efae246af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674198519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.674198519
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.364834845
Short name T1211
Test name
Test status
Simulation time 83652000 ps
CPU time 18.47 seconds
Started Jun 11 02:29:37 PM PDT 24
Finished Jun 11 02:29:56 PM PDT 24
Peak memory 263168 kb
Host smart-5e1fa76c-8c06-4303-95b8-a923a1851073
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364834845 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.364834845
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2386229013
Short name T1152
Test name
Test status
Simulation time 12676100 ps
CPU time 15.67 seconds
Started Jun 11 02:29:35 PM PDT 24
Finished Jun 11 02:29:52 PM PDT 24
Peak memory 253024 kb
Host smart-1d38ca15-43bf-453a-b510-330b2bd52c7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386229013 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2386229013
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.295883372
Short name T1091
Test name
Test status
Simulation time 42442500 ps
CPU time 15.63 seconds
Started Jun 11 02:29:36 PM PDT 24
Finished Jun 11 02:29:53 PM PDT 24
Peak memory 252828 kb
Host smart-c8d922d9-a0b0-4f03-bf84-21d604325f1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295883372 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.295883372
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3935481649
Short name T357
Test name
Test status
Simulation time 34097200 ps
CPU time 16.49 seconds
Started Jun 11 02:29:39 PM PDT 24
Finished Jun 11 02:29:56 PM PDT 24
Peak memory 263752 kb
Host smart-3e509c39-a219-4a49-9208-6403a63c2a73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935481649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3935481649
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3818862992
Short name T1173
Test name
Test status
Simulation time 97131400 ps
CPU time 18.3 seconds
Started Jun 11 02:29:49 PM PDT 24
Finished Jun 11 02:30:08 PM PDT 24
Peak memory 271872 kb
Host smart-3804c59a-ad35-4ee0-8ef4-3b981d13cfe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818862992 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3818862992
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3342003019
Short name T1122
Test name
Test status
Simulation time 18004800 ps
CPU time 16.24 seconds
Started Jun 11 02:29:53 PM PDT 24
Finished Jun 11 02:30:10 PM PDT 24
Peak memory 263744 kb
Host smart-5b0c2bf0-c572-4058-bcc0-88398944903a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342003019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3342003019
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2751261281
Short name T1115
Test name
Test status
Simulation time 68585000 ps
CPU time 13.63 seconds
Started Jun 11 02:29:49 PM PDT 24
Finished Jun 11 02:30:03 PM PDT 24
Peak memory 261084 kb
Host smart-3ab8827e-b9fb-43a4-b194-7e7ab69aede9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751261281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2751261281
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2047203168
Short name T1111
Test name
Test status
Simulation time 229934700 ps
CPU time 33.94 seconds
Started Jun 11 02:29:53 PM PDT 24
Finished Jun 11 02:30:28 PM PDT 24
Peak memory 261220 kb
Host smart-1b20ec30-ec78-486d-845d-469aef060f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047203168 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2047203168
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3379594027
Short name T1219
Test name
Test status
Simulation time 24204400 ps
CPU time 15.23 seconds
Started Jun 11 02:29:38 PM PDT 24
Finished Jun 11 02:29:54 PM PDT 24
Peak memory 253000 kb
Host smart-048caaff-d9da-4ee6-aad0-e8bc79a3fd39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379594027 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.3379594027
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3704438262
Short name T1196
Test name
Test status
Simulation time 19504700 ps
CPU time 12.96 seconds
Started Jun 11 02:29:48 PM PDT 24
Finished Jun 11 02:30:02 PM PDT 24
Peak memory 253012 kb
Host smart-2150f14b-21b2-4ae8-a84f-018867d99f84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704438262 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3704438262
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.536062696
Short name T1154
Test name
Test status
Simulation time 582371900 ps
CPU time 19.37 seconds
Started Jun 11 02:29:38 PM PDT 24
Finished Jun 11 02:29:58 PM PDT 24
Peak memory 263752 kb
Host smart-adafceab-f4a6-4627-b014-e79fdfae2fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536062696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.536062696
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.345863735
Short name T68
Test name
Test status
Simulation time 640214800 ps
CPU time 456.55 seconds
Started Jun 11 02:29:38 PM PDT 24
Finished Jun 11 02:37:15 PM PDT 24
Peak memory 263944 kb
Host smart-708e53a8-009a-471b-a18f-22cde017c145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345863735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.345863735
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.309772229
Short name T297
Test name
Test status
Simulation time 367181600 ps
CPU time 15.59 seconds
Started Jun 11 02:29:48 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 262088 kb
Host smart-6fc7c963-4e18-4ef1-8069-5b3e0a2944eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309772229 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.309772229
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2326791970
Short name T1105
Test name
Test status
Simulation time 28267300 ps
CPU time 15.98 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:30:06 PM PDT 24
Peak memory 263656 kb
Host smart-fbe4ae04-ddc1-4c66-9ed4-4a6c46b9c79a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326791970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2326791970
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2425868351
Short name T1161
Test name
Test status
Simulation time 14515500 ps
CPU time 13.35 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 261096 kb
Host smart-069e9a3c-8c7e-4f8f-8974-8a44bf61d9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425868351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
2425868351
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3426266640
Short name T1215
Test name
Test status
Simulation time 199707500 ps
CPU time 19.32 seconds
Started Jun 11 02:29:47 PM PDT 24
Finished Jun 11 02:30:07 PM PDT 24
Peak memory 263724 kb
Host smart-f8805300-f316-4fdb-8313-c82906692b9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426266640 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3426266640
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2956008050
Short name T1151
Test name
Test status
Simulation time 11386600 ps
CPU time 15.47 seconds
Started Jun 11 02:29:51 PM PDT 24
Finished Jun 11 02:30:08 PM PDT 24
Peak memory 252084 kb
Host smart-6ad5fc3e-04f6-4ea0-8cb4-df0fae94d094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956008050 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2956008050
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1659088974
Short name T1160
Test name
Test status
Simulation time 11729700 ps
CPU time 13.19 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 252928 kb
Host smart-b85906bb-af48-4e73-b66f-6cce3f552ef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659088974 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1659088974
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2048161447
Short name T218
Test name
Test status
Simulation time 52640400 ps
CPU time 18.61 seconds
Started Jun 11 02:29:53 PM PDT 24
Finished Jun 11 02:30:12 PM PDT 24
Peak memory 263776 kb
Host smart-ad78b7a5-fedb-4116-95e5-568678cbf1db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048161447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
2048161447
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3588602992
Short name T363
Test name
Test status
Simulation time 1025498900 ps
CPU time 379.56 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:36:10 PM PDT 24
Peak memory 263944 kb
Host smart-3f04e29c-a0cc-4c19-9e6e-b844e35898cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588602992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3588602992
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2292405754
Short name T1143
Test name
Test status
Simulation time 51624100 ps
CPU time 15 seconds
Started Jun 11 02:29:51 PM PDT 24
Finished Jun 11 02:30:07 PM PDT 24
Peak memory 275900 kb
Host smart-61e18d00-09fb-45be-8b31-0d4e06780fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292405754 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2292405754
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1249322793
Short name T1197
Test name
Test status
Simulation time 34541200 ps
CPU time 16.33 seconds
Started Jun 11 02:29:48 PM PDT 24
Finished Jun 11 02:30:05 PM PDT 24
Peak memory 263656 kb
Host smart-6ebb8863-2312-46cb-b15b-a8dd4e7d6091
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249322793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1249322793
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1444741036
Short name T1170
Test name
Test status
Simulation time 26860600 ps
CPU time 13.54 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:30:05 PM PDT 24
Peak memory 261160 kb
Host smart-da6b0495-7149-4809-b3e8-dd4fce48327a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444741036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1444741036
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2679825869
Short name T302
Test name
Test status
Simulation time 97604300 ps
CPU time 18.06 seconds
Started Jun 11 02:29:47 PM PDT 24
Finished Jun 11 02:30:06 PM PDT 24
Peak memory 263724 kb
Host smart-98012017-73c3-4a3d-95e6-d35bcc552292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679825869 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2679825869
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.977668339
Short name T1104
Test name
Test status
Simulation time 14949400 ps
CPU time 13.27 seconds
Started Jun 11 02:29:50 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 252984 kb
Host smart-2744a87f-56fe-41d3-b0ee-78f906ecb405
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977668339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.977668339
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2515333502
Short name T1191
Test name
Test status
Simulation time 14327700 ps
CPU time 15.69 seconds
Started Jun 11 02:29:51 PM PDT 24
Finished Jun 11 02:30:07 PM PDT 24
Peak memory 252928 kb
Host smart-cf1e8b76-8d49-445c-9d0b-174d6bd008fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515333502 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2515333502
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3665774240
Short name T267
Test name
Test status
Simulation time 47403600 ps
CPU time 18.42 seconds
Started Jun 11 02:29:48 PM PDT 24
Finished Jun 11 02:30:07 PM PDT 24
Peak memory 263768 kb
Host smart-ba6c3a27-f5ee-438e-9487-17b09461585f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665774240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3665774240
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.171392047
Short name T300
Test name
Test status
Simulation time 3129138700 ps
CPU time 884.91 seconds
Started Jun 11 02:29:51 PM PDT 24
Finished Jun 11 02:44:37 PM PDT 24
Peak memory 262840 kb
Host smart-9d846179-20dc-4224-af1b-f479ad7afa59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171392047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.171392047
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2799012705
Short name T215
Test name
Test status
Simulation time 45278000 ps
CPU time 17.06 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:15 PM PDT 24
Peak memory 277268 kb
Host smart-a9398a64-14de-4036-b78b-ad76c6a2fd5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799012705 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2799012705
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2991889489
Short name T1235
Test name
Test status
Simulation time 59855800 ps
CPU time 14.14 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:13 PM PDT 24
Peak memory 263732 kb
Host smart-c51b1993-f22b-447f-8316-c320cb112c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991889489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2991889489
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2391281330
Short name T1102
Test name
Test status
Simulation time 47867300 ps
CPU time 13.39 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:12 PM PDT 24
Peak memory 261172 kb
Host smart-01b52e97-955c-44b6-a74d-e32f44aeda82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391281330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2391281330
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2334795906
Short name T1194
Test name
Test status
Simulation time 85604100 ps
CPU time 18.24 seconds
Started Jun 11 02:29:57 PM PDT 24
Finished Jun 11 02:30:16 PM PDT 24
Peak memory 261292 kb
Host smart-24d2f422-d3ea-4b12-ade6-01904840a968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334795906 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2334795906
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.307423701
Short name T1222
Test name
Test status
Simulation time 14673100 ps
CPU time 16.04 seconds
Started Jun 11 02:30:00 PM PDT 24
Finished Jun 11 02:30:17 PM PDT 24
Peak memory 252956 kb
Host smart-2da83cf7-f3f4-4ac8-bd0d-2dd8419fcfc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307423701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.307423701
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1020630709
Short name T1119
Test name
Test status
Simulation time 35381400 ps
CPU time 15.83 seconds
Started Jun 11 02:30:01 PM PDT 24
Finished Jun 11 02:30:18 PM PDT 24
Peak memory 252936 kb
Host smart-0c0a80a2-69ac-4fa5-8cf8-b89b3e993e81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020630709 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1020630709
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2510188097
Short name T1227
Test name
Test status
Simulation time 579206100 ps
CPU time 21.99 seconds
Started Jun 11 02:29:59 PM PDT 24
Finished Jun 11 02:30:21 PM PDT 24
Peak memory 263768 kb
Host smart-edec4b76-9ed7-4f8c-935a-3e03877df865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510188097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2510188097
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3169432713
Short name T362
Test name
Test status
Simulation time 2061057800 ps
CPU time 461.8 seconds
Started Jun 11 02:29:57 PM PDT 24
Finished Jun 11 02:37:39 PM PDT 24
Peak memory 263752 kb
Host smart-6311238d-be2a-4d45-9e29-71279070cad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169432713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3169432713
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1152586261
Short name T271
Test name
Test status
Simulation time 372785800 ps
CPU time 16.3 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:16 PM PDT 24
Peak memory 272032 kb
Host smart-4a0ed80b-9bca-4af5-b539-dc5a2d139370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152586261 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1152586261
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4113771759
Short name T1140
Test name
Test status
Simulation time 61521400 ps
CPU time 16.92 seconds
Started Jun 11 02:29:56 PM PDT 24
Finished Jun 11 02:30:13 PM PDT 24
Peak memory 263676 kb
Host smart-8383eb7f-e792-4365-b793-0d846085e29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113771759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.4113771759
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3248731157
Short name T1182
Test name
Test status
Simulation time 17186400 ps
CPU time 14.36 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:14 PM PDT 24
Peak memory 261100 kb
Host smart-e537b057-d03f-4f7b-8fa5-b890dc86e082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248731157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3248731157
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3814455296
Short name T256
Test name
Test status
Simulation time 289444300 ps
CPU time 35.15 seconds
Started Jun 11 02:30:00 PM PDT 24
Finished Jun 11 02:30:36 PM PDT 24
Peak memory 262576 kb
Host smart-798f6854-a39a-45cb-a807-174337fae6f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814455296 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3814455296
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.615073279
Short name T1189
Test name
Test status
Simulation time 10942200 ps
CPU time 13.51 seconds
Started Jun 11 02:29:57 PM PDT 24
Finished Jun 11 02:30:11 PM PDT 24
Peak memory 252984 kb
Host smart-bab14c67-eb2e-4cfa-80f3-1a6099e4f8d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615073279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.615073279
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2216621832
Short name T1133
Test name
Test status
Simulation time 17334400 ps
CPU time 16.22 seconds
Started Jun 11 02:29:57 PM PDT 24
Finished Jun 11 02:30:14 PM PDT 24
Peak memory 252916 kb
Host smart-8c0a3b0d-93c8-4af0-ad74-fa646f59a3ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216621832 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.2216621832
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3926648229
Short name T270
Test name
Test status
Simulation time 111342900 ps
CPU time 20.86 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:20 PM PDT 24
Peak memory 263776 kb
Host smart-76a82af1-50a6-4763-af2e-c65573ad1bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926648229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3926648229
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2552993956
Short name T1238
Test name
Test status
Simulation time 87199800 ps
CPU time 16.04 seconds
Started Jun 11 02:30:10 PM PDT 24
Finished Jun 11 02:30:27 PM PDT 24
Peak memory 272000 kb
Host smart-081a1624-85f1-4bb6-92d3-2869d4b4bdd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552993956 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2552993956
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.60411028
Short name T1185
Test name
Test status
Simulation time 20300500 ps
CPU time 13.98 seconds
Started Jun 11 02:30:10 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 261060 kb
Host smart-a72b2a8b-13e3-4220-a6df-4a3e19544543
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60411028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.flash_ctrl_csr_rw.60411028
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.448786128
Short name T1199
Test name
Test status
Simulation time 44365800 ps
CPU time 13.21 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261160 kb
Host smart-daf9ee87-6eff-40f5-b4eb-bfe6b6603bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448786128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.448786128
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2190090445
Short name T1165
Test name
Test status
Simulation time 1220517600 ps
CPU time 19.6 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:30 PM PDT 24
Peak memory 262616 kb
Host smart-355932c8-e728-49fa-baa4-87d0a2a1e2e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190090445 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2190090445
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2202035175
Short name T1156
Test name
Test status
Simulation time 21269900 ps
CPU time 16.57 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:27 PM PDT 24
Peak memory 252584 kb
Host smart-0e2669d7-0ce8-441c-9635-ae1dcbcde14d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202035175 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2202035175
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.853520172
Short name T1193
Test name
Test status
Simulation time 30722800 ps
CPU time 15.46 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:26 PM PDT 24
Peak memory 253016 kb
Host smart-951fdd40-ee57-4e39-ba30-52a2c90c00ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853520172 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.853520172
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.550307378
Short name T1163
Test name
Test status
Simulation time 73769600 ps
CPU time 19.86 seconds
Started Jun 11 02:29:58 PM PDT 24
Finished Jun 11 02:30:19 PM PDT 24
Peak memory 263632 kb
Host smart-953eb808-2dc7-4788-a4f5-c98f292b4a27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550307378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.550307378
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2524798481
Short name T1101
Test name
Test status
Simulation time 849764300 ps
CPU time 34.68 seconds
Started Jun 11 02:28:47 PM PDT 24
Finished Jun 11 02:29:22 PM PDT 24
Peak memory 261080 kb
Host smart-c616754a-3b44-452f-95cc-3870e85560e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524798481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2524798481
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1465297232
Short name T301
Test name
Test status
Simulation time 12415358900 ps
CPU time 94.14 seconds
Started Jun 11 02:28:46 PM PDT 24
Finished Jun 11 02:30:21 PM PDT 24
Peak memory 261196 kb
Host smart-8ee0f210-0529-4d10-9a9e-27f92c7cef26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465297232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1465297232
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.4198434341
Short name T264
Test name
Test status
Simulation time 96973500 ps
CPU time 37.82 seconds
Started Jun 11 02:28:44 PM PDT 24
Finished Jun 11 02:29:23 PM PDT 24
Peak memory 261188 kb
Host smart-641973e1-5363-4ae4-b1ba-88265313f828
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198434341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.4198434341
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4228422463
Short name T1192
Test name
Test status
Simulation time 292849900 ps
CPU time 17.46 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:29:03 PM PDT 24
Peak memory 263972 kb
Host smart-cda65783-b2ed-4223-9c2a-f569867d2d58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228422463 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4228422463
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3470082630
Short name T1166
Test name
Test status
Simulation time 126277600 ps
CPU time 17.61 seconds
Started Jun 11 02:28:46 PM PDT 24
Finished Jun 11 02:29:04 PM PDT 24
Peak memory 263772 kb
Host smart-be7a5cb0-321e-472b-8b8b-d75b5f7008df
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470082630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3470082630
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.950272490
Short name T1128
Test name
Test status
Simulation time 17063300 ps
CPU time 13.95 seconds
Started Jun 11 02:28:47 PM PDT 24
Finished Jun 11 02:29:02 PM PDT 24
Peak memory 261144 kb
Host smart-ae2989f0-8b65-4a4b-b38a-3117e61ada65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950272490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.950272490
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1459016190
Short name T247
Test name
Test status
Simulation time 32526300 ps
CPU time 13.31 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:29:00 PM PDT 24
Peak memory 262132 kb
Host smart-971bd5fd-4027-4218-abe3-3f29dbc77430
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459016190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1459016190
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1855079335
Short name T1120
Test name
Test status
Simulation time 160596100 ps
CPU time 13.29 seconds
Started Jun 11 02:28:44 PM PDT 24
Finished Jun 11 02:28:58 PM PDT 24
Peak memory 261152 kb
Host smart-f4b2809c-dc1c-46a9-a237-3f9ea2556d87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855079335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1855079335
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.915830196
Short name T1123
Test name
Test status
Simulation time 241646900 ps
CPU time 35.28 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:29:21 PM PDT 24
Peak memory 262720 kb
Host smart-512b8391-811a-44de-ad21-f0deda37936c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915830196 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.915830196
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2941552817
Short name T1118
Test name
Test status
Simulation time 39446300 ps
CPU time 13.03 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:28:58 PM PDT 24
Peak memory 253048 kb
Host smart-c4790496-5cab-4514-a413-9e05d6a16e5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941552817 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2941552817
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2914588259
Short name T1147
Test name
Test status
Simulation time 11695100 ps
CPU time 15.6 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:29:02 PM PDT 24
Peak memory 252908 kb
Host smart-3173c426-ec1a-47d7-8c8a-4871028ea737
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914588259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2914588259
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2197046624
Short name T337
Test name
Test status
Simulation time 51975000 ps
CPU time 13.44 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261068 kb
Host smart-af76527b-0ac1-440c-b77a-b96e1943fe76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197046624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2197046624
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.856762743
Short name T1237
Test name
Test status
Simulation time 52523500 ps
CPU time 13.7 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261092 kb
Host smart-bcdce95e-6bc5-475d-ac1b-92dd0c55d249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856762743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.856762743
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.545387596
Short name T1148
Test name
Test status
Simulation time 99895100 ps
CPU time 13.39 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261080 kb
Host smart-7af21fcb-b2b6-40a1-bfbb-08c8a98bae16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545387596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.545387596
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3238801617
Short name T1180
Test name
Test status
Simulation time 17702800 ps
CPU time 14.61 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 260848 kb
Host smart-b6449a4b-60f7-44b6-87a2-4b02d514ebc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238801617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
3238801617
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.4195836397
Short name T1169
Test name
Test status
Simulation time 27339900 ps
CPU time 13.43 seconds
Started Jun 11 02:30:10 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 260980 kb
Host smart-61ee55bc-5850-42eb-b4bb-14d4bdda06f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195836397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
4195836397
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1711553985
Short name T1228
Test name
Test status
Simulation time 48416000 ps
CPU time 13.28 seconds
Started Jun 11 02:30:11 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 261040 kb
Host smart-f92cd0c9-375a-47e8-87a5-e955bf835fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711553985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1711553985
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3926824160
Short name T1099
Test name
Test status
Simulation time 59777800 ps
CPU time 13.31 seconds
Started Jun 11 02:30:10 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 261104 kb
Host smart-97fb5f55-10d7-4152-8856-1cd9cc94e2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926824160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
3926824160
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1282865225
Short name T1236
Test name
Test status
Simulation time 93286600 ps
CPU time 13.28 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261196 kb
Host smart-cc8caca6-797a-44a5-ba9b-effede17994c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282865225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1282865225
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.935379437
Short name T1229
Test name
Test status
Simulation time 77119200 ps
CPU time 13.66 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261048 kb
Host smart-c861eefc-9cc6-4fed-9bec-744841eb7525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935379437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.935379437
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3612185064
Short name T1183
Test name
Test status
Simulation time 15230700 ps
CPU time 13.26 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261064 kb
Host smart-6021ddf6-eed4-4dd1-b221-88ad84ea7516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612185064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
3612185064
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2656305404
Short name T1175
Test name
Test status
Simulation time 5075712200 ps
CPU time 66.93 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:30:04 PM PDT 24
Peak memory 261080 kb
Host smart-2cce24c1-22e5-4e9e-8e9e-9a4f9906ea65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656305404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2656305404
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1171170187
Short name T1206
Test name
Test status
Simulation time 2530263600 ps
CPU time 57.05 seconds
Started Jun 11 02:28:57 PM PDT 24
Finished Jun 11 02:29:55 PM PDT 24
Peak memory 261204 kb
Host smart-afe1e7d0-682a-4770-b48e-51a26d023a59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171170187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1171170187
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1909420830
Short name T1216
Test name
Test status
Simulation time 45451400 ps
CPU time 45.31 seconds
Started Jun 11 02:28:55 PM PDT 24
Finished Jun 11 02:29:41 PM PDT 24
Peak memory 261248 kb
Host smart-60eef570-e214-4315-8554-39baeb2ecb1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909420830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.1909420830
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2473276141
Short name T1174
Test name
Test status
Simulation time 114850200 ps
CPU time 17.62 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:14 PM PDT 24
Peak memory 263792 kb
Host smart-cc738ade-42b0-4ed0-8f0c-2c129d6d396c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473276141 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2473276141
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.128919468
Short name T1121
Test name
Test status
Simulation time 32576000 ps
CPU time 16.65 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:14 PM PDT 24
Peak memory 263736 kb
Host smart-76398354-7961-4106-9d53-31475c14bc3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128919468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_csr_rw.128919468
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3918957428
Short name T1200
Test name
Test status
Simulation time 51208000 ps
CPU time 13.54 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:11 PM PDT 24
Peak memory 261232 kb
Host smart-86739f89-720e-499d-8aaf-3a0982bc10ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918957428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3
918957428
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1559827513
Short name T245
Test name
Test status
Simulation time 49991100 ps
CPU time 13.49 seconds
Started Jun 11 02:28:55 PM PDT 24
Finished Jun 11 02:29:09 PM PDT 24
Peak memory 262696 kb
Host smart-b7312c57-8038-4203-98f9-d1f2d6367268
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559827513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.1559827513
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.826458081
Short name T1090
Test name
Test status
Simulation time 34861500 ps
CPU time 13.32 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:10 PM PDT 24
Peak memory 261228 kb
Host smart-78a422e7-e594-405e-9229-5c620fc7f500
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826458081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.826458081
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1765220141
Short name T1117
Test name
Test status
Simulation time 44357600 ps
CPU time 17.89 seconds
Started Jun 11 02:28:55 PM PDT 24
Finished Jun 11 02:29:13 PM PDT 24
Peak memory 263300 kb
Host smart-fd078166-a6c2-4246-beb5-e1f27334028c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765220141 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1765220141
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.755339699
Short name T1232
Test name
Test status
Simulation time 22380000 ps
CPU time 15.65 seconds
Started Jun 11 02:28:46 PM PDT 24
Finished Jun 11 02:29:03 PM PDT 24
Peak memory 253020 kb
Host smart-4cd0f187-8092-47e7-8d9d-f028403fe222
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755339699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.755339699
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.966729410
Short name T1089
Test name
Test status
Simulation time 14721700 ps
CPU time 13.01 seconds
Started Jun 11 02:28:45 PM PDT 24
Finished Jun 11 02:28:59 PM PDT 24
Peak memory 252960 kb
Host smart-c606ace9-57d2-4e14-a30b-f5887db6c9d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966729410 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.966729410
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2755142436
Short name T269
Test name
Test status
Simulation time 63114700 ps
CPU time 16.94 seconds
Started Jun 11 02:28:46 PM PDT 24
Finished Jun 11 02:29:04 PM PDT 24
Peak memory 263700 kb
Host smart-63f0336b-ce8a-4d8e-9508-e78ab13aa86d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755142436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2
755142436
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1190673289
Short name T1107
Test name
Test status
Simulation time 29425900 ps
CPU time 13.31 seconds
Started Jun 11 02:30:07 PM PDT 24
Finished Jun 11 02:30:22 PM PDT 24
Peak memory 261108 kb
Host smart-245d4242-ef77-496d-9c9f-670639a3fe83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190673289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1190673289
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2097839396
Short name T1214
Test name
Test status
Simulation time 16504000 ps
CPU time 13.27 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:22 PM PDT 24
Peak memory 261132 kb
Host smart-5332b9e5-8332-4294-a87b-675f54abdcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097839396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
2097839396
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2692292068
Short name T1224
Test name
Test status
Simulation time 14143300 ps
CPU time 13.46 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261096 kb
Host smart-e3bb5ec4-8a2a-40e2-8200-81a31d1fba4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692292068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2692292068
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.775559741
Short name T1186
Test name
Test status
Simulation time 17882000 ps
CPU time 13.43 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261072 kb
Host smart-aadb507e-51d7-450a-a6f3-886af392bc25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775559741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.775559741
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3889363596
Short name T1226
Test name
Test status
Simulation time 45474000 ps
CPU time 13.32 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261076 kb
Host smart-e1db565b-4851-4843-b1d9-72aa29db0aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889363596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3889363596
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2816356614
Short name T1131
Test name
Test status
Simulation time 18957800 ps
CPU time 13.37 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:22 PM PDT 24
Peak memory 260916 kb
Host smart-92c095df-e976-43bf-a1f5-fe9d001a8fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816356614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
2816356614
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1894164955
Short name T1150
Test name
Test status
Simulation time 25869200 ps
CPU time 13.34 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261080 kb
Host smart-5dfc8688-5be9-48cc-afec-57ac4cdefb44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894164955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1894164955
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2929888395
Short name T1103
Test name
Test status
Simulation time 41921000 ps
CPU time 13.37 seconds
Started Jun 11 02:30:10 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 261084 kb
Host smart-8e6ef4c5-1992-46e7-9584-843bfd93b170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929888395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2929888395
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3903387621
Short name T335
Test name
Test status
Simulation time 94494100 ps
CPU time 14.3 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:25 PM PDT 24
Peak memory 261060 kb
Host smart-1c29f0b3-f304-4446-bdb1-a0f60fa5ca2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903387621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
3903387621
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1134949837
Short name T1230
Test name
Test status
Simulation time 791614700 ps
CPU time 39.2 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 261276 kb
Host smart-25f1d93b-7024-4348-901b-e97f01c1754a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134949837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1134949837
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2019835962
Short name T259
Test name
Test status
Simulation time 4147420600 ps
CPU time 89.38 seconds
Started Jun 11 02:29:02 PM PDT 24
Finished Jun 11 02:30:33 PM PDT 24
Peak memory 261256 kb
Host smart-71c33d62-ebcc-4a3d-b547-4950b53d42ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019835962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2019835962
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3334129923
Short name T1116
Test name
Test status
Simulation time 69973900 ps
CPU time 38.72 seconds
Started Jun 11 02:28:57 PM PDT 24
Finished Jun 11 02:29:37 PM PDT 24
Peak memory 261348 kb
Host smart-a2bc7cfa-eac9-4657-b840-178004573791
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334129923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3334129923
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.719374496
Short name T303
Test name
Test status
Simulation time 360925000 ps
CPU time 16.24 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:25 PM PDT 24
Peak memory 272060 kb
Host smart-9db6fa33-5202-4389-b48b-551eb5ea5fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719374496 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.719374496
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.178229390
Short name T1144
Test name
Test status
Simulation time 247130000 ps
CPU time 17.87 seconds
Started Jun 11 02:28:55 PM PDT 24
Finished Jun 11 02:29:14 PM PDT 24
Peak memory 263720 kb
Host smart-d92e50da-fbdf-43aa-ba9a-5a0cb7e4a93e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178229390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_csr_rw.178229390
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1194470179
Short name T1184
Test name
Test status
Simulation time 15873100 ps
CPU time 13.65 seconds
Started Jun 11 02:29:05 PM PDT 24
Finished Jun 11 02:29:20 PM PDT 24
Peak memory 261068 kb
Host smart-3dbbfa8e-fbc6-48a8-80ac-795daf914b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194470179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
194470179
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.968905760
Short name T1204
Test name
Test status
Simulation time 30167100 ps
CPU time 13.3 seconds
Started Jun 11 02:28:57 PM PDT 24
Finished Jun 11 02:29:11 PM PDT 24
Peak memory 262120 kb
Host smart-3928ff8e-1ffe-4f4b-b20d-fff6c98c38c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968905760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.968905760
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2203320765
Short name T1198
Test name
Test status
Simulation time 17183200 ps
CPU time 13.18 seconds
Started Jun 11 02:28:57 PM PDT 24
Finished Jun 11 02:29:11 PM PDT 24
Peak memory 261240 kb
Host smart-464b6ce1-ce2c-4e00-ac0c-553f51998977
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203320765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2203320765
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1345949299
Short name T1171
Test name
Test status
Simulation time 96093800 ps
CPU time 17.71 seconds
Started Jun 11 02:28:58 PM PDT 24
Finished Jun 11 02:29:17 PM PDT 24
Peak memory 262720 kb
Host smart-31ad987e-355b-4f2c-8048-5120b0c2edbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345949299 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1345949299
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.523547993
Short name T1223
Test name
Test status
Simulation time 42218200 ps
CPU time 13.14 seconds
Started Jun 11 02:29:06 PM PDT 24
Finished Jun 11 02:29:20 PM PDT 24
Peak memory 252940 kb
Host smart-efa351a4-eb7d-4c29-b417-e25bd0f619a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523547993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.523547993
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3776498489
Short name T1203
Test name
Test status
Simulation time 19673300 ps
CPU time 15.63 seconds
Started Jun 11 02:28:59 PM PDT 24
Finished Jun 11 02:29:15 PM PDT 24
Peak memory 252948 kb
Host smart-c98e0ac5-65fa-473e-bfac-8cd638831794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776498489 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3776498489
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1274086394
Short name T1149
Test name
Test status
Simulation time 48080600 ps
CPU time 18.52 seconds
Started Jun 11 02:28:56 PM PDT 24
Finished Jun 11 02:29:16 PM PDT 24
Peak memory 263780 kb
Host smart-656e2682-8a9b-4555-ae89-e57627da505c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274086394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
274086394
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4209540242
Short name T1153
Test name
Test status
Simulation time 25008700 ps
CPU time 13.21 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:23 PM PDT 24
Peak memory 261024 kb
Host smart-86100d21-2cdb-48dc-8a79-f0d00940760b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209540242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
4209540242
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3445264319
Short name T1126
Test name
Test status
Simulation time 77887300 ps
CPU time 13.43 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261168 kb
Host smart-9e52c524-ea99-401a-bbaa-42fd460beea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445264319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
3445264319
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.195690541
Short name T1124
Test name
Test status
Simulation time 50997400 ps
CPU time 13.44 seconds
Started Jun 11 02:30:06 PM PDT 24
Finished Jun 11 02:30:21 PM PDT 24
Peak memory 261040 kb
Host smart-6074ec64-b507-4858-84b0-1962b0c51417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195690541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.195690541
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.864650263
Short name T1106
Test name
Test status
Simulation time 16939100 ps
CPU time 14.27 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261068 kb
Host smart-b66ad3af-4b55-4f41-a033-41e0f2353ce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864650263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.864650263
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1873799107
Short name T1138
Test name
Test status
Simulation time 23043400 ps
CPU time 13.4 seconds
Started Jun 11 02:30:09 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261080 kb
Host smart-fa114c99-9182-4b47-a219-4dc238321305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873799107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
1873799107
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.55712888
Short name T1164
Test name
Test status
Simulation time 70767400 ps
CPU time 13.94 seconds
Started Jun 11 02:30:08 PM PDT 24
Finished Jun 11 02:30:24 PM PDT 24
Peak memory 261084 kb
Host smart-fbaefe2d-7738-4499-b78e-a538b97b0d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55712888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.55712888
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1539317157
Short name T1168
Test name
Test status
Simulation time 50414200 ps
CPU time 13.4 seconds
Started Jun 11 02:30:19 PM PDT 24
Finished Jun 11 02:30:34 PM PDT 24
Peak memory 261088 kb
Host smart-875f1a5c-68ee-4060-8b49-9fba363d9499
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539317157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1539317157
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2799166756
Short name T262
Test name
Test status
Simulation time 41691400 ps
CPU time 13.34 seconds
Started Jun 11 02:30:21 PM PDT 24
Finished Jun 11 02:30:36 PM PDT 24
Peak memory 261168 kb
Host smart-e79e793d-8282-49fc-95d5-f0f8ade7a8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799166756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2799166756
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2165283891
Short name T1108
Test name
Test status
Simulation time 20024500 ps
CPU time 13.26 seconds
Started Jun 11 02:30:18 PM PDT 24
Finished Jun 11 02:30:32 PM PDT 24
Peak memory 261160 kb
Host smart-4783589a-4943-44b6-8a1c-67d3e4f58a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165283891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2165283891
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2879879381
Short name T1139
Test name
Test status
Simulation time 18711600 ps
CPU time 13.19 seconds
Started Jun 11 02:30:20 PM PDT 24
Finished Jun 11 02:30:35 PM PDT 24
Peak memory 261060 kb
Host smart-963df623-dd5d-4b4d-b6fa-3687f3b5ab0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879879381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2879879381
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1566927847
Short name T272
Test name
Test status
Simulation time 86430300 ps
CPU time 19.46 seconds
Started Jun 11 02:29:06 PM PDT 24
Finished Jun 11 02:29:26 PM PDT 24
Peak memory 272000 kb
Host smart-9589286e-d375-4f85-8977-011afe132023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566927847 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1566927847
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3753272370
Short name T220
Test name
Test status
Simulation time 101124600 ps
CPU time 16.26 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:24 PM PDT 24
Peak memory 263740 kb
Host smart-540300ff-583c-4a42-bedf-20496240d0eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753272370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3753272370
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2620098497
Short name T338
Test name
Test status
Simulation time 101964300 ps
CPU time 13.49 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:21 PM PDT 24
Peak memory 261156 kb
Host smart-c041448d-8d6f-4ec3-b7fa-e49bbc271c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620098497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
620098497
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3710673406
Short name T1207
Test name
Test status
Simulation time 1247912500 ps
CPU time 36.07 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:44 PM PDT 24
Peak memory 263648 kb
Host smart-7cb99a55-9c04-45da-9647-2f73cd6e0e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710673406 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3710673406
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3769078852
Short name T1109
Test name
Test status
Simulation time 169953900 ps
CPU time 15.58 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:24 PM PDT 24
Peak memory 252896 kb
Host smart-1ade974a-6b3f-4fbc-970c-dcdec6e54a87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769078852 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3769078852
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1174585027
Short name T1187
Test name
Test status
Simulation time 43308900 ps
CPU time 15.61 seconds
Started Jun 11 02:29:05 PM PDT 24
Finished Jun 11 02:29:22 PM PDT 24
Peak memory 252844 kb
Host smart-5a90911e-1031-4d12-adf6-07bcd9d2697b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174585027 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1174585027
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.452048121
Short name T1220
Test name
Test status
Simulation time 70998900 ps
CPU time 16.32 seconds
Started Jun 11 02:29:06 PM PDT 24
Finished Jun 11 02:29:24 PM PDT 24
Peak memory 263668 kb
Host smart-2a511832-c3e8-4321-ab71-7cc8ca6edd87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452048121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.452048121
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2444046436
Short name T360
Test name
Test status
Simulation time 193964900 ps
CPU time 463.14 seconds
Started Jun 11 02:30:33 PM PDT 24
Finished Jun 11 02:38:17 PM PDT 24
Peak memory 263756 kb
Host smart-7c18c5ad-2b7f-4166-a92e-15a12ab915c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444046436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2444046436
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1240108374
Short name T214
Test name
Test status
Simulation time 114179600 ps
CPU time 19.73 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:28 PM PDT 24
Peak memory 271972 kb
Host smart-e1e984f7-719b-41dc-b295-1dc1198b1daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240108374 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1240108374
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2675825631
Short name T1213
Test name
Test status
Simulation time 34133700 ps
CPU time 13.95 seconds
Started Jun 11 02:29:06 PM PDT 24
Finished Jun 11 02:29:21 PM PDT 24
Peak memory 263744 kb
Host smart-1a4e5068-416a-4537-836d-22cfe73b9c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675825631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2675825631
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3559776214
Short name T1167
Test name
Test status
Simulation time 31264200 ps
CPU time 13.7 seconds
Started Jun 11 02:29:06 PM PDT 24
Finished Jun 11 02:29:20 PM PDT 24
Peak memory 261052 kb
Host smart-43a38a7a-16b2-477a-b4b9-e76506b5c834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559776214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
559776214
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2181900618
Short name T1098
Test name
Test status
Simulation time 62690500 ps
CPU time 20.47 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:29 PM PDT 24
Peak memory 263624 kb
Host smart-de8eb2b6-cebd-4e0b-9817-44a8e86654b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181900618 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2181900618
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2704369953
Short name T1221
Test name
Test status
Simulation time 46688600 ps
CPU time 13.13 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:21 PM PDT 24
Peak memory 252844 kb
Host smart-4279ec0e-8c13-4246-bf2c-d69c7e75e148
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704369953 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2704369953
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.807214379
Short name T1162
Test name
Test status
Simulation time 11814500 ps
CPU time 15.94 seconds
Started Jun 11 02:29:09 PM PDT 24
Finished Jun 11 02:29:26 PM PDT 24
Peak memory 252920 kb
Host smart-9bc325f4-b5f0-47a3-97de-7ee9ee2d8ed2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807214379 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.807214379
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2105861437
Short name T261
Test name
Test status
Simulation time 30451900 ps
CPU time 15.96 seconds
Started Jun 11 02:29:09 PM PDT 24
Finished Jun 11 02:29:26 PM PDT 24
Peak memory 263756 kb
Host smart-e57b9830-eddc-49a8-a3f5-037a37cad1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105861437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
105861437
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.4112333165
Short name T274
Test name
Test status
Simulation time 395084200 ps
CPU time 379.47 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:35:27 PM PDT 24
Peak memory 263780 kb
Host smart-5cef4688-812c-4de2-acbb-97604a2cbecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112333165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.4112333165
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2829679904
Short name T1218
Test name
Test status
Simulation time 234054300 ps
CPU time 14.92 seconds
Started Jun 11 02:29:20 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 277116 kb
Host smart-8f8d58bc-ba58-4a32-a9b7-2c1b0582c22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829679904 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2829679904
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2987312057
Short name T1176
Test name
Test status
Simulation time 90147500 ps
CPU time 16.51 seconds
Started Jun 11 02:29:24 PM PDT 24
Finished Jun 11 02:29:41 PM PDT 24
Peak memory 261576 kb
Host smart-022a331b-6a2e-419c-ae07-12f812102289
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987312057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.2987312057
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2653007876
Short name T263
Test name
Test status
Simulation time 49574400 ps
CPU time 13.41 seconds
Started Jun 11 02:29:18 PM PDT 24
Finished Jun 11 02:29:32 PM PDT 24
Peak memory 261084 kb
Host smart-6d05ca77-afc2-49ec-904b-70239091caf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653007876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
653007876
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.673092300
Short name T1234
Test name
Test status
Simulation time 84847200 ps
CPU time 17.69 seconds
Started Jun 11 02:29:15 PM PDT 24
Finished Jun 11 02:29:33 PM PDT 24
Peak memory 263692 kb
Host smart-8f12a7b3-617e-4c97-80ad-feac54260312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673092300 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.673092300
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2673091580
Short name T1132
Test name
Test status
Simulation time 19862100 ps
CPU time 15.56 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:33 PM PDT 24
Peak memory 252936 kb
Host smart-98038100-470a-437b-a48b-8141578c3363
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673091580 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2673091580
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3848143760
Short name T1137
Test name
Test status
Simulation time 12293000 ps
CPU time 15.89 seconds
Started Jun 11 02:29:16 PM PDT 24
Finished Jun 11 02:29:33 PM PDT 24
Peak memory 252984 kb
Host smart-60ca8709-7745-4460-8900-c7bf9a618513
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848143760 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3848143760
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1350277329
Short name T1205
Test name
Test status
Simulation time 601041700 ps
CPU time 20.47 seconds
Started Jun 11 02:29:07 PM PDT 24
Finished Jun 11 02:29:28 PM PDT 24
Peak memory 263768 kb
Host smart-62ecd5ac-6750-4838-bb39-d7ed716036aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350277329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
350277329
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4219883658
Short name T1195
Test name
Test status
Simulation time 54344900 ps
CPU time 18 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 272020 kb
Host smart-1b548f1c-3103-4b51-a2d1-1c6c6325ab34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219883658 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.4219883658
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1928418793
Short name T1217
Test name
Test status
Simulation time 83549000 ps
CPU time 16.73 seconds
Started Jun 11 02:29:18 PM PDT 24
Finished Jun 11 02:29:35 PM PDT 24
Peak memory 263744 kb
Host smart-cd59a84e-09c3-47e4-b01a-1a11b81ac973
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928418793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.1928418793
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2917318935
Short name T1125
Test name
Test status
Simulation time 29262100 ps
CPU time 13.49 seconds
Started Jun 11 02:29:21 PM PDT 24
Finished Jun 11 02:29:35 PM PDT 24
Peak memory 261108 kb
Host smart-5248aa96-b693-4a20-9b02-10ac6c43b3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917318935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
917318935
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3782223779
Short name T1172
Test name
Test status
Simulation time 236739600 ps
CPU time 18.68 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:36 PM PDT 24
Peak memory 261224 kb
Host smart-3e88035f-a62d-415f-a6bd-a1d53aa6afe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782223779 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3782223779
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3504326005
Short name T1112
Test name
Test status
Simulation time 45156100 ps
CPU time 13.4 seconds
Started Jun 11 02:29:18 PM PDT 24
Finished Jun 11 02:29:32 PM PDT 24
Peak memory 252828 kb
Host smart-8c47b1a9-b268-4d73-b0d3-135a8b4f6d71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504326005 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3504326005
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.306426361
Short name T1155
Test name
Test status
Simulation time 39178800 ps
CPU time 13.38 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:31 PM PDT 24
Peak memory 252944 kb
Host smart-31c6e35c-669c-4ffa-bd96-4db3e1ac9632
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306426361 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.306426361
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.833349199
Short name T266
Test name
Test status
Simulation time 203693100 ps
CPU time 18.89 seconds
Started Jun 11 02:29:20 PM PDT 24
Finished Jun 11 02:29:39 PM PDT 24
Peak memory 263728 kb
Host smart-fa1a0243-e375-4793-84fb-f73ee27fc0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833349199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.833349199
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1173083266
Short name T319
Test name
Test status
Simulation time 178059000 ps
CPU time 468.82 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:37:07 PM PDT 24
Peak memory 263788 kb
Host smart-8b2f33fc-3c4a-4509-94dd-02349487a57c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173083266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1173083266
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4173280206
Short name T273
Test name
Test status
Simulation time 82166400 ps
CPU time 16.46 seconds
Started Jun 11 02:29:17 PM PDT 24
Finished Jun 11 02:29:34 PM PDT 24
Peak memory 270436 kb
Host smart-8d6c6a16-68df-4e8d-96d1-84c22904d837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173280206 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.4173280206
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2472924791
Short name T257
Test name
Test status
Simulation time 693174200 ps
CPU time 17.81 seconds
Started Jun 11 02:29:16 PM PDT 24
Finished Jun 11 02:29:35 PM PDT 24
Peak memory 261112 kb
Host smart-9cab24c1-7679-4453-97bc-6a6fe7673280
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472924791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2472924791
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.645138903
Short name T1114
Test name
Test status
Simulation time 81383400 ps
CPU time 13.32 seconds
Started Jun 11 02:29:16 PM PDT 24
Finished Jun 11 02:29:30 PM PDT 24
Peak memory 261152 kb
Host smart-ec6cc53f-403c-4903-8235-113185cbebad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645138903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.645138903
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3980411479
Short name T69
Test name
Test status
Simulation time 211024200 ps
CPU time 21.1 seconds
Started Jun 11 02:29:16 PM PDT 24
Finished Jun 11 02:29:38 PM PDT 24
Peak memory 262308 kb
Host smart-c0d80300-3cf1-4159-ba0b-935a6bad7f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980411479 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.3980411479
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.970758451
Short name T1130
Test name
Test status
Simulation time 69761600 ps
CPU time 15.52 seconds
Started Jun 11 02:29:21 PM PDT 24
Finished Jun 11 02:29:37 PM PDT 24
Peak memory 253048 kb
Host smart-f24e4e65-1b7e-40eb-a3a8-dbc8f7ff2377
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970758451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.970758451
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.251097378
Short name T1092
Test name
Test status
Simulation time 193173200 ps
CPU time 15.2 seconds
Started Jun 11 02:29:22 PM PDT 24
Finished Jun 11 02:29:39 PM PDT 24
Peak memory 253048 kb
Host smart-44984b64-136f-40fc-a5b1-14a82ca0a00e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251097378 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.251097378
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4266027037
Short name T1208
Test name
Test status
Simulation time 29504300 ps
CPU time 16.11 seconds
Started Jun 11 02:29:23 PM PDT 24
Finished Jun 11 02:29:40 PM PDT 24
Peak memory 263748 kb
Host smart-75fcca61-f123-45da-8c84-9fe963cdfa65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266027037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4
266027037
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3430699772
Short name T217
Test name
Test status
Simulation time 272990100 ps
CPU time 451.7 seconds
Started Jun 11 02:29:21 PM PDT 24
Finished Jun 11 02:36:53 PM PDT 24
Peak memory 263800 kb
Host smart-eccd1514-32cc-49b3-8cd3-afc03522962f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430699772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3430699772
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.569701529
Short name T506
Test name
Test status
Simulation time 286296900 ps
CPU time 13.67 seconds
Started Jun 11 02:59:04 PM PDT 24
Finished Jun 11 02:59:18 PM PDT 24
Peak memory 258640 kb
Host smart-fccecea7-77d2-413d-8bea-c9d67486c600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569701529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.569701529
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.2717550957
Short name T775
Test name
Test status
Simulation time 21640200 ps
CPU time 13.84 seconds
Started Jun 11 02:59:03 PM PDT 24
Finished Jun 11 02:59:18 PM PDT 24
Peak memory 261656 kb
Host smart-a7a771cd-ebf7-4589-a0d3-3f3f3e5d5d41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717550957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.2717550957
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.282794282
Short name T802
Test name
Test status
Simulation time 14177200 ps
CPU time 13.52 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 02:58:59 PM PDT 24
Peak memory 275192 kb
Host smart-5a864c40-c33e-4115-8f67-cf28f8028202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282794282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.282794282
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1959062257
Short name T159
Test name
Test status
Simulation time 374661500 ps
CPU time 103.55 seconds
Started Jun 11 02:58:18 PM PDT 24
Finished Jun 11 03:00:03 PM PDT 24
Peak memory 282224 kb
Host smart-07328a24-712a-432b-8f25-8f623f2721d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959062257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.1959062257
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.495198022
Short name T152
Test name
Test status
Simulation time 3352640500 ps
CPU time 567.07 seconds
Started Jun 11 02:57:39 PM PDT 24
Finished Jun 11 03:07:07 PM PDT 24
Peak memory 263692 kb
Host smart-c61eb808-b5d5-40bb-adae-6d67a1631397
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495198022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.495198022
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.3319296162
Short name T285
Test name
Test status
Simulation time 1360023900 ps
CPU time 43.33 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 02:59:30 PM PDT 24
Peak memory 263060 kb
Host smart-f625902d-2558-4a52-bc64-585f0437c851
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319296162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.3319296162
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1730771856
Short name T961
Test name
Test status
Simulation time 203464845800 ps
CPU time 4374.14 seconds
Started Jun 11 02:57:52 PM PDT 24
Finished Jun 11 04:10:48 PM PDT 24
Peak memory 265548 kb
Host smart-5bfeac7f-5c7a-4513-88d0-7d3b5bf68e26
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730771856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1730771856
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2123181852
Short name T202
Test name
Test status
Simulation time 336395756300 ps
CPU time 2363.33 seconds
Started Jun 11 02:57:51 PM PDT 24
Finished Jun 11 03:37:16 PM PDT 24
Peak memory 265616 kb
Host smart-3acb5080-db2f-4b8e-9a4f-3f886f331471
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123181852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2123181852
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.506951844
Short name T623
Test name
Test status
Simulation time 129766100 ps
CPU time 92.13 seconds
Started Jun 11 02:57:31 PM PDT 24
Finished Jun 11 02:59:04 PM PDT 24
Peak memory 265760 kb
Host smart-cc28c75f-7f98-4fde-bdc8-7e51b3dd3eb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=506951844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.506951844
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.4021099252
Short name T864
Test name
Test status
Simulation time 10048663100 ps
CPU time 89.42 seconds
Started Jun 11 02:59:03 PM PDT 24
Finished Jun 11 03:00:34 PM PDT 24
Peak memory 266024 kb
Host smart-abc771ab-59ad-4ccf-a218-382545ec6205
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021099252 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.4021099252
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.429846045
Short name T673
Test name
Test status
Simulation time 171315432600 ps
CPU time 1861.62 seconds
Started Jun 11 02:57:39 PM PDT 24
Finished Jun 11 03:28:41 PM PDT 24
Peak memory 265420 kb
Host smart-4c108f7a-4f36-4c0d-b63c-c4b38c4baa08
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429846045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.429846045
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.385096667
Short name T818
Test name
Test status
Simulation time 160191629000 ps
CPU time 961.56 seconds
Started Jun 11 02:57:53 PM PDT 24
Finished Jun 11 03:13:56 PM PDT 24
Peak memory 264204 kb
Host smart-9bdbeb51-964b-4294-afda-1ce2137e014c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385096667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.385096667
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3601486512
Short name T305
Test name
Test status
Simulation time 3914547400 ps
CPU time 78.04 seconds
Started Jun 11 02:57:38 PM PDT 24
Finished Jun 11 02:58:57 PM PDT 24
Peak memory 263024 kb
Host smart-9d396c83-a790-4c0f-9c9b-6928dc3fd60a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601486512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.3601486512
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.1141976727
Short name T227
Test name
Test status
Simulation time 4083335700 ps
CPU time 567.09 seconds
Started Jun 11 02:58:27 PM PDT 24
Finished Jun 11 03:07:55 PM PDT 24
Peak memory 314924 kb
Host smart-5428dd0a-0f69-4cc9-8e5b-25ab7e1e66c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141976727 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.1141976727
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.83309352
Short name T1045
Test name
Test status
Simulation time 7353014800 ps
CPU time 242.9 seconds
Started Jun 11 02:58:29 PM PDT 24
Finished Jun 11 03:02:33 PM PDT 24
Peak memory 285416 kb
Host smart-f1d5fddb-0a21-46a3-9fb1-4a426296a543
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83309352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_
ctrl_intr_rd.83309352
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2891557234
Short name T611
Test name
Test status
Simulation time 15106251300 ps
CPU time 92.68 seconds
Started Jun 11 02:58:25 PM PDT 24
Finished Jun 11 02:59:58 PM PDT 24
Peak memory 260264 kb
Host smart-7d513156-56cc-4454-ae9f-225733fd95ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891557234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2891557234
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.4270797198
Short name T106
Test name
Test status
Simulation time 10326736900 ps
CPU time 82.07 seconds
Started Jun 11 02:58:00 PM PDT 24
Finished Jun 11 02:59:24 PM PDT 24
Peak memory 260660 kb
Host smart-b0eead4d-05e4-4355-81c9-0fb7ab8b935d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270797198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4270797198
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2098780646
Short name T1071
Test name
Test status
Simulation time 44868200 ps
CPU time 13.45 seconds
Started Jun 11 02:58:53 PM PDT 24
Finished Jun 11 02:59:08 PM PDT 24
Peak memory 260244 kb
Host smart-92bd555b-cad6-4813-b12b-f31eda6e4eb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098780646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2098780646
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.4041626033
Short name T151
Test name
Test status
Simulation time 1654306100 ps
CPU time 70.4 seconds
Started Jun 11 02:58:04 PM PDT 24
Finished Jun 11 02:59:16 PM PDT 24
Peak memory 261124 kb
Host smart-a77ed793-d57b-4603-a952-e954f901fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041626033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.4041626033
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2256293140
Short name T578
Test name
Test status
Simulation time 147852600 ps
CPU time 131.69 seconds
Started Jun 11 02:57:52 PM PDT 24
Finished Jun 11 03:00:04 PM PDT 24
Peak memory 260096 kb
Host smart-644ff37f-3127-4237-93a1-b222a232c10f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256293140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2256293140
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.511840089
Short name T187
Test name
Test status
Simulation time 16731912300 ps
CPU time 201.34 seconds
Started Jun 11 02:58:18 PM PDT 24
Finished Jun 11 03:01:40 PM PDT 24
Peak memory 282248 kb
Host smart-4ae8c736-1395-4892-9c93-31f19f70e964
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511840089 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.511840089
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4219452584
Short name T46
Test name
Test status
Simulation time 16003000 ps
CPU time 14.09 seconds
Started Jun 11 02:58:59 PM PDT 24
Finished Jun 11 02:59:15 PM PDT 24
Peak memory 279536 kb
Host smart-57a56836-b899-4e5e-9cb1-b2e1987286b7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4219452584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4219452584
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.2214837738
Short name T894
Test name
Test status
Simulation time 1128755600 ps
CPU time 429.24 seconds
Started Jun 11 02:57:39 PM PDT 24
Finished Jun 11 03:04:49 PM PDT 24
Peak memory 263348 kb
Host smart-942bec70-39e1-41cb-ae15-71a8abd38194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214837738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2214837738
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2869220517
Short name T211
Test name
Test status
Simulation time 24661600 ps
CPU time 14.69 seconds
Started Jun 11 02:58:55 PM PDT 24
Finished Jun 11 02:59:11 PM PDT 24
Peak memory 263236 kb
Host smart-c48ee05d-95e4-485b-9162-875c190da897
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869220517 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2869220517
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3344560722
Short name T424
Test name
Test status
Simulation time 10086900900 ps
CPU time 202.33 seconds
Started Jun 11 02:58:26 PM PDT 24
Finished Jun 11 03:01:50 PM PDT 24
Peak memory 260532 kb
Host smart-f6e35ad9-0c7d-44b9-80ea-d21ae2bf0c39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344560722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3344560722
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3591485168
Short name T793
Test name
Test status
Simulation time 249158800 ps
CPU time 253.26 seconds
Started Jun 11 02:57:23 PM PDT 24
Finished Jun 11 03:01:37 PM PDT 24
Peak memory 281920 kb
Host smart-790a533b-7fbf-4e02-a01c-09bb99b2c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591485168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3591485168
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1135752976
Short name T353
Test name
Test status
Simulation time 66568900 ps
CPU time 32.82 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 02:59:18 PM PDT 24
Peak memory 276012 kb
Host smart-d9ecc84e-c3d3-4cf0-9785-03ad072727ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135752976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1135752976
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2663395542
Short name T757
Test name
Test status
Simulation time 147795100 ps
CPU time 43.87 seconds
Started Jun 11 02:59:05 PM PDT 24
Finished Jun 11 02:59:50 PM PDT 24
Peak memory 277524 kb
Host smart-2c018331-130f-4e40-a60f-42997376fdcf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663395542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2663395542
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.1402478220
Short name T482
Test name
Test status
Simulation time 75963000 ps
CPU time 35.41 seconds
Started Jun 11 02:58:35 PM PDT 24
Finished Jun 11 02:59:11 PM PDT 24
Peak memory 277684 kb
Host smart-b7546ccc-59d9-4e6d-9fe8-787bbd8c6d06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402478220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.1402478220
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3454567493
Short name T545
Test name
Test status
Simulation time 22905700 ps
CPU time 14.19 seconds
Started Jun 11 02:58:08 PM PDT 24
Finished Jun 11 02:58:25 PM PDT 24
Peak memory 258620 kb
Host smart-b274ba79-018c-48c1-b4f8-7d321949ecc1
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3454567493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3454567493
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2295865330
Short name T571
Test name
Test status
Simulation time 39595900 ps
CPU time 22.93 seconds
Started Jun 11 02:58:09 PM PDT 24
Finished Jun 11 02:58:34 PM PDT 24
Peak memory 265716 kb
Host smart-bcca0f2a-2089-488b-a75c-7fd6d8ea33b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295865330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2295865330
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.987055507
Short name T137
Test name
Test status
Simulation time 157544442500 ps
CPU time 1041.79 seconds
Started Jun 11 02:58:52 PM PDT 24
Finished Jun 11 03:16:15 PM PDT 24
Peak memory 262816 kb
Host smart-32a8b97a-e2ac-4109-84fe-acf0662532ca
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987055507 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.987055507
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.3475822046
Short name T176
Test name
Test status
Simulation time 2207679100 ps
CPU time 156.63 seconds
Started Jun 11 02:58:08 PM PDT 24
Finished Jun 11 03:00:46 PM PDT 24
Peak memory 290368 kb
Host smart-346488cb-c9d6-41df-9194-14550d679e73
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475822046 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.3475822046
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.2840520487
Short name T166
Test name
Test status
Simulation time 6117908500 ps
CPU time 180.52 seconds
Started Jun 11 02:58:17 PM PDT 24
Finished Jun 11 03:01:19 PM PDT 24
Peak memory 284392 kb
Host smart-ec88e3c7-00fa-4125-8571-b9a17ec29e59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2840520487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2840520487
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3202636306
Short name T1081
Test name
Test status
Simulation time 6112412200 ps
CPU time 133.82 seconds
Started Jun 11 02:58:08 PM PDT 24
Finished Jun 11 03:00:24 PM PDT 24
Peak memory 292144 kb
Host smart-9f35aa38-f276-4a7e-8694-53645e918b10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202636306 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3202636306
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1389801883
Short name T190
Test name
Test status
Simulation time 8951714900 ps
CPU time 571.75 seconds
Started Jun 11 02:58:09 PM PDT 24
Finished Jun 11 03:07:43 PM PDT 24
Peak memory 309752 kb
Host smart-76e844a3-4b49-4961-bc0f-d688e81d599e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389801883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1389801883
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.2700700630
Short name T962
Test name
Test status
Simulation time 32651800 ps
CPU time 31.47 seconds
Started Jun 11 02:58:26 PM PDT 24
Finished Jun 11 02:58:58 PM PDT 24
Peak memory 278564 kb
Host smart-3c411683-578e-4eb9-87a8-48180449224b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700700630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.2700700630
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1337890461
Short name T322
Test name
Test status
Simulation time 130052700 ps
CPU time 32.24 seconds
Started Jun 11 02:58:36 PM PDT 24
Finished Jun 11 02:59:09 PM PDT 24
Peak memory 268068 kb
Host smart-cef7b0da-ca33-4f2e-be35-e8ae070976d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337890461 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1337890461
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.341779521
Short name T654
Test name
Test status
Simulation time 18550120800 ps
CPU time 685.28 seconds
Started Jun 11 02:58:09 PM PDT 24
Finished Jun 11 03:09:37 PM PDT 24
Peak memory 321296 kb
Host smart-7281fd37-ee4f-4754-8064-2c63a48ea204
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341779521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_se
rr.341779521
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3144248749
Short name T369
Test name
Test status
Simulation time 8803152600 ps
CPU time 78.75 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 03:00:05 PM PDT 24
Peak memory 263956 kb
Host smart-ca475a6c-30fb-408e-995c-685081f731f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144248749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3144248749
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.876030281
Short name T425
Test name
Test status
Simulation time 2115013800 ps
CPU time 94.2 seconds
Started Jun 11 02:58:19 PM PDT 24
Finished Jun 11 02:59:54 PM PDT 24
Peak memory 273996 kb
Host smart-1834cb9f-7cf9-441b-a63a-f93ca0b77363
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876030281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.876030281
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3039154506
Short name T439
Test name
Test status
Simulation time 3012370500 ps
CPU time 80.05 seconds
Started Jun 11 02:58:19 PM PDT 24
Finished Jun 11 02:59:40 PM PDT 24
Peak memory 274864 kb
Host smart-2f4d2ed5-a55d-4e1a-8673-7871e8496fc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039154506 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3039154506
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.4087922671
Short name T668
Test name
Test status
Simulation time 62283600 ps
CPU time 187.67 seconds
Started Jun 11 02:57:22 PM PDT 24
Finished Jun 11 03:00:31 PM PDT 24
Peak memory 277700 kb
Host smart-8b50e3d9-80ed-4f07-9ccb-407fab28a1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087922671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.4087922671
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.819419566
Short name T681
Test name
Test status
Simulation time 15456800 ps
CPU time 23.49 seconds
Started Jun 11 02:57:23 PM PDT 24
Finished Jun 11 02:57:47 PM PDT 24
Peak memory 259788 kb
Host smart-67fdd3a4-5138-437b-8eb4-5d9f03698086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819419566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.819419566
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.4204233155
Short name T481
Test name
Test status
Simulation time 69909400 ps
CPU time 63.26 seconds
Started Jun 11 02:58:45 PM PDT 24
Finished Jun 11 02:59:49 PM PDT 24
Peak memory 261860 kb
Host smart-fbbc246b-2df4-418a-8d74-813666cda492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204233155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.4204233155
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1045355981
Short name T603
Test name
Test status
Simulation time 20970900 ps
CPU time 23.87 seconds
Started Jun 11 02:57:33 PM PDT 24
Finished Jun 11 02:57:57 PM PDT 24
Peak memory 262696 kb
Host smart-83fe5421-5df2-44c2-b7f1-eb938aa40980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045355981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1045355981
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.3520338367
Short name T598
Test name
Test status
Simulation time 2092808000 ps
CPU time 185.84 seconds
Started Jun 11 02:58:00 PM PDT 24
Finished Jun 11 03:01:07 PM PDT 24
Peak memory 265676 kb
Host smart-bd8bb35c-d98a-4223-bcbc-43a3bb3cf6a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520338367 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.3520338367
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.2973771577
Short name T10
Test name
Test status
Simulation time 553704200 ps
CPU time 15.17 seconds
Started Jun 11 02:58:46 PM PDT 24
Finished Jun 11 02:59:02 PM PDT 24
Peak memory 260680 kb
Host smart-d88b3d1c-d940-44b1-a05b-43340fef33be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973771577 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2973771577
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2241560248
Short name T815
Test name
Test status
Simulation time 178922600 ps
CPU time 15.19 seconds
Started Jun 11 02:58:00 PM PDT 24
Finished Jun 11 02:58:17 PM PDT 24
Peak memory 265420 kb
Host smart-6505efd4-1357-43dc-9b4a-b1227835d423
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2241560248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2241560248
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.400334211
Short name T5
Test name
Test status
Simulation time 15442400 ps
CPU time 13.79 seconds
Started Jun 11 03:00:01 PM PDT 24
Finished Jun 11 03:00:15 PM PDT 24
Peak memory 261740 kb
Host smart-91f9a0b0-9407-45d0-8c63-f028bf2af4ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400334211 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.400334211
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3116993886
Short name T604
Test name
Test status
Simulation time 108249600 ps
CPU time 14.21 seconds
Started Jun 11 03:00:22 PM PDT 24
Finished Jun 11 03:00:38 PM PDT 24
Peak memory 258776 kb
Host smart-bb804d7f-aac0-47e5-bbb1-38190596ae32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116993886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
116993886
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.1933327225
Short name T368
Test name
Test status
Simulation time 64990600 ps
CPU time 13.72 seconds
Started Jun 11 03:00:15 PM PDT 24
Finished Jun 11 03:00:30 PM PDT 24
Peak memory 261876 kb
Host smart-af956b9e-ab74-4126-8fe2-481b1ee91c36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933327225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.1933327225
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3712063202
Short name T485
Test name
Test status
Simulation time 15784500 ps
CPU time 16.36 seconds
Started Jun 11 03:00:03 PM PDT 24
Finished Jun 11 03:00:20 PM PDT 24
Peak memory 275072 kb
Host smart-2452b8c0-b8c1-482a-bd92-38b1805697e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712063202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3712063202
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.1666966643
Short name T156
Test name
Test status
Simulation time 311518900 ps
CPU time 103.19 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:01:26 PM PDT 24
Peak memory 282280 kb
Host smart-dc665313-991b-45ba-94e5-dd9ca86ce209
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666966643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.1666966643
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3087067962
Short name T139
Test name
Test status
Simulation time 94158400 ps
CPU time 21.73 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 03:00:25 PM PDT 24
Peak memory 274024 kb
Host smart-16f7dd99-54cc-43d5-af76-1b8cc66b049d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087067962 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3087067962
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.4203030969
Short name T153
Test name
Test status
Simulation time 1422662200 ps
CPU time 359.02 seconds
Started Jun 11 02:59:22 PM PDT 24
Finished Jun 11 03:05:23 PM PDT 24
Peak memory 263408 kb
Host smart-23d7329e-f3dd-4421-9060-7bb0574f0215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203030969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.4203030969
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.4057542726
Short name T108
Test name
Test status
Simulation time 14134237000 ps
CPU time 2140.03 seconds
Started Jun 11 02:59:42 PM PDT 24
Finished Jun 11 03:35:23 PM PDT 24
Peak memory 264592 kb
Host smart-b2d6aad0-d8b5-4b49-afdd-13963df07a68
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057542726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.4057542726
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2408185212
Short name T161
Test name
Test status
Simulation time 2466214800 ps
CPU time 2575.92 seconds
Started Jun 11 02:59:32 PM PDT 24
Finished Jun 11 03:42:30 PM PDT 24
Peak memory 262516 kb
Host smart-38bedc79-2584-42ad-8628-d9a2936cd61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408185212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2408185212
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2103614072
Short name T952
Test name
Test status
Simulation time 1351760500 ps
CPU time 768.48 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:12:31 PM PDT 24
Peak memory 273664 kb
Host smart-b0effd11-0b35-4144-94b4-d93a5e026489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103614072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2103614072
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2070847429
Short name T566
Test name
Test status
Simulation time 323858800 ps
CPU time 41.21 seconds
Started Jun 11 03:00:03 PM PDT 24
Finished Jun 11 03:00:45 PM PDT 24
Peak memory 265464 kb
Host smart-525edc00-3926-40e3-8b22-b0610cee1f09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070847429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2070847429
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4089569962
Short name T147
Test name
Test status
Simulation time 507388608600 ps
CPU time 1919.32 seconds
Started Jun 11 02:59:22 PM PDT 24
Finished Jun 11 03:31:24 PM PDT 24
Peak memory 264212 kb
Host smart-b0b25896-e3ba-44d5-8806-4d3f5ffd9912
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089569962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4089569962
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2727130105
Short name T569
Test name
Test status
Simulation time 46308400 ps
CPU time 34.85 seconds
Started Jun 11 02:59:15 PM PDT 24
Finished Jun 11 02:59:50 PM PDT 24
Peak memory 265516 kb
Host smart-3a00198d-bbd4-451d-9a7f-27bf42d22e36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727130105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2727130105
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3710630796
Short name T291
Test name
Test status
Simulation time 10012494900 ps
CPU time 307.71 seconds
Started Jun 11 03:00:20 PM PDT 24
Finished Jun 11 03:05:29 PM PDT 24
Peak memory 271856 kb
Host smart-48a81f56-e5d9-4177-8267-01a409562701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710630796 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3710630796
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3089380952
Short name T556
Test name
Test status
Simulation time 25562200 ps
CPU time 13.82 seconds
Started Jun 11 03:00:21 PM PDT 24
Finished Jun 11 03:00:36 PM PDT 24
Peak memory 265900 kb
Host smart-5661bbf7-9b15-4b84-bf14-217f8b7eed6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089380952 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3089380952
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2424599124
Short name T79
Test name
Test status
Simulation time 95679059600 ps
CPU time 1995.16 seconds
Started Jun 11 02:59:22 PM PDT 24
Finished Jun 11 03:32:40 PM PDT 24
Peak memory 260904 kb
Host smart-b72054db-1357-4ae5-901c-0249c11fb83a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424599124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2424599124
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1537230511
Short name T634
Test name
Test status
Simulation time 40120659600 ps
CPU time 868.89 seconds
Started Jun 11 02:59:24 PM PDT 24
Finished Jun 11 03:13:54 PM PDT 24
Peak memory 264132 kb
Host smart-7730149a-4f47-4cf5-b088-9c7308ee6aa1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537230511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.1537230511
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.2908020727
Short name T1053
Test name
Test status
Simulation time 17002774000 ps
CPU time 148.55 seconds
Started Jun 11 02:59:12 PM PDT 24
Finished Jun 11 03:01:41 PM PDT 24
Peak memory 263464 kb
Host smart-c0576f07-bc24-4f83-a9d9-f185201ea044
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908020727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.2908020727
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1376938816
Short name T352
Test name
Test status
Simulation time 727998800 ps
CPU time 149.23 seconds
Started Jun 11 02:59:49 PM PDT 24
Finished Jun 11 03:02:19 PM PDT 24
Peak memory 294328 kb
Host smart-91df9453-6495-4ff2-9892-803453045c7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376938816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1376938816
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3357034752
Short name T817
Test name
Test status
Simulation time 25889228600 ps
CPU time 153.85 seconds
Started Jun 11 03:01:12 PM PDT 24
Finished Jun 11 03:03:47 PM PDT 24
Peak memory 290976 kb
Host smart-0ae75701-b61c-4626-a9ac-ecb5b5f4c80b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357034752 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3357034752
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4068581196
Short name T943
Test name
Test status
Simulation time 85966501100 ps
CPU time 248.77 seconds
Started Jun 11 02:59:52 PM PDT 24
Finished Jun 11 03:04:01 PM PDT 24
Peak memory 260632 kb
Host smart-c064554e-d2f5-4c1d-873d-6dc64223e40a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406
8581196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.4068581196
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1253535489
Short name T84
Test name
Test status
Simulation time 4313857900 ps
CPU time 72.48 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:00:54 PM PDT 24
Peak memory 260704 kb
Host smart-d4cbb014-bc33-4952-8480-91248e9211c1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253535489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1253535489
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.4245917527
Short name T630
Test name
Test status
Simulation time 15412300 ps
CPU time 13.28 seconds
Started Jun 11 03:00:14 PM PDT 24
Finished Jun 11 03:00:29 PM PDT 24
Peak memory 265312 kb
Host smart-8d38a664-7623-4276-b58d-5b0fc1eb8259
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245917527 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.4245917527
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3129092570
Short name T996
Test name
Test status
Simulation time 67637800 ps
CPU time 131.54 seconds
Started Jun 11 02:59:22 PM PDT 24
Finished Jun 11 03:01:35 PM PDT 24
Peak memory 261420 kb
Host smart-10534bf8-c048-4979-b390-a3f8800e1876
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129092570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3129092570
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.1660793573
Short name T750
Test name
Test status
Simulation time 6739699800 ps
CPU time 223.99 seconds
Started Jun 11 02:59:50 PM PDT 24
Finished Jun 11 03:03:34 PM PDT 24
Peak memory 295080 kb
Host smart-56f88bb6-8bd9-4c7e-ae40-89c9e4f05115
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660793573 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1660793573
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2040064145
Short name T213
Test name
Test status
Simulation time 125902900 ps
CPU time 282.4 seconds
Started Jun 11 02:59:11 PM PDT 24
Finished Jun 11 03:03:54 PM PDT 24
Peak memory 263508 kb
Host smart-f910c755-e806-4daf-99b3-03aaf0ff57fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040064145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2040064145
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1791911610
Short name T230
Test name
Test status
Simulation time 69879700 ps
CPU time 13.85 seconds
Started Jun 11 03:00:12 PM PDT 24
Finished Jun 11 03:00:27 PM PDT 24
Peak memory 262968 kb
Host smart-602a96a5-43e6-4d9c-9d0a-eb99dfb9590a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791911610 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1791911610
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1841230511
Short name T93
Test name
Test status
Simulation time 24106400 ps
CPU time 13.32 seconds
Started Jun 11 02:59:51 PM PDT 24
Finished Jun 11 03:00:05 PM PDT 24
Peak memory 258948 kb
Host smart-500c6a1a-0332-4cd9-9b7e-9cfe0dca25f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841230511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1841230511
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1907880374
Short name T1029
Test name
Test status
Simulation time 1077761800 ps
CPU time 322.54 seconds
Started Jun 11 02:59:13 PM PDT 24
Finished Jun 11 03:04:36 PM PDT 24
Peak memory 281976 kb
Host smart-2fee6b0f-415b-49c3-a54b-2f7af958f899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907880374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1907880374
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.487256954
Short name T57
Test name
Test status
Simulation time 729694600 ps
CPU time 123.44 seconds
Started Jun 11 02:59:16 PM PDT 24
Finished Jun 11 03:01:20 PM PDT 24
Peak memory 262908 kb
Host smart-e82a15b2-fb22-497d-8f07-34812492e7fc
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=487256954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.487256954
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2927789726
Short name T181
Test name
Test status
Simulation time 373424800 ps
CPU time 32.26 seconds
Started Jun 11 03:00:04 PM PDT 24
Finished Jun 11 03:00:37 PM PDT 24
Peak memory 272820 kb
Host smart-d16e8a49-2e04-4b03-9026-3c7e767846ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927789726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2927789726
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.48997453
Short name T595
Test name
Test status
Simulation time 201211100 ps
CPU time 34.52 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 03:00:37 PM PDT 24
Peak memory 275692 kb
Host smart-b4fa5a8e-bd6e-4a5b-abff-8d097a2ae6cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48997453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_re_evict.48997453
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3298789130
Short name T438
Test name
Test status
Simulation time 77879100 ps
CPU time 22.72 seconds
Started Jun 11 02:59:42 PM PDT 24
Finished Jun 11 03:00:06 PM PDT 24
Peak memory 265732 kb
Host smart-ef06628c-189a-4d30-b51b-9408c4602e64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298789130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.3298789130
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2281097038
Short name T81
Test name
Test status
Simulation time 70393751600 ps
CPU time 827 seconds
Started Jun 11 03:01:28 PM PDT 24
Finished Jun 11 03:15:16 PM PDT 24
Peak memory 264784 kb
Host smart-0b70c5e5-ba2e-4b5e-9af3-276624e16183
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281097038 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2281097038
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2957999345
Short name T935
Test name
Test status
Simulation time 913214900 ps
CPU time 166.37 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:02:28 PM PDT 24
Peak memory 297732 kb
Host smart-20dab2ff-552f-4e70-8b91-0d81d309d0d4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957999345 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.2957999345
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.2143724885
Short name T170
Test name
Test status
Simulation time 1284536700 ps
CPU time 202.27 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:03:04 PM PDT 24
Peak memory 283288 kb
Host smart-1df82246-f59e-463a-be08-7ce1bbd0ffd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2143724885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2143724885
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2585016221
Short name T194
Test name
Test status
Simulation time 1443502900 ps
CPU time 161.62 seconds
Started Jun 11 02:59:40 PM PDT 24
Finished Jun 11 03:02:22 PM PDT 24
Peak memory 282240 kb
Host smart-f1bf809c-defe-414e-bb46-e20bb4c90407
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585016221 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2585016221
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.967355366
Short name T184
Test name
Test status
Simulation time 19346053900 ps
CPU time 483.73 seconds
Started Jun 11 03:01:01 PM PDT 24
Finished Jun 11 03:09:07 PM PDT 24
Peak memory 313596 kb
Host smart-0f6f6312-08ee-455c-9d30-85279fc62769
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967355366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_rw.967355366
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.492041837
Short name T175
Test name
Test status
Simulation time 15502990400 ps
CPU time 713.14 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:11:35 PM PDT 24
Peak memory 337688 kb
Host smart-fe521e40-5d93-4e93-8722-c8edd8d0d3e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492041837 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_rw_derr.492041837
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3512912102
Short name T736
Test name
Test status
Simulation time 34671000 ps
CPU time 32.1 seconds
Started Jun 11 02:59:50 PM PDT 24
Finished Jun 11 03:00:23 PM PDT 24
Peak memory 277016 kb
Host smart-fca260b9-2abf-403e-a122-11faa4d3b7d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512912102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3512912102
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3069510439
Short name T226
Test name
Test status
Simulation time 19476868600 ps
CPU time 632.68 seconds
Started Jun 11 02:59:42 PM PDT 24
Finished Jun 11 03:10:15 PM PDT 24
Peak memory 321164 kb
Host smart-e4b93273-a96f-41ca-8224-8ba0be4db850
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069510439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3069510439
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3159918628
Short name T208
Test name
Test status
Simulation time 7055668500 ps
CPU time 74.94 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 03:01:18 PM PDT 24
Peak memory 263896 kb
Host smart-a43cc728-2e3b-4243-a756-6dbc6aa409fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159918628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3159918628
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3658230697
Short name T527
Test name
Test status
Simulation time 3498391800 ps
CPU time 97.92 seconds
Started Jun 11 02:59:41 PM PDT 24
Finished Jun 11 03:01:19 PM PDT 24
Peak memory 265276 kb
Host smart-15cd0944-ea92-4e6d-bfc0-29b7f8d4ab9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658230697 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3658230697
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.751805112
Short name T522
Test name
Test status
Simulation time 1170006600 ps
CPU time 61.35 seconds
Started Jun 11 02:59:42 PM PDT 24
Finished Jun 11 03:00:45 PM PDT 24
Peak memory 274012 kb
Host smart-44e14044-b4b7-4574-84b1-66891470b017
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751805112 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_counter.751805112
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.936083831
Short name T557
Test name
Test status
Simulation time 81741500 ps
CPU time 144.8 seconds
Started Jun 11 02:59:07 PM PDT 24
Finished Jun 11 03:01:33 PM PDT 24
Peak memory 278344 kb
Host smart-db81330a-2c3b-45aa-9637-02362109f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936083831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.936083831
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.586099021
Short name T1082
Test name
Test status
Simulation time 232172300 ps
CPU time 23.58 seconds
Started Jun 11 02:59:13 PM PDT 24
Finished Jun 11 02:59:38 PM PDT 24
Peak memory 260164 kb
Host smart-50d2fe52-e27f-4f56-8793-d079adede4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586099021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.586099021
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1817283800
Short name T463
Test name
Test status
Simulation time 710564500 ps
CPU time 1678.89 seconds
Started Jun 11 03:00:02 PM PDT 24
Finished Jun 11 03:28:02 PM PDT 24
Peak memory 290160 kb
Host smart-61200303-48cb-4a5d-b3ea-356940f84f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817283800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1817283800
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.1348549848
Short name T519
Test name
Test status
Simulation time 36690000 ps
CPU time 26.46 seconds
Started Jun 11 02:59:14 PM PDT 24
Finished Jun 11 02:59:41 PM PDT 24
Peak memory 262660 kb
Host smart-cead1eea-932e-4c4b-8055-47fe7245933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348549848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1348549848
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3079105648
Short name T946
Test name
Test status
Simulation time 2206810600 ps
CPU time 194.39 seconds
Started Jun 11 02:59:40 PM PDT 24
Finished Jun 11 03:02:56 PM PDT 24
Peak memory 265544 kb
Host smart-c29e8249-8d54-4c18-8cb0-32375586d708
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079105648 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.3079105648
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.4093412396
Short name T234
Test name
Test status
Simulation time 44503400 ps
CPU time 15.35 seconds
Started Jun 11 03:00:03 PM PDT 24
Finished Jun 11 03:00:19 PM PDT 24
Peak memory 265800 kb
Host smart-98f44f6d-62b4-4eb4-b5fd-51f70d69eb84
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093412396 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.4093412396
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.453314755
Short name T652
Test name
Test status
Simulation time 135821300 ps
CPU time 13.95 seconds
Started Jun 11 03:07:50 PM PDT 24
Finished Jun 11 03:08:05 PM PDT 24
Peak memory 265548 kb
Host smart-3e48dce7-545c-4dd3-ac48-e0300c38559b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453314755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.453314755
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.3220717691
Short name T586
Test name
Test status
Simulation time 15419800 ps
CPU time 15.99 seconds
Started Jun 11 03:07:48 PM PDT 24
Finished Jun 11 03:08:05 PM PDT 24
Peak memory 284420 kb
Host smart-0cf3a6f3-babf-43f0-907c-e365b33bf145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220717691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3220717691
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3450630564
Short name T616
Test name
Test status
Simulation time 10011877500 ps
CPU time 96.97 seconds
Started Jun 11 03:07:48 PM PDT 24
Finished Jun 11 03:09:25 PM PDT 24
Peak memory 282704 kb
Host smart-85bd1273-6cf6-40a7-a6dd-83dee966ba74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450630564 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.3450630564
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2944906177
Short name T670
Test name
Test status
Simulation time 15142076500 ps
CPU time 148.68 seconds
Started Jun 11 03:07:34 PM PDT 24
Finished Jun 11 03:10:04 PM PDT 24
Peak memory 262812 kb
Host smart-f57dd179-34a9-495e-8434-34bdfe8390bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944906177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2944906177
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.19446511
Short name T347
Test name
Test status
Simulation time 649138300 ps
CPU time 132.96 seconds
Started Jun 11 03:07:40 PM PDT 24
Finished Jun 11 03:09:54 PM PDT 24
Peak memory 295412 kb
Host smart-f555bf58-5d78-4b19-87da-c5e43a93633f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash
_ctrl_intr_rd.19446511
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2633252747
Short name T918
Test name
Test status
Simulation time 5777814400 ps
CPU time 118.1 seconds
Started Jun 11 03:07:42 PM PDT 24
Finished Jun 11 03:09:41 PM PDT 24
Peak memory 293356 kb
Host smart-cf2004c2-1293-46a6-8e93-1a6e402b14b9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633252747 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2633252747
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2110623946
Short name T1044
Test name
Test status
Simulation time 2101955200 ps
CPU time 68.55 seconds
Started Jun 11 03:07:31 PM PDT 24
Finished Jun 11 03:08:42 PM PDT 24
Peak memory 263620 kb
Host smart-606e52c2-57e3-46fa-9673-4bb007c40479
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110623946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
110623946
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1863996745
Short name T293
Test name
Test status
Simulation time 26197900 ps
CPU time 13.39 seconds
Started Jun 11 03:07:50 PM PDT 24
Finished Jun 11 03:08:04 PM PDT 24
Peak memory 265812 kb
Host smart-6e59c6f2-9e54-4fe7-b58d-839a339223f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863996745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1863996745
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.513030684
Short name T131
Test name
Test status
Simulation time 145836100 ps
CPU time 131.47 seconds
Started Jun 11 03:07:31 PM PDT 24
Finished Jun 11 03:09:44 PM PDT 24
Peak memory 260528 kb
Host smart-8d6f6a2b-6dc6-47dd-b381-38e33287e785
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513030684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot
p_reset.513030684
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3821459546
Short name T548
Test name
Test status
Simulation time 1482159600 ps
CPU time 450.44 seconds
Started Jun 11 03:07:30 PM PDT 24
Finished Jun 11 03:15:02 PM PDT 24
Peak memory 263496 kb
Host smart-11481d1e-e780-4e44-8fcb-8576519eca31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821459546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3821459546
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.364525308
Short name T593
Test name
Test status
Simulation time 18600100 ps
CPU time 13.46 seconds
Started Jun 11 03:07:41 PM PDT 24
Finished Jun 11 03:07:55 PM PDT 24
Peak memory 259076 kb
Host smart-40a91d82-ab86-4e84-a7e6-426c92d9328e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364525308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_res
et.364525308
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.3428097567
Short name T997
Test name
Test status
Simulation time 318099500 ps
CPU time 706.13 seconds
Started Jun 11 03:07:32 PM PDT 24
Finished Jun 11 03:19:20 PM PDT 24
Peak memory 284092 kb
Host smart-85becc3b-2a2b-45ce-a918-559d82dcd8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428097567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3428097567
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.4223379349
Short name T500
Test name
Test status
Simulation time 1141289800 ps
CPU time 36.68 seconds
Started Jun 11 03:07:41 PM PDT 24
Finished Jun 11 03:08:19 PM PDT 24
Peak memory 277108 kb
Host smart-778eafbf-55a9-4ae4-92fc-24d581bdc81b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223379349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.4223379349
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2208731621
Short name T287
Test name
Test status
Simulation time 1295213700 ps
CPU time 114.62 seconds
Started Jun 11 03:07:41 PM PDT 24
Finished Jun 11 03:09:36 PM PDT 24
Peak memory 290388 kb
Host smart-94da4233-9a09-42cf-851b-29fc16de83ef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208731621 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2208731621
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1820572641
Short name T185
Test name
Test status
Simulation time 7093609100 ps
CPU time 547.76 seconds
Started Jun 11 03:07:39 PM PDT 24
Finished Jun 11 03:16:48 PM PDT 24
Peak memory 309844 kb
Host smart-0efd2002-ff2c-470d-9aee-0217ea53122f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820572641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.1820572641
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3920197974
Short name T526
Test name
Test status
Simulation time 80883300 ps
CPU time 30.94 seconds
Started Jun 11 03:07:40 PM PDT 24
Finished Jun 11 03:08:12 PM PDT 24
Peak memory 267880 kb
Host smart-f4367648-f6ca-45bf-9d80-11a67b5c6c62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920197974 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3920197974
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.743258089
Short name T249
Test name
Test status
Simulation time 2022444200 ps
CPU time 68.96 seconds
Started Jun 11 03:07:40 PM PDT 24
Finished Jun 11 03:08:50 PM PDT 24
Peak memory 263624 kb
Host smart-3204b662-aec2-416b-81ef-8cf91549f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743258089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.743258089
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.463410093
Short name T441
Test name
Test status
Simulation time 58803300 ps
CPU time 190.6 seconds
Started Jun 11 03:07:32 PM PDT 24
Finished Jun 11 03:10:44 PM PDT 24
Peak memory 277956 kb
Host smart-03271d3c-68cb-45ef-8987-e8c0434ba735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463410093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.463410093
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.217626639
Short name T484
Test name
Test status
Simulation time 6912385500 ps
CPU time 204.97 seconds
Started Jun 11 03:07:41 PM PDT 24
Finished Jun 11 03:11:06 PM PDT 24
Peak memory 265676 kb
Host smart-a7c8b7c2-8fb0-4ed8-b085-4331305c6ffa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217626639 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.217626639
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1972717935
Short name T457
Test name
Test status
Simulation time 467425700 ps
CPU time 13.71 seconds
Started Jun 11 03:08:21 PM PDT 24
Finished Jun 11 03:08:36 PM PDT 24
Peak memory 258540 kb
Host smart-2156e85f-7b4c-4e4d-bb5b-bcc62b117b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972717935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1972717935
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.803740283
Short name T414
Test name
Test status
Simulation time 46439600 ps
CPU time 15.56 seconds
Started Jun 11 03:08:23 PM PDT 24
Finished Jun 11 03:08:40 PM PDT 24
Peak memory 284596 kb
Host smart-ea9d07e1-3afd-462e-b7a9-3fb333f5eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803740283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.803740283
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.1666395841
Short name T846
Test name
Test status
Simulation time 18252800 ps
CPU time 21.9 seconds
Started Jun 11 03:08:14 PM PDT 24
Finished Jun 11 03:08:37 PM PDT 24
Peak memory 274084 kb
Host smart-6dd2bf6d-116c-4bd1-9fed-e62428451627
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666395841 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.1666395841
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3206202495
Short name T975
Test name
Test status
Simulation time 10059679100 ps
CPU time 81.14 seconds
Started Jun 11 03:08:22 PM PDT 24
Finished Jun 11 03:09:45 PM PDT 24
Peak memory 265720 kb
Host smart-40d0b74f-0fed-4b7f-8f4f-3ad4704fef56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206202495 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3206202495
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2000244805
Short name T480
Test name
Test status
Simulation time 15810500 ps
CPU time 13.39 seconds
Started Jun 11 03:08:23 PM PDT 24
Finished Jun 11 03:08:37 PM PDT 24
Peak memory 265840 kb
Host smart-b14d3b48-6006-4b06-bb91-d4004ed3739c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000244805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2000244805
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3996534538
Short name T513
Test name
Test status
Simulation time 80139609600 ps
CPU time 832.5 seconds
Started Jun 11 03:07:58 PM PDT 24
Finished Jun 11 03:21:52 PM PDT 24
Peak memory 264832 kb
Host smart-58366170-e816-435b-9c6f-1734b9b6a27b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996534538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3996534538
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2416554439
Short name T813
Test name
Test status
Simulation time 3118036600 ps
CPU time 92.89 seconds
Started Jun 11 03:07:50 PM PDT 24
Finished Jun 11 03:09:24 PM PDT 24
Peak memory 263480 kb
Host smart-7d767dba-02c8-40e2-9e8f-ca360d99ba38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416554439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.2416554439
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3057276937
Short name T404
Test name
Test status
Simulation time 11779363700 ps
CPU time 148.16 seconds
Started Jun 11 03:08:17 PM PDT 24
Finished Jun 11 03:10:46 PM PDT 24
Peak memory 294436 kb
Host smart-32685ff6-e058-4fd4-8913-dc71363a3729
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057276937 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3057276937
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1236229185
Short name T784
Test name
Test status
Simulation time 4056679100 ps
CPU time 81.59 seconds
Started Jun 11 03:07:58 PM PDT 24
Finished Jun 11 03:09:20 PM PDT 24
Peak memory 260968 kb
Host smart-d9543c4f-9935-482a-b933-16965245becc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236229185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
236229185
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3219676240
Short name T579
Test name
Test status
Simulation time 15546800 ps
CPU time 13.58 seconds
Started Jun 11 03:08:22 PM PDT 24
Finished Jun 11 03:08:37 PM PDT 24
Peak memory 260200 kb
Host smart-fcfccd12-fd27-48bf-a5d2-8d0aace7bbb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219676240 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3219676240
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3260532891
Short name T1043
Test name
Test status
Simulation time 19017857600 ps
CPU time 413.79 seconds
Started Jun 11 03:07:59 PM PDT 24
Finished Jun 11 03:14:53 PM PDT 24
Peak memory 275180 kb
Host smart-db6aad0d-4144-41f3-a511-d5172c8ff61c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260532891 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3260532891
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.1697448217
Short name T844
Test name
Test status
Simulation time 88039800 ps
CPU time 134.26 seconds
Started Jun 11 03:07:56 PM PDT 24
Finished Jun 11 03:10:12 PM PDT 24
Peak memory 260204 kb
Host smart-6a4084c1-1903-420d-9df1-99b59dc23310
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697448217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.1697448217
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2727933627
Short name T599
Test name
Test status
Simulation time 118431300 ps
CPU time 151.75 seconds
Started Jun 11 03:07:48 PM PDT 24
Finished Jun 11 03:10:21 PM PDT 24
Peak memory 263600 kb
Host smart-afc2579e-1590-4691-bdd5-572eb9c524e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727933627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2727933627
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.882386793
Short name T706
Test name
Test status
Simulation time 116674200 ps
CPU time 13.87 seconds
Started Jun 11 03:08:15 PM PDT 24
Finished Jun 11 03:08:31 PM PDT 24
Peak memory 259040 kb
Host smart-15cf4c55-c297-414b-b134-a66228b47c61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882386793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_res
et.882386793
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2185957884
Short name T43
Test name
Test status
Simulation time 64472500 ps
CPU time 280.89 seconds
Started Jun 11 03:07:48 PM PDT 24
Finished Jun 11 03:12:30 PM PDT 24
Peak memory 275464 kb
Host smart-a25303fa-1f06-43f3-90cc-21a4102d73df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185957884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2185957884
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3667558445
Short name T21
Test name
Test status
Simulation time 102156500 ps
CPU time 37.38 seconds
Started Jun 11 03:08:14 PM PDT 24
Finished Jun 11 03:08:53 PM PDT 24
Peak memory 275820 kb
Host smart-89cc28b3-9122-4e8f-ab4b-dde9423d74b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667558445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3667558445
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.1460061008
Short name T835
Test name
Test status
Simulation time 485101800 ps
CPU time 118.11 seconds
Started Jun 11 03:08:08 PM PDT 24
Finished Jun 11 03:10:08 PM PDT 24
Peak memory 290404 kb
Host smart-f1a354e0-96f5-4e23-9efa-b87041d42360
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460061008 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.1460061008
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.2000420144
Short name T798
Test name
Test status
Simulation time 9763223400 ps
CPU time 579.44 seconds
Started Jun 11 03:08:06 PM PDT 24
Finished Jun 11 03:17:47 PM PDT 24
Peak memory 315032 kb
Host smart-879cc2f5-7404-44c2-9d91-4d250687d010
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000420144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.2000420144
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3774596090
Short name T933
Test name
Test status
Simulation time 83183000 ps
CPU time 98.3 seconds
Started Jun 11 03:07:49 PM PDT 24
Finished Jun 11 03:09:28 PM PDT 24
Peak memory 269952 kb
Host smart-5aaa89b9-c6e0-4315-a913-753f86bf1fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774596090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3774596090
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.105909813
Short name T97
Test name
Test status
Simulation time 13136181600 ps
CPU time 239.71 seconds
Started Jun 11 03:07:57 PM PDT 24
Finished Jun 11 03:11:58 PM PDT 24
Peak memory 265472 kb
Host smart-0c8159c6-c3c2-4387-af4a-349687a1c363
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105909813 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.105909813
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.2011521291
Short name T998
Test name
Test status
Simulation time 22766000 ps
CPU time 13.37 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:08:56 PM PDT 24
Peak memory 265684 kb
Host smart-389c7256-5389-42be-956e-6a3fe8c03178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011521291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
2011521291
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.2106207311
Short name T54
Test name
Test status
Simulation time 66092500 ps
CPU time 15.56 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:08:58 PM PDT 24
Peak memory 284456 kb
Host smart-a4b1090e-a26b-4d33-b69b-70850f98baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106207311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2106207311
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1694359972
Short name T640
Test name
Test status
Simulation time 18772300 ps
CPU time 21.4 seconds
Started Jun 11 03:08:39 PM PDT 24
Finished Jun 11 03:09:01 PM PDT 24
Peak memory 274076 kb
Host smart-a3f8df6b-f634-44ca-a912-894e491884e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694359972 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1694359972
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2039419443
Short name T884
Test name
Test status
Simulation time 10034536100 ps
CPU time 113.55 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:10:36 PM PDT 24
Peak memory 275560 kb
Host smart-aa4ade4e-859d-400c-8559-b7d416261fc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039419443 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2039419443
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2482631927
Short name T115
Test name
Test status
Simulation time 24904000 ps
CPU time 13.77 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:08:56 PM PDT 24
Peak memory 258864 kb
Host smart-cb6d3269-320b-45a8-9eb2-893f1f3e63ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482631927 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2482631927
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1874793852
Short name T1084
Test name
Test status
Simulation time 420249567500 ps
CPU time 1088.09 seconds
Started Jun 11 03:08:33 PM PDT 24
Finished Jun 11 03:26:43 PM PDT 24
Peak memory 261416 kb
Host smart-9d1d8a7b-5909-4f70-a3f0-22f89080ea8c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874793852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1874793852
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.4119250664
Short name T988
Test name
Test status
Simulation time 1464231200 ps
CPU time 124.92 seconds
Started Jun 11 03:08:33 PM PDT 24
Finished Jun 11 03:10:39 PM PDT 24
Peak memory 262948 kb
Host smart-3ab85c8d-357d-4f18-8a36-12baeea12499
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119250664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.4119250664
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.871558646
Short name T415
Test name
Test status
Simulation time 24553765900 ps
CPU time 170.21 seconds
Started Jun 11 03:08:32 PM PDT 24
Finished Jun 11 03:11:24 PM PDT 24
Peak memory 292816 kb
Host smart-b7ddbd6d-161d-4a55-8bf2-119aaded1f13
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871558646 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.871558646
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2444545108
Short name T602
Test name
Test status
Simulation time 3290598500 ps
CPU time 68.19 seconds
Started Jun 11 03:08:31 PM PDT 24
Finished Jun 11 03:09:41 PM PDT 24
Peak memory 260760 kb
Host smart-894bc7d5-420f-420c-9b59-da854d501211
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444545108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
444545108
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.247159965
Short name T116
Test name
Test status
Simulation time 156819500 ps
CPU time 13.43 seconds
Started Jun 11 03:08:39 PM PDT 24
Finished Jun 11 03:08:53 PM PDT 24
Peak memory 260268 kb
Host smart-e1755e0b-cc95-4efc-bbb3-171447dbd2ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247159965 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.247159965
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.2548023620
Short name T91
Test name
Test status
Simulation time 19174521600 ps
CPU time 782.73 seconds
Started Jun 11 03:08:32 PM PDT 24
Finished Jun 11 03:21:37 PM PDT 24
Peak memory 275456 kb
Host smart-a70fecf5-96a4-4870-9f26-0ac264c0614a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548023620 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.2548023620
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1235853178
Short name T122
Test name
Test status
Simulation time 136595500 ps
CPU time 132.84 seconds
Started Jun 11 03:08:32 PM PDT 24
Finished Jun 11 03:10:47 PM PDT 24
Peak memory 261376 kb
Host smart-2199813b-5a88-402e-a6ca-16f94af8b9a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235853178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1235853178
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.79964127
Short name T700
Test name
Test status
Simulation time 41274000 ps
CPU time 68.45 seconds
Started Jun 11 03:08:33 PM PDT 24
Finished Jun 11 03:09:43 PM PDT 24
Peak memory 263376 kb
Host smart-ae428012-8746-4979-88cb-ac8e261a4f6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=79964127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.79964127
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.2794087785
Short name T666
Test name
Test status
Simulation time 40256200 ps
CPU time 13.58 seconds
Started Jun 11 03:08:31 PM PDT 24
Finished Jun 11 03:08:46 PM PDT 24
Peak memory 265684 kb
Host smart-708fdc3a-777a-49eb-9374-1ea961d9530f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794087785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.2794087785
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.2233460845
Short name T696
Test name
Test status
Simulation time 3546183000 ps
CPU time 724.37 seconds
Started Jun 11 03:08:33 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 284704 kb
Host smart-4a921ba8-fe93-493e-a0fb-25d56b758183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233460845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2233460845
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.4084402329
Short name T570
Test name
Test status
Simulation time 330598600 ps
CPU time 36.97 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:09:19 PM PDT 24
Peak memory 275728 kb
Host smart-6f34959b-0849-4351-975c-29a376513847
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084402329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.4084402329
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2851099237
Short name T173
Test name
Test status
Simulation time 2034756500 ps
CPU time 126.28 seconds
Started Jun 11 03:08:32 PM PDT 24
Finished Jun 11 03:10:39 PM PDT 24
Peak memory 282240 kb
Host smart-0921b321-3c3c-4127-8d4b-589b2f4046ef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851099237 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.2851099237
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1512646553
Short name T490
Test name
Test status
Simulation time 4856864400 ps
CPU time 679.03 seconds
Started Jun 11 03:08:31 PM PDT 24
Finished Jun 11 03:19:51 PM PDT 24
Peak memory 309832 kb
Host smart-17f6c222-f8a4-4481-ba02-09e569bf3780
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512646553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.1512646553
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.2901775591
Short name T1010
Test name
Test status
Simulation time 28149800 ps
CPU time 31.15 seconds
Started Jun 11 03:08:39 PM PDT 24
Finished Jun 11 03:09:11 PM PDT 24
Peak memory 273492 kb
Host smart-87ba04f7-2c0c-43ab-bef5-a9fee58dcb25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901775591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.2901775591
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.4275966806
Short name T833
Test name
Test status
Simulation time 1742334500 ps
CPU time 71.81 seconds
Started Jun 11 03:08:41 PM PDT 24
Finished Jun 11 03:09:54 PM PDT 24
Peak memory 263848 kb
Host smart-240b90b1-c03c-4c6b-bb11-68f939cbfb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275966806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.4275966806
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.1926256570
Short name T468
Test name
Test status
Simulation time 804835900 ps
CPU time 243.24 seconds
Started Jun 11 03:08:22 PM PDT 24
Finished Jun 11 03:12:27 PM PDT 24
Peak memory 281564 kb
Host smart-e6959e36-686f-4106-92c0-3060e69dbf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926256570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1926256570
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2655865552
Short name T450
Test name
Test status
Simulation time 10078323200 ps
CPU time 210.66 seconds
Started Jun 11 03:08:31 PM PDT 24
Finished Jun 11 03:12:03 PM PDT 24
Peak memory 260304 kb
Host smart-2d780b84-cf29-4c82-b72d-9de45546befa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655865552 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.2655865552
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3916069251
Short name T521
Test name
Test status
Simulation time 104904700 ps
CPU time 13.59 seconds
Started Jun 11 03:09:14 PM PDT 24
Finished Jun 11 03:09:28 PM PDT 24
Peak memory 258628 kb
Host smart-fc58ef8c-2b77-48c4-850c-24868e3332f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916069251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3916069251
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.19753520
Short name T563
Test name
Test status
Simulation time 24357300 ps
CPU time 15.96 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:09:33 PM PDT 24
Peak memory 284536 kb
Host smart-874c92fd-4c6b-4814-abb2-7bab843933fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19753520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.19753520
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3195180810
Short name T370
Test name
Test status
Simulation time 35069300 ps
CPU time 21.3 seconds
Started Jun 11 03:09:05 PM PDT 24
Finished Jun 11 03:09:27 PM PDT 24
Peak memory 273956 kb
Host smart-f9d21eeb-0c6c-4fac-940a-de0e22077e05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195180810 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3195180810
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.4118669113
Short name T289
Test name
Test status
Simulation time 14937000 ps
CPU time 13.53 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:09:30 PM PDT 24
Peak memory 259740 kb
Host smart-3244d218-c8b2-4df2-b0ea-11b542f0b18b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118669113 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.4118669113
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1445341224
Short name T995
Test name
Test status
Simulation time 100143613300 ps
CPU time 827.8 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:22:38 PM PDT 24
Peak memory 264636 kb
Host smart-adcab9ee-066a-42f9-bb95-bb51eeafbcb6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445341224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1445341224
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.961760201
Short name T920
Test name
Test status
Simulation time 3361418700 ps
CPU time 291.05 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:13:41 PM PDT 24
Peak memory 263432 kb
Host smart-1acfa0c2-44d5-4955-9584-b752b14655ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961760201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_h
w_sec_otp.961760201
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.4205166968
Short name T405
Test name
Test status
Simulation time 37127220300 ps
CPU time 147.36 seconds
Started Jun 11 03:08:58 PM PDT 24
Finished Jun 11 03:11:26 PM PDT 24
Peak memory 293412 kb
Host smart-6ecb1505-1f83-46f0-88f8-cc403ec2d755
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205166968 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.4205166968
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.1428869773
Short name T806
Test name
Test status
Simulation time 2017163500 ps
CPU time 83.3 seconds
Started Jun 11 03:08:50 PM PDT 24
Finished Jun 11 03:10:15 PM PDT 24
Peak memory 260860 kb
Host smart-748369be-4976-4f8c-8dca-21bf54e00ee6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428869773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1
428869773
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3907187355
Short name T954
Test name
Test status
Simulation time 22213800 ps
CPU time 13.46 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:09:30 PM PDT 24
Peak memory 260256 kb
Host smart-899c7004-fa1f-4fe4-a805-d9b4ee561a2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907187355 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3907187355
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.329006252
Short name T92
Test name
Test status
Simulation time 16978482900 ps
CPU time 1055.04 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:26:25 PM PDT 24
Peak memory 274900 kb
Host smart-f53eed93-b665-437a-ab17-89d51bf0ff08
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329006252 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.329006252
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.3933064354
Short name T748
Test name
Test status
Simulation time 71781800 ps
CPU time 110.53 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:10:40 PM PDT 24
Peak memory 261376 kb
Host smart-fc1a3630-fc6d-4fed-a792-79c0750006f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933064354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.3933064354
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.2006895420
Short name T622
Test name
Test status
Simulation time 166242500 ps
CPU time 323.33 seconds
Started Jun 11 03:08:51 PM PDT 24
Finished Jun 11 03:14:15 PM PDT 24
Peak memory 263504 kb
Host smart-45c68b9e-b082-4808-b050-d308083aabc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006895420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2006895420
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.1489084409
Short name T436
Test name
Test status
Simulation time 37617500 ps
CPU time 13.45 seconds
Started Jun 11 03:08:57 PM PDT 24
Finished Jun 11 03:09:11 PM PDT 24
Peak memory 265520 kb
Host smart-9784ba52-f0c2-47e6-8fa7-88137c136808
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489084409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.1489084409
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.1098479168
Short name T909
Test name
Test status
Simulation time 78560700 ps
CPU time 72.26 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:10:02 PM PDT 24
Peak memory 275756 kb
Host smart-3da0c18a-2883-4477-b068-16e4fd9877a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098479168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.1098479168
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.4182045847
Short name T643
Test name
Test status
Simulation time 93708300 ps
CPU time 34.32 seconds
Started Jun 11 03:08:58 PM PDT 24
Finished Jun 11 03:09:33 PM PDT 24
Peak memory 275808 kb
Host smart-cb833882-cbd5-4255-9967-34443b54b715
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182045847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.4182045847
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.4276900763
Short name T561
Test name
Test status
Simulation time 3327003200 ps
CPU time 119.72 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:10:49 PM PDT 24
Peak memory 281168 kb
Host smart-b4f73ba3-8499-4a40-9698-dd8ced6bfd7f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276900763 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.4276900763
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2714690961
Short name T206
Test name
Test status
Simulation time 4064662700 ps
CPU time 654.67 seconds
Started Jun 11 03:08:52 PM PDT 24
Finished Jun 11 03:19:47 PM PDT 24
Peak memory 309788 kb
Host smart-85c88425-0d26-49a3-9484-bd8a6d04253a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714690961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.2714690961
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1104767083
Short name T1069
Test name
Test status
Simulation time 83823900 ps
CPU time 31.77 seconds
Started Jun 11 03:09:00 PM PDT 24
Finished Jun 11 03:09:33 PM PDT 24
Peak memory 278672 kb
Host smart-cbfb83af-2827-42b3-ae49-e957820b7227
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104767083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1104767083
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.3763810595
Short name T392
Test name
Test status
Simulation time 612715600 ps
CPU time 69.4 seconds
Started Jun 11 03:09:05 PM PDT 24
Finished Jun 11 03:10:15 PM PDT 24
Peak memory 263892 kb
Host smart-8465cce4-a5f6-445f-8043-ab08efe42ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763810595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3763810595
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.4036310595
Short name T891
Test name
Test status
Simulation time 39013700 ps
CPU time 122.32 seconds
Started Jun 11 03:08:49 PM PDT 24
Finished Jun 11 03:10:53 PM PDT 24
Peak memory 276660 kb
Host smart-d559eab2-4c01-4bbe-82d4-f7e71c5b2020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036310595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.4036310595
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.2357690953
Short name T82
Test name
Test status
Simulation time 5367029200 ps
CPU time 244.6 seconds
Started Jun 11 03:08:48 PM PDT 24
Finished Jun 11 03:12:53 PM PDT 24
Peak memory 265724 kb
Host smart-ca078bde-a867-443a-b0a2-53fcfc35dac0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357690953 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.2357690953
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.672670759
Short name T205
Test name
Test status
Simulation time 17500000 ps
CPU time 16.16 seconds
Started Jun 11 03:09:35 PM PDT 24
Finished Jun 11 03:09:52 PM PDT 24
Peak memory 284544 kb
Host smart-561c14b2-890f-4b5b-96c1-0bc7eab66d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672670759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.672670759
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3677891274
Short name T460
Test name
Test status
Simulation time 109623700 ps
CPU time 21.87 seconds
Started Jun 11 03:09:34 PM PDT 24
Finished Jun 11 03:09:57 PM PDT 24
Peak memory 274220 kb
Host smart-9deecd30-9dbf-42d1-8107-c2b712249fe6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677891274 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3677891274
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.453855967
Short name T588
Test name
Test status
Simulation time 10034952700 ps
CPU time 67.89 seconds
Started Jun 11 03:09:35 PM PDT 24
Finished Jun 11 03:10:44 PM PDT 24
Peak memory 293668 kb
Host smart-bc388f31-f9c2-482a-8716-9b37ebb2ca08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453855967 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.453855967
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2271709111
Short name T767
Test name
Test status
Simulation time 18823800 ps
CPU time 13.27 seconds
Started Jun 11 03:09:35 PM PDT 24
Finished Jun 11 03:09:49 PM PDT 24
Peak memory 265160 kb
Host smart-30a99b0a-981b-477c-8864-9ae57c3ee650
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271709111 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2271709111
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2979051538
Short name T382
Test name
Test status
Simulation time 80135327600 ps
CPU time 897.85 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 264664 kb
Host smart-f0aac26c-fb8a-4a17-b2f1-b21bdce7216d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979051538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2979051538
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.3676534228
Short name T567
Test name
Test status
Simulation time 4586909300 ps
CPU time 95.22 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:11:01 PM PDT 24
Peak memory 263352 kb
Host smart-baef2c93-ba58-4225-a74f-0bd11263c3e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676534228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.3676534228
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.638676700
Short name T37
Test name
Test status
Simulation time 1925715000 ps
CPU time 218.32 seconds
Started Jun 11 03:09:24 PM PDT 24
Finished Jun 11 03:13:03 PM PDT 24
Peak memory 291328 kb
Host smart-a6fc077c-5245-4510-9606-756e1a7d4f41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638676700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_intr_rd.638676700
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4230786106
Short name T992
Test name
Test status
Simulation time 11322380900 ps
CPU time 157.8 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:12:04 PM PDT 24
Peak memory 293572 kb
Host smart-a86e4e3a-01ca-4e60-a13a-0376b86b23e0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230786106 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.4230786106
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1943430445
Short name T715
Test name
Test status
Simulation time 3363235400 ps
CPU time 64.59 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:10:31 PM PDT 24
Peak memory 260716 kb
Host smart-15f9fdae-581d-4901-b668-99349671ff50
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943430445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
943430445
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2932823191
Short name T100
Test name
Test status
Simulation time 49461700 ps
CPU time 13.29 seconds
Started Jun 11 03:09:34 PM PDT 24
Finished Jun 11 03:09:48 PM PDT 24
Peak memory 260272 kb
Host smart-84cb8cc7-ee3f-40e1-9bcb-191a74f12a9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932823191 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2932823191
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1462502770
Short name T828
Test name
Test status
Simulation time 4191036700 ps
CPU time 343.13 seconds
Started Jun 11 03:09:24 PM PDT 24
Finished Jun 11 03:15:09 PM PDT 24
Peak memory 274264 kb
Host smart-738d41a0-9385-4001-9f75-6a6fc0ecda74
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462502770 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1462502770
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.1117429105
Short name T127
Test name
Test status
Simulation time 39542200 ps
CPU time 109.09 seconds
Started Jun 11 03:09:24 PM PDT 24
Finished Jun 11 03:11:14 PM PDT 24
Peak memory 260300 kb
Host smart-94fdac9e-7f34-4df3-849e-fa4ae6b3f8a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117429105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.1117429105
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3905915864
Short name T859
Test name
Test status
Simulation time 40910843700 ps
CPU time 636.17 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:19:53 PM PDT 24
Peak memory 263416 kb
Host smart-a57d1688-ec12-4d4c-b766-7972d15310b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905915864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3905915864
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1710709482
Short name T411
Test name
Test status
Simulation time 58269400 ps
CPU time 13.27 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:09:39 PM PDT 24
Peak memory 259088 kb
Host smart-4f519281-ce2e-490e-be6a-e757d83fb97a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710709482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1710709482
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.2927947031
Short name T665
Test name
Test status
Simulation time 42702400 ps
CPU time 52.93 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:10:10 PM PDT 24
Peak memory 271408 kb
Host smart-17d412cc-9da8-4b16-90fa-647a649027a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927947031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2927947031
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3342955297
Short name T453
Test name
Test status
Simulation time 247306700 ps
CPU time 36.79 seconds
Started Jun 11 03:09:36 PM PDT 24
Finished Jun 11 03:10:14 PM PDT 24
Peak memory 277068 kb
Host smart-073c3b4e-f66c-44bf-95e0-95908b4e2e8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342955297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3342955297
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.4143062019
Short name T250
Test name
Test status
Simulation time 702854200 ps
CPU time 134.31 seconds
Started Jun 11 03:09:24 PM PDT 24
Finished Jun 11 03:11:39 PM PDT 24
Peak memory 297648 kb
Host smart-95b90688-ad66-4689-a407-8b488c1371b5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143062019 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.4143062019
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.378645220
Short name T59
Test name
Test status
Simulation time 12665181300 ps
CPU time 555.52 seconds
Started Jun 11 03:09:25 PM PDT 24
Finished Jun 11 03:18:42 PM PDT 24
Peak memory 310220 kb
Host smart-fbeca568-5281-4e08-82d3-334e84e07704
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378645220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.flash_ctrl_rw.378645220
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1081637202
Short name T165
Test name
Test status
Simulation time 59955900 ps
CPU time 30.7 seconds
Started Jun 11 03:09:36 PM PDT 24
Finished Jun 11 03:10:07 PM PDT 24
Peak memory 277460 kb
Host smart-2645eabd-b48d-4c5b-9a2f-23e0f12610c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081637202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1081637202
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3201162008
Short name T862
Test name
Test status
Simulation time 43270800 ps
CPU time 31.05 seconds
Started Jun 11 03:09:36 PM PDT 24
Finished Jun 11 03:10:08 PM PDT 24
Peak memory 267792 kb
Host smart-0a29e4fc-361f-45f6-a297-f567faf691b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201162008 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3201162008
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3843476961
Short name T866
Test name
Test status
Simulation time 23808622500 ps
CPU time 92.52 seconds
Started Jun 11 03:09:34 PM PDT 24
Finished Jun 11 03:11:08 PM PDT 24
Peak memory 265548 kb
Host smart-1199ea64-5269-48dd-9213-02bba37f0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843476961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3843476961
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.467218995
Short name T870
Test name
Test status
Simulation time 80973200 ps
CPU time 212.85 seconds
Started Jun 11 03:09:16 PM PDT 24
Finished Jun 11 03:12:50 PM PDT 24
Peak memory 279348 kb
Host smart-132a4cd9-3bf5-4076-b656-3991c9b0a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467218995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.467218995
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3425216625
Short name T538
Test name
Test status
Simulation time 8191307800 ps
CPU time 155.48 seconds
Started Jun 11 03:09:24 PM PDT 24
Finished Jun 11 03:12:00 PM PDT 24
Peak memory 265636 kb
Host smart-37167776-eba9-4f97-b046-6ffebe4e6c02
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425216625 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3425216625
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1610134406
Short name T210
Test name
Test status
Simulation time 166322200 ps
CPU time 13.74 seconds
Started Jun 11 03:10:04 PM PDT 24
Finished Jun 11 03:10:19 PM PDT 24
Peak memory 265552 kb
Host smart-e1b28474-5c09-41ae-9893-7dab75369a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610134406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1610134406
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1764203224
Short name T433
Test name
Test status
Simulation time 49151800 ps
CPU time 13.32 seconds
Started Jun 11 03:09:54 PM PDT 24
Finished Jun 11 03:10:09 PM PDT 24
Peak memory 275064 kb
Host smart-866299fa-d10b-4498-94cc-ab9acba4678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764203224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1764203224
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.75082517
Short name T601
Test name
Test status
Simulation time 38051900 ps
CPU time 21.88 seconds
Started Jun 11 03:09:52 PM PDT 24
Finished Jun 11 03:10:15 PM PDT 24
Peak memory 265784 kb
Host smart-f89f9dff-a6f6-4f5a-95fd-f2e26c0919c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75082517 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_disable.75082517
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.132343782
Short name T719
Test name
Test status
Simulation time 93914000 ps
CPU time 13.4 seconds
Started Jun 11 03:09:54 PM PDT 24
Finished Jun 11 03:10:09 PM PDT 24
Peak memory 265108 kb
Host smart-fd96d5db-5506-43d4-80e1-5f8f551f0e43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132343782 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.132343782
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2382847807
Short name T679
Test name
Test status
Simulation time 40127005300 ps
CPU time 836.71 seconds
Started Jun 11 03:09:46 PM PDT 24
Finished Jun 11 03:23:45 PM PDT 24
Peak memory 264724 kb
Host smart-61e3333d-b654-4975-a885-aeb8e127ee95
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382847807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2382847807
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1450731426
Short name T446
Test name
Test status
Simulation time 3584891400 ps
CPU time 143.34 seconds
Started Jun 11 03:09:45 PM PDT 24
Finished Jun 11 03:12:11 PM PDT 24
Peak memory 263444 kb
Host smart-739d8d6f-3581-4b85-832e-a9471f84fbca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450731426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1450731426
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.3082276715
Short name T343
Test name
Test status
Simulation time 3521260300 ps
CPU time 241.11 seconds
Started Jun 11 03:09:44 PM PDT 24
Finished Jun 11 03:13:47 PM PDT 24
Peak memory 285160 kb
Host smart-5a6e3afb-5f03-4b55-ac47-415d774be8f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082276715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.3082276715
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.1280071786
Short name T703
Test name
Test status
Simulation time 6105644000 ps
CPU time 162.72 seconds
Started Jun 11 03:09:53 PM PDT 24
Finished Jun 11 03:12:37 PM PDT 24
Peak memory 294308 kb
Host smart-13365ed1-7b4d-433b-b3ce-6656c12f15c2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280071786 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.1280071786
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.136758815
Short name T774
Test name
Test status
Simulation time 62199600 ps
CPU time 13.51 seconds
Started Jun 11 03:09:53 PM PDT 24
Finished Jun 11 03:10:08 PM PDT 24
Peak memory 265176 kb
Host smart-a996a8e4-c9cb-4841-bf9f-c85d5bff7455
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136758815 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.136758815
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1599984378
Short name T1050
Test name
Test status
Simulation time 8766039600 ps
CPU time 215.38 seconds
Started Jun 11 03:09:44 PM PDT 24
Finished Jun 11 03:13:22 PM PDT 24
Peak memory 265464 kb
Host smart-c5471e29-f969-4b16-9860-dd95a932f97a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599984378 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1599984378
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2342241073
Short name T528
Test name
Test status
Simulation time 36072500 ps
CPU time 130.03 seconds
Started Jun 11 03:09:44 PM PDT 24
Finished Jun 11 03:11:56 PM PDT 24
Peak memory 265500 kb
Host smart-565a9eb9-7b8f-405e-9e6c-cef3f2eb399c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342241073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2342241073
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.448302314
Short name T873
Test name
Test status
Simulation time 1998983300 ps
CPU time 423.04 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:16:48 PM PDT 24
Peak memory 263436 kb
Host smart-18532906-e607-437a-b076-6ea7d6599a92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448302314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.448302314
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.470302053
Short name T412
Test name
Test status
Simulation time 129670600 ps
CPU time 18.17 seconds
Started Jun 11 03:09:54 PM PDT 24
Finished Jun 11 03:10:14 PM PDT 24
Peak memory 265572 kb
Host smart-2cc0153c-d7ea-4032-978c-264026ae766a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470302053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.470302053
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3945495397
Short name T574
Test name
Test status
Simulation time 126186800 ps
CPU time 949.6 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:25:35 PM PDT 24
Peak memory 285476 kb
Host smart-2ba08f95-8eb8-4587-b376-ca74dcbd4642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945495397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3945495397
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1067964489
Short name T979
Test name
Test status
Simulation time 237230000 ps
CPU time 33.12 seconds
Started Jun 11 03:09:54 PM PDT 24
Finished Jun 11 03:10:28 PM PDT 24
Peak memory 270680 kb
Host smart-6830000b-f0a2-4ecb-804e-bac1e0093026
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067964489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1067964489
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.697983904
Short name T242
Test name
Test status
Simulation time 1731394600 ps
CPU time 114.49 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:11:39 PM PDT 24
Peak memory 290436 kb
Host smart-2f6f4b66-8e81-4e37-8790-31440d64d73a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697983904 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.flash_ctrl_ro.697983904
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1853366014
Short name T174
Test name
Test status
Simulation time 4113727600 ps
CPU time 586.33 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:19:32 PM PDT 24
Peak memory 309996 kb
Host smart-ce1d5f1a-9734-400b-aea3-5ecf49247675
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853366014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.1853366014
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.4016197726
Short name T531
Test name
Test status
Simulation time 28752000 ps
CPU time 30.79 seconds
Started Jun 11 03:09:54 PM PDT 24
Finished Jun 11 03:10:26 PM PDT 24
Peak memory 277660 kb
Host smart-395d73eb-621c-4722-be5b-ef1e59a1bbd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016197726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.4016197726
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3600129523
Short name T829
Test name
Test status
Simulation time 4218234900 ps
CPU time 78.53 seconds
Started Jun 11 03:09:53 PM PDT 24
Finished Jun 11 03:11:12 PM PDT 24
Peak memory 265532 kb
Host smart-7cee707d-f7df-40d0-abb2-ba0af31d64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600129523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3600129523
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.543879482
Short name T501
Test name
Test status
Simulation time 3525360400 ps
CPU time 135.48 seconds
Started Jun 11 03:09:43 PM PDT 24
Finished Jun 11 03:12:00 PM PDT 24
Peak memory 272404 kb
Host smart-827b35ab-4bab-4a76-ba5b-43bbfbdadf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543879482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.543879482
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.782460662
Short name T890
Test name
Test status
Simulation time 12346104100 ps
CPU time 166 seconds
Started Jun 11 03:09:46 PM PDT 24
Finished Jun 11 03:12:34 PM PDT 24
Peak memory 265672 kb
Host smart-d5edfbaf-ade4-4ec9-b078-325abaab378b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782460662 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.782460662
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2313916413
Short name T786
Test name
Test status
Simulation time 53493700 ps
CPU time 13.67 seconds
Started Jun 11 03:10:23 PM PDT 24
Finished Jun 11 03:10:38 PM PDT 24
Peak memory 265696 kb
Host smart-959ccdbe-7252-490d-9209-3c214d1797e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313916413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2313916413
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.3486405020
Short name T709
Test name
Test status
Simulation time 13480500 ps
CPU time 15.85 seconds
Started Jun 11 03:10:11 PM PDT 24
Finished Jun 11 03:10:27 PM PDT 24
Peak memory 284592 kb
Host smart-76378aeb-d47e-48ba-87ac-6e1da80bcbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486405020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3486405020
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.3939432975
Short name T1006
Test name
Test status
Simulation time 10710400 ps
CPU time 21.77 seconds
Started Jun 11 03:10:12 PM PDT 24
Finished Jun 11 03:10:35 PM PDT 24
Peak memory 265872 kb
Host smart-e974a080-cff1-4ffe-ab64-8bb9f999ad4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939432975 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.3939432975
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1047951186
Short name T126
Test name
Test status
Simulation time 10011752200 ps
CPU time 122.4 seconds
Started Jun 11 03:10:22 PM PDT 24
Finished Jun 11 03:12:26 PM PDT 24
Peak memory 313548 kb
Host smart-e1d236ef-bf67-47d8-8612-28a46f5550e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047951186 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1047951186
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.1027140271
Short name T705
Test name
Test status
Simulation time 15781900 ps
CPU time 13.17 seconds
Started Jun 11 03:10:22 PM PDT 24
Finished Jun 11 03:10:37 PM PDT 24
Peak memory 259812 kb
Host smart-c7811e35-45bc-4647-b661-c949b801bd77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027140271 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.1027140271
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1332382497
Short name T510
Test name
Test status
Simulation time 150159524400 ps
CPU time 922.57 seconds
Started Jun 11 03:10:03 PM PDT 24
Finished Jun 11 03:25:27 PM PDT 24
Peak memory 264492 kb
Host smart-dc7212de-d7db-4357-8148-ec21424592d1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332382497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1332382497
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.374422027
Short name T318
Test name
Test status
Simulation time 2654101100 ps
CPU time 59.72 seconds
Started Jun 11 03:10:03 PM PDT 24
Finished Jun 11 03:11:04 PM PDT 24
Peak memory 263448 kb
Host smart-53bf8794-41d2-4b90-b7a0-7fe913433542
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374422027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_h
w_sec_otp.374422027
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3345237346
Short name T903
Test name
Test status
Simulation time 1111581700 ps
CPU time 151.81 seconds
Started Jun 11 03:10:15 PM PDT 24
Finished Jun 11 03:12:47 PM PDT 24
Peak memory 285464 kb
Host smart-9ef83546-2012-4152-8a48-e2fc759e3bfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345237346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3345237346
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2810946051
Short name T936
Test name
Test status
Simulation time 12013163200 ps
CPU time 314.38 seconds
Started Jun 11 03:10:11 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 291324 kb
Host smart-08632dcf-b988-4148-806b-74d4a50bbf0f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810946051 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2810946051
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.4205614217
Short name T209
Test name
Test status
Simulation time 4023779400 ps
CPU time 69.81 seconds
Started Jun 11 03:10:12 PM PDT 24
Finished Jun 11 03:11:23 PM PDT 24
Peak memory 260740 kb
Host smart-44f419dc-4c8e-424a-83d0-374c0bd4fc50
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205614217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.4
205614217
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1166198668
Short name T294
Test name
Test status
Simulation time 46188400 ps
CPU time 13.52 seconds
Started Jun 11 03:10:23 PM PDT 24
Finished Jun 11 03:10:38 PM PDT 24
Peak memory 260196 kb
Host smart-d8494f5c-18e2-40dd-a95c-f892c717f9fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166198668 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1166198668
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.2481222112
Short name T769
Test name
Test status
Simulation time 12168703100 ps
CPU time 171.76 seconds
Started Jun 11 03:10:05 PM PDT 24
Finished Jun 11 03:12:58 PM PDT 24
Peak memory 265528 kb
Host smart-deb20032-732c-4650-86d6-b24b179469c9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481222112 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.2481222112
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.3486292987
Short name T1047
Test name
Test status
Simulation time 64484500 ps
CPU time 131.77 seconds
Started Jun 11 03:10:03 PM PDT 24
Finished Jun 11 03:12:16 PM PDT 24
Peak memory 260148 kb
Host smart-b869a0f1-6971-4a80-b9b0-2b2cb38b74e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486292987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.3486292987
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.497730449
Short name T224
Test name
Test status
Simulation time 94017000 ps
CPU time 194.51 seconds
Started Jun 11 03:10:03 PM PDT 24
Finished Jun 11 03:13:18 PM PDT 24
Peak memory 263364 kb
Host smart-6aceb964-75ec-4df7-86b5-6a53d193278e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=497730449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.497730449
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3701919986
Short name T788
Test name
Test status
Simulation time 4328354100 ps
CPU time 187.52 seconds
Started Jun 11 03:10:13 PM PDT 24
Finished Jun 11 03:13:22 PM PDT 24
Peak memory 265460 kb
Host smart-a49aeb7b-8475-445f-8761-25feda2c65fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701919986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.3701919986
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2827270903
Short name T771
Test name
Test status
Simulation time 299772500 ps
CPU time 390.13 seconds
Started Jun 11 03:10:03 PM PDT 24
Finished Jun 11 03:16:35 PM PDT 24
Peak memory 279012 kb
Host smart-952ca862-e460-475d-9f2c-b289bf352bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827270903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2827270903
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.575448459
Short name T929
Test name
Test status
Simulation time 115744100 ps
CPU time 37.78 seconds
Started Jun 11 03:10:12 PM PDT 24
Finished Jun 11 03:10:51 PM PDT 24
Peak memory 277076 kb
Host smart-a0be1dc3-7840-417a-878f-98ee592f1901
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575448459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.575448459
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1944601885
Short name T177
Test name
Test status
Simulation time 1836854500 ps
CPU time 117.85 seconds
Started Jun 11 03:10:13 PM PDT 24
Finished Jun 11 03:12:12 PM PDT 24
Peak memory 282108 kb
Host smart-0fe18122-4e07-49eb-904c-c08e31791d90
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944601885 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.1944601885
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2401253679
Short name T1083
Test name
Test status
Simulation time 9660456500 ps
CPU time 701.4 seconds
Started Jun 11 03:10:13 PM PDT 24
Finished Jun 11 03:21:56 PM PDT 24
Peak memory 314800 kb
Host smart-5a285c15-995e-4472-988a-b5bff75242e9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401253679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2401253679
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2101294351
Short name T330
Test name
Test status
Simulation time 37615200 ps
CPU time 29.25 seconds
Started Jun 11 03:10:11 PM PDT 24
Finished Jun 11 03:10:42 PM PDT 24
Peak memory 277212 kb
Host smart-a90dde8c-2e3b-4aba-8272-60966e9268a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101294351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2101294351
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1268529833
Short name T751
Test name
Test status
Simulation time 1631240900 ps
CPU time 72.08 seconds
Started Jun 11 03:10:15 PM PDT 24
Finished Jun 11 03:11:28 PM PDT 24
Peak memory 265520 kb
Host smart-95fb5063-0a91-48ce-8123-9bb48cf9d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268529833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1268529833
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3457777747
Short name T1067
Test name
Test status
Simulation time 23287100 ps
CPU time 76.11 seconds
Started Jun 11 03:10:04 PM PDT 24
Finished Jun 11 03:11:21 PM PDT 24
Peak memory 275644 kb
Host smart-b23b7128-fab8-4f88-84bb-110fcf8620d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457777747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3457777747
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.560585391
Short name T885
Test name
Test status
Simulation time 8070744600 ps
CPU time 161.8 seconds
Started Jun 11 03:10:12 PM PDT 24
Finished Jun 11 03:12:55 PM PDT 24
Peak memory 260680 kb
Host smart-37baaad7-f70d-47bb-aa04-233532afdcc6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560585391 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.flash_ctrl_wo.560585391
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.2182547666
Short name T924
Test name
Test status
Simulation time 38853900 ps
CPU time 13.7 seconds
Started Jun 11 03:10:48 PM PDT 24
Finished Jun 11 03:11:03 PM PDT 24
Peak memory 258584 kb
Host smart-bec145e9-209e-420a-971d-6d5d5993c690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182547666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
2182547666
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2729471061
Short name T761
Test name
Test status
Simulation time 236492500 ps
CPU time 13.71 seconds
Started Jun 11 03:10:33 PM PDT 24
Finished Jun 11 03:10:48 PM PDT 24
Peak memory 284508 kb
Host smart-6e5b2917-bbc3-4232-b58c-8c86714a75b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729471061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2729471061
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1950855744
Short name T1025
Test name
Test status
Simulation time 28402800 ps
CPU time 21.69 seconds
Started Jun 11 03:10:33 PM PDT 24
Finished Jun 11 03:10:56 PM PDT 24
Peak memory 274064 kb
Host smart-c3700f30-a964-4487-b823-408233c65cda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950855744 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1950855744
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.4274413886
Short name T826
Test name
Test status
Simulation time 26807400 ps
CPU time 13.69 seconds
Started Jun 11 03:10:48 PM PDT 24
Finished Jun 11 03:11:03 PM PDT 24
Peak memory 265736 kb
Host smart-71358ec0-d63f-4495-b3a2-d05bebe0fddd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274413886 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.4274413886
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2423683782
Short name T660
Test name
Test status
Simulation time 80140808100 ps
CPU time 843.77 seconds
Started Jun 11 03:10:22 PM PDT 24
Finished Jun 11 03:24:28 PM PDT 24
Peak memory 264408 kb
Host smart-602510c6-ad68-4d0e-af07-7e7cee2d9ba2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423683782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2423683782
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3298554787
Short name T479
Test name
Test status
Simulation time 11912074500 ps
CPU time 217.26 seconds
Started Jun 11 03:10:23 PM PDT 24
Finished Jun 11 03:14:01 PM PDT 24
Peak memory 263476 kb
Host smart-ca4991a8-dba0-40d9-9f0c-299fcf569f35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298554787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3298554787
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3865437385
Short name T810
Test name
Test status
Simulation time 34047654100 ps
CPU time 303.99 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:15:40 PM PDT 24
Peak memory 292700 kb
Host smart-16ad26b2-97e4-465f-b230-a933d8fabb0f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865437385 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3865437385
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.2904338903
Short name T103
Test name
Test status
Simulation time 1625258700 ps
CPU time 73.12 seconds
Started Jun 11 03:10:36 PM PDT 24
Finished Jun 11 03:11:51 PM PDT 24
Peak memory 260764 kb
Host smart-4b21da19-8d81-4c0e-bdf6-aecb7ca6d7ba
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904338903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2
904338903
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.4135131802
Short name T621
Test name
Test status
Simulation time 15488500 ps
CPU time 13.49 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:10:50 PM PDT 24
Peak memory 260100 kb
Host smart-46b94d88-e2f7-4010-9171-872c9f3a1af8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135131802 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.4135131802
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2422930778
Short name T800
Test name
Test status
Simulation time 55785924800 ps
CPU time 832.23 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:24:29 PM PDT 24
Peak memory 274776 kb
Host smart-32ba26c7-ba87-426d-bae2-e3bc2011098c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422930778 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2422930778
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3388538594
Short name T927
Test name
Test status
Simulation time 73846400 ps
CPU time 133.07 seconds
Started Jun 11 03:10:23 PM PDT 24
Finished Jun 11 03:12:37 PM PDT 24
Peak memory 265404 kb
Host smart-b5517995-3821-4f0a-a80c-e0c8c173d1e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388538594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3388538594
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1272513969
Short name T544
Test name
Test status
Simulation time 132516000 ps
CPU time 113.7 seconds
Started Jun 11 03:10:23 PM PDT 24
Finished Jun 11 03:12:18 PM PDT 24
Peak memory 263340 kb
Host smart-420bdbed-c3d9-4772-a972-ec9964163954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272513969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1272513969
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1987376527
Short name T516
Test name
Test status
Simulation time 9715609100 ps
CPU time 156.17 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:13:12 PM PDT 24
Peak memory 265676 kb
Host smart-a30709d4-afa9-4472-908c-4b816bb1dd9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987376527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1987376527
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.408920178
Short name T111
Test name
Test status
Simulation time 82508300 ps
CPU time 471.36 seconds
Started Jun 11 03:10:24 PM PDT 24
Finished Jun 11 03:18:16 PM PDT 24
Peak memory 284476 kb
Host smart-80279223-2a64-4b22-946b-9d21a902cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408920178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.408920178
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2962528506
Short name T407
Test name
Test status
Simulation time 94351900 ps
CPU time 37.87 seconds
Started Jun 11 03:10:35 PM PDT 24
Finished Jun 11 03:11:16 PM PDT 24
Peak memory 277288 kb
Host smart-1a1fbc67-c578-447a-a9b8-724d6a05ae69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962528506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2962528506
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3649659394
Short name T753
Test name
Test status
Simulation time 2722558900 ps
CPU time 117.17 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:12:34 PM PDT 24
Peak memory 290408 kb
Host smart-46d6bbfd-59be-4c77-8e80-a58cadfa02b0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649659394 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.3649659394
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.450222075
Short name T536
Test name
Test status
Simulation time 4034433800 ps
CPU time 553.3 seconds
Started Jun 11 03:10:35 PM PDT 24
Finished Jun 11 03:19:51 PM PDT 24
Peak memory 314620 kb
Host smart-f1b93e5a-5b56-4718-bd84-f4632c15af2c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450222075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_rw.450222075
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.1610401125
Short name T926
Test name
Test status
Simulation time 43790900 ps
CPU time 31.39 seconds
Started Jun 11 03:10:34 PM PDT 24
Finished Jun 11 03:11:07 PM PDT 24
Peak memory 276084 kb
Host smart-e1b09c09-4b4b-4525-af11-08d7d5a7f166
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610401125 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.1610401125
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.734818176
Short name T902
Test name
Test status
Simulation time 2134336200 ps
CPU time 78.23 seconds
Started Jun 11 03:10:33 PM PDT 24
Finished Jun 11 03:11:53 PM PDT 24
Peak memory 263892 kb
Host smart-caa28dd4-62c5-48df-a45b-151e8748e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734818176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.734818176
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1319582371
Short name T677
Test name
Test status
Simulation time 41388700 ps
CPU time 167.57 seconds
Started Jun 11 03:10:22 PM PDT 24
Finished Jun 11 03:13:12 PM PDT 24
Peak memory 277484 kb
Host smart-c842af03-f271-4f95-9b1c-32d7e483e9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319582371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1319582371
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.1139244857
Short name T462
Test name
Test status
Simulation time 2055364600 ps
CPU time 177.34 seconds
Started Jun 11 03:10:36 PM PDT 24
Finished Jun 11 03:13:35 PM PDT 24
Peak memory 265740 kb
Host smart-87ba7fcf-1ec7-4d55-9b39-66b8ce0c5376
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139244857 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.1139244857
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.178140631
Short name T427
Test name
Test status
Simulation time 192920200 ps
CPU time 13.93 seconds
Started Jun 11 03:11:00 PM PDT 24
Finished Jun 11 03:11:14 PM PDT 24
Peak memory 265452 kb
Host smart-759f9245-9d95-48b5-bffe-ca9f6caa6ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178140631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.178140631
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.1040835123
Short name T919
Test name
Test status
Simulation time 29893400 ps
CPU time 15.87 seconds
Started Jun 11 03:11:00 PM PDT 24
Finished Jun 11 03:11:17 PM PDT 24
Peak memory 274980 kb
Host smart-f3813f3c-a838-4e98-a327-88550b7279dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040835123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1040835123
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.4160499865
Short name T138
Test name
Test status
Simulation time 23475900 ps
CPU time 21.98 seconds
Started Jun 11 03:10:59 PM PDT 24
Finished Jun 11 03:11:22 PM PDT 24
Peak memory 265752 kb
Host smart-e6a529cb-2185-4a50-a509-0e06ecd533b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160499865 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.4160499865
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.233524369
Short name T523
Test name
Test status
Simulation time 10012721100 ps
CPU time 330.66 seconds
Started Jun 11 03:10:56 PM PDT 24
Finished Jun 11 03:16:28 PM PDT 24
Peak memory 317360 kb
Host smart-184fbbcd-ab96-477d-95ba-08be6c4c2af5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233524369 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.233524369
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3194668107
Short name T984
Test name
Test status
Simulation time 47917700 ps
CPU time 13.54 seconds
Started Jun 11 03:10:58 PM PDT 24
Finished Jun 11 03:11:13 PM PDT 24
Peak memory 258800 kb
Host smart-2dcad8cf-a161-4a34-b9bd-fb6f52c69860
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194668107 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3194668107
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2496442491
Short name T310
Test name
Test status
Simulation time 6363272800 ps
CPU time 91.67 seconds
Started Jun 11 03:10:44 PM PDT 24
Finished Jun 11 03:12:17 PM PDT 24
Peak memory 263428 kb
Host smart-5be4bcd1-3cb1-4579-b0dc-efa57f4c3d70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496442491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2496442491
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1843015531
Short name T619
Test name
Test status
Simulation time 5798495700 ps
CPU time 120.61 seconds
Started Jun 11 03:10:58 PM PDT 24
Finished Jun 11 03:13:00 PM PDT 24
Peak memory 292868 kb
Host smart-f48ede5f-0684-43d3-a78d-75668d87079d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843015531 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1843015531
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.3103772305
Short name T780
Test name
Test status
Simulation time 3304729600 ps
CPU time 62.33 seconds
Started Jun 11 03:10:46 PM PDT 24
Finished Jun 11 03:11:50 PM PDT 24
Peak memory 263756 kb
Host smart-1f4458e4-5121-46d7-9a1e-31b5a70d7932
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103772305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3
103772305
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.336251565
Short name T511
Test name
Test status
Simulation time 59247900 ps
CPU time 13.53 seconds
Started Jun 11 03:11:00 PM PDT 24
Finished Jun 11 03:11:15 PM PDT 24
Peak memory 265280 kb
Host smart-cbca44f8-599a-4567-9715-dae454b29fcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336251565 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.336251565
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.850762361
Short name T1017
Test name
Test status
Simulation time 16979532800 ps
CPU time 280.37 seconds
Started Jun 11 03:10:47 PM PDT 24
Finished Jun 11 03:15:28 PM PDT 24
Peak memory 274840 kb
Host smart-871ed1ea-0cf0-4c23-9a57-970e2538bc33
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850762361 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.850762361
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1617304715
Short name T1001
Test name
Test status
Simulation time 36865000 ps
CPU time 109.41 seconds
Started Jun 11 03:10:48 PM PDT 24
Finished Jun 11 03:12:39 PM PDT 24
Peak memory 260428 kb
Host smart-6f51b1b9-bdf8-44dd-bf40-8c9d1edd275d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617304715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1617304715
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.3742180070
Short name T982
Test name
Test status
Simulation time 3406287000 ps
CPU time 586.59 seconds
Started Jun 11 03:10:47 PM PDT 24
Finished Jun 11 03:20:35 PM PDT 24
Peak memory 263560 kb
Host smart-8006092e-dde7-4d87-ae23-820cd4c6ba47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742180070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3742180070
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.3726773044
Short name T651
Test name
Test status
Simulation time 61653700 ps
CPU time 13.76 seconds
Started Jun 11 03:10:57 PM PDT 24
Finished Jun 11 03:11:12 PM PDT 24
Peak memory 265544 kb
Host smart-50b6253a-5b33-4d2f-91bc-34de6a1cd886
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726773044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.3726773044
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.411520149
Short name T85
Test name
Test status
Simulation time 1782239600 ps
CPU time 256.82 seconds
Started Jun 11 03:10:47 PM PDT 24
Finished Jun 11 03:15:05 PM PDT 24
Peak memory 281700 kb
Host smart-afa737bc-7c69-4b01-9cb3-4ee4503a89ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411520149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.411520149
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2779319931
Short name T977
Test name
Test status
Simulation time 80873700 ps
CPU time 35.02 seconds
Started Jun 11 03:10:58 PM PDT 24
Finished Jun 11 03:11:33 PM PDT 24
Peak memory 275736 kb
Host smart-afc87bf8-83dc-435b-a375-db385208330f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779319931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2779319931
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.3651389680
Short name T1088
Test name
Test status
Simulation time 1795449700 ps
CPU time 101.97 seconds
Started Jun 11 03:10:56 PM PDT 24
Finished Jun 11 03:12:39 PM PDT 24
Peak memory 291348 kb
Host smart-c7eaa68c-ad3b-4e73-8e82-c81d593d4d38
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651389680 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.3651389680
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2634781237
Short name T735
Test name
Test status
Simulation time 2998502600 ps
CPU time 622.91 seconds
Started Jun 11 03:10:58 PM PDT 24
Finished Jun 11 03:21:22 PM PDT 24
Peak memory 309836 kb
Host smart-8d81c8df-ec0d-4766-87df-f26ebb6e92e4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634781237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.2634781237
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3680075792
Short name T797
Test name
Test status
Simulation time 39503000 ps
CPU time 31.55 seconds
Started Jun 11 03:10:57 PM PDT 24
Finished Jun 11 03:11:30 PM PDT 24
Peak memory 277140 kb
Host smart-79d7338a-5f2f-44c7-be02-18e4b2086a76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680075792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3680075792
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2784321818
Short name T332
Test name
Test status
Simulation time 28979000 ps
CPU time 30.92 seconds
Started Jun 11 03:10:59 PM PDT 24
Finished Jun 11 03:11:30 PM PDT 24
Peak memory 267884 kb
Host smart-7a3ce659-3564-4836-bdb6-4d46fc41263c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784321818 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2784321818
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1382492611
Short name T512
Test name
Test status
Simulation time 7640397600 ps
CPU time 72.22 seconds
Started Jun 11 03:10:57 PM PDT 24
Finished Jun 11 03:12:10 PM PDT 24
Peak memory 259884 kb
Host smart-6090b151-fb95-4a2e-8951-679baf185aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382492611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1382492611
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.3450321555
Short name T476
Test name
Test status
Simulation time 29323600 ps
CPU time 95.68 seconds
Started Jun 11 03:10:46 PM PDT 24
Finished Jun 11 03:12:23 PM PDT 24
Peak memory 276440 kb
Host smart-ca04edcc-30ee-45ee-ab3e-688e06844480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450321555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3450321555
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.3438576391
Short name T55
Test name
Test status
Simulation time 11301781200 ps
CPU time 182.36 seconds
Started Jun 11 03:10:57 PM PDT 24
Finished Jun 11 03:14:00 PM PDT 24
Peak memory 265620 kb
Host smart-c0130fe9-b53b-4f56-af77-8a4b6724f3d5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438576391 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.3438576391
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2643053311
Short name T515
Test name
Test status
Simulation time 92451100 ps
CPU time 13.97 seconds
Started Jun 11 03:11:24 PM PDT 24
Finished Jun 11 03:11:39 PM PDT 24
Peak memory 258556 kb
Host smart-06ad613b-a0c6-4668-a6d8-a75d88e9ae3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643053311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2643053311
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.103914192
Short name T880
Test name
Test status
Simulation time 48705400 ps
CPU time 15.66 seconds
Started Jun 11 03:11:17 PM PDT 24
Finished Jun 11 03:11:33 PM PDT 24
Peak memory 284592 kb
Host smart-633352e1-142c-415d-8b75-a2da10ed239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103914192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.103914192
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.2712179610
Short name T381
Test name
Test status
Simulation time 62689000 ps
CPU time 20.57 seconds
Started Jun 11 03:11:16 PM PDT 24
Finished Jun 11 03:11:37 PM PDT 24
Peak memory 274060 kb
Host smart-a306084c-bcdd-469d-a3cb-be140f691559
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712179610 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.2712179610
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2296269123
Short name T125
Test name
Test status
Simulation time 10019690000 ps
CPU time 90.92 seconds
Started Jun 11 03:11:27 PM PDT 24
Finished Jun 11 03:12:59 PM PDT 24
Peak memory 329360 kb
Host smart-09520f90-9b38-4e8e-9488-9674d05329e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296269123 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2296269123
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3264187600
Short name T158
Test name
Test status
Simulation time 79390300 ps
CPU time 13.78 seconds
Started Jun 11 03:11:15 PM PDT 24
Finished Jun 11 03:11:30 PM PDT 24
Peak memory 265148 kb
Host smart-2887d069-8003-4304-b57d-123c1e59e406
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264187600 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3264187600
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.586342011
Short name T143
Test name
Test status
Simulation time 100147939600 ps
CPU time 796.91 seconds
Started Jun 11 03:11:06 PM PDT 24
Finished Jun 11 03:24:24 PM PDT 24
Peak memory 263972 kb
Host smart-767f37e0-70ed-494a-b27b-e946abf286b4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586342011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.flash_ctrl_hw_rma_reset.586342011
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.223819501
Short name T610
Test name
Test status
Simulation time 2726805400 ps
CPU time 94.26 seconds
Started Jun 11 03:11:10 PM PDT 24
Finished Jun 11 03:12:45 PM PDT 24
Peak memory 263484 kb
Host smart-774462b5-5ed2-48b7-848e-6cae12bd830c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223819501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.223819501
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.851251841
Short name T341
Test name
Test status
Simulation time 1537297500 ps
CPU time 262.88 seconds
Started Jun 11 03:11:08 PM PDT 24
Finished Jun 11 03:15:32 PM PDT 24
Peak memory 285176 kb
Host smart-afbfc903-e04a-438b-a008-543457f56ff0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851251841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.851251841
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2547673391
Short name T349
Test name
Test status
Simulation time 13014397400 ps
CPU time 279.45 seconds
Started Jun 11 03:11:05 PM PDT 24
Finished Jun 11 03:15:46 PM PDT 24
Peak memory 291360 kb
Host smart-dad6a7e8-4857-4a68-ab6c-632f8fadf665
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547673391 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.2547673391
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.223294384
Short name T678
Test name
Test status
Simulation time 2041083600 ps
CPU time 96.07 seconds
Started Jun 11 03:11:07 PM PDT 24
Finished Jun 11 03:12:44 PM PDT 24
Peak memory 260664 kb
Host smart-86072023-ad91-4b67-9175-d34c6f080346
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223294384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.223294384
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.1568323973
Short name T897
Test name
Test status
Simulation time 16094014700 ps
CPU time 571.85 seconds
Started Jun 11 03:11:06 PM PDT 24
Finished Jun 11 03:20:39 PM PDT 24
Peak memory 275736 kb
Host smart-a5721a2f-e2d7-40f9-8372-52f392c527ae
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568323973 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.1568323973
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.29071600
Short name T133
Test name
Test status
Simulation time 73980400 ps
CPU time 135.03 seconds
Started Jun 11 03:11:07 PM PDT 24
Finished Jun 11 03:13:23 PM PDT 24
Peak memory 265700 kb
Host smart-e61b6461-e37d-43b1-814e-16a445dbdba6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29071600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp
_reset.29071600
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.3423296703
Short name T816
Test name
Test status
Simulation time 83347800 ps
CPU time 65.17 seconds
Started Jun 11 03:11:00 PM PDT 24
Finished Jun 11 03:12:06 PM PDT 24
Peak memory 263420 kb
Host smart-cfe0a8b3-cab5-4635-bf4b-37866a7c0df8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423296703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3423296703
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.49949216
Short name T1054
Test name
Test status
Simulation time 22507500 ps
CPU time 13.47 seconds
Started Jun 11 03:11:17 PM PDT 24
Finished Jun 11 03:11:31 PM PDT 24
Peak memory 259032 kb
Host smart-48d0b9d0-6d83-4f1c-ae44-a8ae14a623dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49949216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_rese
t.49949216
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.2723266292
Short name T781
Test name
Test status
Simulation time 162556900 ps
CPU time 195.35 seconds
Started Jun 11 03:11:00 PM PDT 24
Finished Jun 11 03:14:16 PM PDT 24
Peak memory 279136 kb
Host smart-bcd033e1-4ede-4a45-836a-8a048782fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723266292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2723266292
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.21926559
Short name T410
Test name
Test status
Simulation time 212559800 ps
CPU time 34.88 seconds
Started Jun 11 03:11:16 PM PDT 24
Finished Jun 11 03:11:52 PM PDT 24
Peak memory 275748 kb
Host smart-ca099791-0cd5-4301-9df8-c1340e006733
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21926559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_re_evict.21926559
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.1280268045
Short name T186
Test name
Test status
Simulation time 623479400 ps
CPU time 132.93 seconds
Started Jun 11 03:11:10 PM PDT 24
Finished Jun 11 03:13:24 PM PDT 24
Peak memory 290424 kb
Host smart-903a4325-a4c2-4c69-8365-1f9dedef49ff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280268045 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.1280268045
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3861173834
Short name T711
Test name
Test status
Simulation time 17713976800 ps
CPU time 605.52 seconds
Started Jun 11 03:11:07 PM PDT 24
Finished Jun 11 03:21:13 PM PDT 24
Peak memory 310048 kb
Host smart-546c80e6-7e86-4b8d-bbc5-cb137e0667a0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861173834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.3861173834
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.3052311586
Short name T1022
Test name
Test status
Simulation time 28525200 ps
CPU time 28.13 seconds
Started Jun 11 03:11:15 PM PDT 24
Finished Jun 11 03:11:44 PM PDT 24
Peak memory 275652 kb
Host smart-be911cdd-d745-4574-a3ae-c15419c97341
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052311586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.3052311586
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3368062686
Short name T29
Test name
Test status
Simulation time 33193000 ps
CPU time 30.14 seconds
Started Jun 11 03:11:14 PM PDT 24
Finished Jun 11 03:11:45 PM PDT 24
Peak memory 275216 kb
Host smart-eacb3a6c-f2b0-468d-836a-71805d4ffafb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368062686 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3368062686
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.598144302
Short name T222
Test name
Test status
Simulation time 801270800 ps
CPU time 61.83 seconds
Started Jun 11 03:11:15 PM PDT 24
Finished Jun 11 03:12:17 PM PDT 24
Peak memory 264340 kb
Host smart-0934ceb3-eddd-4909-9c62-351fd5e8d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598144302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.598144302
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3086516676
Short name T378
Test name
Test status
Simulation time 58216400 ps
CPU time 52.65 seconds
Started Jun 11 03:10:57 PM PDT 24
Finished Jun 11 03:11:51 PM PDT 24
Peak memory 270084 kb
Host smart-c81b2973-7445-4f18-9d2d-a91955304191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086516676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3086516676
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.2999911477
Short name T589
Test name
Test status
Simulation time 11256746200 ps
CPU time 259.4 seconds
Started Jun 11 03:11:06 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 265420 kb
Host smart-441ac231-74b8-4030-a01e-29645e7eea6a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999911477 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.2999911477
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.4241386608
Short name T23
Test name
Test status
Simulation time 42759600 ps
CPU time 13.7 seconds
Started Jun 11 03:01:24 PM PDT 24
Finished Jun 11 03:01:38 PM PDT 24
Peak memory 265784 kb
Host smart-a54e4986-3d39-4ac6-8c13-373f500f3b7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241386608 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.4241386608
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.3283556472
Short name T808
Test name
Test status
Simulation time 30123700 ps
CPU time 13.8 seconds
Started Jun 11 03:01:41 PM PDT 24
Finished Jun 11 03:01:55 PM PDT 24
Peak memory 265736 kb
Host smart-fb1686f9-88e3-4752-a44d-f878e9614c04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283556472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3
283556472
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.2786234186
Short name T967
Test name
Test status
Simulation time 124015300 ps
CPU time 14.44 seconds
Started Jun 11 03:01:25 PM PDT 24
Finished Jun 11 03:01:40 PM PDT 24
Peak memory 265172 kb
Host smart-488d62d9-8a76-4dee-a41e-9e91c8ecca16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786234186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.2786234186
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.2767919128
Short name T455
Test name
Test status
Simulation time 144836000 ps
CPU time 13.36 seconds
Started Jun 11 03:01:17 PM PDT 24
Finished Jun 11 03:01:31 PM PDT 24
Peak memory 275072 kb
Host smart-7ebd9b23-4c08-4510-bd32-a856ce5836cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767919128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2767919128
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.4011385576
Short name T594
Test name
Test status
Simulation time 123592700 ps
CPU time 104.61 seconds
Started Jun 11 03:01:08 PM PDT 24
Finished Jun 11 03:02:53 PM PDT 24
Peak memory 282232 kb
Host smart-4b492b2d-614f-493d-86c2-ad235404409b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011385576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.4011385576
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3807377549
Short name T592
Test name
Test status
Simulation time 68786700 ps
CPU time 22.09 seconds
Started Jun 11 03:01:15 PM PDT 24
Finished Jun 11 03:01:38 PM PDT 24
Peak memory 274016 kb
Host smart-085a82e9-45de-424a-b72a-ce925cb71a8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807377549 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3807377549
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1313386021
Short name T869
Test name
Test status
Simulation time 27705982300 ps
CPU time 2146.6 seconds
Started Jun 11 03:00:47 PM PDT 24
Finished Jun 11 03:36:34 PM PDT 24
Peak memory 265476 kb
Host smart-b72213bf-8546-4569-a3c6-76e291a5cfda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313386021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1313386021
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.2175449271
Short name T192
Test name
Test status
Simulation time 3863995600 ps
CPU time 2496.67 seconds
Started Jun 11 03:00:47 PM PDT 24
Finished Jun 11 03:42:25 PM PDT 24
Peak memory 265200 kb
Host smart-76b7447c-ecde-463e-b927-1b2242404ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175449271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.2175449271
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1986618338
Short name T686
Test name
Test status
Simulation time 584537500 ps
CPU time 777.68 seconds
Started Jun 11 03:00:50 PM PDT 24
Finished Jun 11 03:13:49 PM PDT 24
Peak memory 273756 kb
Host smart-8b8160b4-d51d-4ef4-b2ec-dd019ee00876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986618338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1986618338
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.3643571151
Short name T676
Test name
Test status
Simulation time 907767500 ps
CPU time 23.93 seconds
Started Jun 11 03:00:39 PM PDT 24
Finished Jun 11 03:01:04 PM PDT 24
Peak memory 262776 kb
Host smart-713314b7-c12f-4ac5-aae9-935fa672d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643571151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3643571151
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.208232003
Short name T1051
Test name
Test status
Simulation time 865690600 ps
CPU time 37.29 seconds
Started Jun 11 03:01:27 PM PDT 24
Finished Jun 11 03:02:05 PM PDT 24
Peak memory 263072 kb
Host smart-fb4422cb-af69-4ace-a708-37917d69e8de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208232003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.208232003
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2481108505
Short name T907
Test name
Test status
Simulation time 99781039400 ps
CPU time 4356.87 seconds
Started Jun 11 03:00:49 PM PDT 24
Finished Jun 11 04:13:28 PM PDT 24
Peak memory 265572 kb
Host smart-aa2a9fb1-bdf0-4b09-98b4-7a398d947fbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481108505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2481108505
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.482694117
Short name T179
Test name
Test status
Simulation time 282057568400 ps
CPU time 2014.31 seconds
Started Jun 11 03:00:38 PM PDT 24
Finished Jun 11 03:34:13 PM PDT 24
Peak memory 264408 kb
Host smart-152efd6c-b734-41d9-8407-d2259bcb950a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482694117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.482694117
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.818107475
Short name T795
Test name
Test status
Simulation time 28334100 ps
CPU time 37.09 seconds
Started Jun 11 03:00:30 PM PDT 24
Finished Jun 11 03:01:09 PM PDT 24
Peak memory 262852 kb
Host smart-f1d61b22-754c-43ba-bf93-507f450eb3a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=818107475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.818107475
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2336814746
Short name T953
Test name
Test status
Simulation time 10036779000 ps
CPU time 100.04 seconds
Started Jun 11 03:01:32 PM PDT 24
Finished Jun 11 03:03:13 PM PDT 24
Peak memory 267192 kb
Host smart-1e1c5659-fe51-43e2-986c-405ae40d8a9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336814746 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2336814746
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.456380558
Short name T731
Test name
Test status
Simulation time 19217000 ps
CPU time 13.4 seconds
Started Jun 11 03:01:50 PM PDT 24
Finished Jun 11 03:02:04 PM PDT 24
Peak memory 259588 kb
Host smart-8f7e960b-7a86-4494-8fdf-fc14be6a92ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456380558 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.456380558
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.820197023
Short name T672
Test name
Test status
Simulation time 83818602000 ps
CPU time 1889.34 seconds
Started Jun 11 03:00:30 PM PDT 24
Finished Jun 11 03:32:01 PM PDT 24
Peak memory 261460 kb
Host smart-b5294781-0ca5-4a19-ad5e-558069ba070d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820197023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_hw_rma.820197023
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.4159267501
Short name T822
Test name
Test status
Simulation time 160175810400 ps
CPU time 868.62 seconds
Started Jun 11 03:00:38 PM PDT 24
Finished Jun 11 03:15:08 PM PDT 24
Peak memory 264340 kb
Host smart-e8948087-387c-4a20-8288-9d12a907ebf3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159267501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.4159267501
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1321904610
Short name T452
Test name
Test status
Simulation time 10966660100 ps
CPU time 226.46 seconds
Started Jun 11 03:00:30 PM PDT 24
Finished Jun 11 03:04:18 PM PDT 24
Peak memory 263468 kb
Host smart-37e4448a-96f1-448b-bf4c-e39ff4c1a49d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321904610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1321904610
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2391733696
Short name T255
Test name
Test status
Simulation time 13892418300 ps
CPU time 744.92 seconds
Started Jun 11 03:01:05 PM PDT 24
Finished Jun 11 03:13:31 PM PDT 24
Peak memory 334928 kb
Host smart-28ac0e6f-88d4-48a0-85b4-1dba17efcd8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391733696 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2391733696
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.602421430
Short name T620
Test name
Test status
Simulation time 10089342600 ps
CPU time 251.1 seconds
Started Jun 11 03:01:06 PM PDT 24
Finished Jun 11 03:05:18 PM PDT 24
Peak memory 285176 kb
Host smart-9bfa4f87-5583-406a-9f28-563555e30a5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602421430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash
_ctrl_intr_rd.602421430
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1631561555
Short name T582
Test name
Test status
Simulation time 157595740000 ps
CPU time 297.53 seconds
Started Jun 11 03:01:15 PM PDT 24
Finished Jun 11 03:06:14 PM PDT 24
Peak memory 292112 kb
Host smart-3e1043a2-8e2a-4ef8-bebd-0f338d38d1bf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631561555 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.1631561555
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.785189655
Short name T32
Test name
Test status
Simulation time 2296799400 ps
CPU time 72.38 seconds
Started Jun 11 03:01:15 PM PDT 24
Finished Jun 11 03:02:29 PM PDT 24
Peak memory 265424 kb
Host smart-7610426b-a764-4a49-9cbb-073b560e1c5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785189655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.785189655
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2343243569
Short name T901
Test name
Test status
Simulation time 80125910900 ps
CPU time 272.03 seconds
Started Jun 11 03:01:13 PM PDT 24
Finished Jun 11 03:05:45 PM PDT 24
Peak memory 260872 kb
Host smart-7a36bf43-4f82-4939-9044-9c94e133f332
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234
3243569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2343243569
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.2417673046
Short name T664
Test name
Test status
Simulation time 2181646000 ps
CPU time 74.26 seconds
Started Jun 11 03:00:49 PM PDT 24
Finished Jun 11 03:02:04 PM PDT 24
Peak memory 260744 kb
Host smart-10cde861-44cb-4294-94ca-c62f5461d932
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417673046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2417673046
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.519402074
Short name T150
Test name
Test status
Simulation time 2578982400 ps
CPU time 73.68 seconds
Started Jun 11 03:00:47 PM PDT 24
Finished Jun 11 03:02:02 PM PDT 24
Peak memory 261068 kb
Host smart-4076de0d-01e5-4528-85b7-5471ff65a72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519402074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.519402074
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.1324827644
Short name T88
Test name
Test status
Simulation time 8560724900 ps
CPU time 669.73 seconds
Started Jun 11 03:00:39 PM PDT 24
Finished Jun 11 03:11:49 PM PDT 24
Peak memory 274792 kb
Host smart-ad25a14b-028d-4061-b5a5-0d3d24bbc0a4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324827644 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.1324827644
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2830974401
Short name T546
Test name
Test status
Simulation time 143477600 ps
CPU time 130 seconds
Started Jun 11 03:01:29 PM PDT 24
Finished Jun 11 03:03:39 PM PDT 24
Peak memory 260100 kb
Host smart-7e928a8c-d4cf-4886-a60e-bea5f0a04f0d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830974401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2830974401
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.4010845468
Short name T718
Test name
Test status
Simulation time 9649310100 ps
CPU time 135.84 seconds
Started Jun 11 03:01:06 PM PDT 24
Finished Jun 11 03:03:23 PM PDT 24
Peak memory 290484 kb
Host smart-87216881-e2c6-421f-8277-c0e13c0ee45a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010845468 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4010845468
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1926671428
Short name T231
Test name
Test status
Simulation time 24548000 ps
CPU time 13.99 seconds
Started Jun 11 03:01:22 PM PDT 24
Finished Jun 11 03:01:37 PM PDT 24
Peak memory 265308 kb
Host smart-faefa4ed-777e-49ab-a56e-1f46494565f0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1926671428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1926671428
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.2589052494
Short name T492
Test name
Test status
Simulation time 709973400 ps
CPU time 168.51 seconds
Started Jun 11 03:00:32 PM PDT 24
Finished Jun 11 03:03:22 PM PDT 24
Peak memory 263396 kb
Host smart-f6e13779-042e-4a5c-99de-1b95bb2ed305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2589052494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2589052494
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.1270288542
Short name T875
Test name
Test status
Simulation time 97013500 ps
CPU time 13.51 seconds
Started Jun 11 03:01:14 PM PDT 24
Finished Jun 11 03:01:29 PM PDT 24
Peak memory 259296 kb
Host smart-bc84f0c8-8770-434e-857e-eaa1b1417bc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270288542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.1270288542
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.95111898
Short name T113
Test name
Test status
Simulation time 222866700 ps
CPU time 1072.7 seconds
Started Jun 11 03:00:29 PM PDT 24
Finished Jun 11 03:18:24 PM PDT 24
Peak memory 286816 kb
Host smart-b91480a2-a868-4216-84e0-f7a49d5b7d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95111898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.95111898
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.214147704
Short name T542
Test name
Test status
Simulation time 950260300 ps
CPU time 97.63 seconds
Started Jun 11 03:00:30 PM PDT 24
Finished Jun 11 03:02:09 PM PDT 24
Peak memory 262896 kb
Host smart-714b4eac-59d4-4e4a-8ab4-a91a5410bed2
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214147704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.214147704
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3478222755
Short name T656
Test name
Test status
Simulation time 111465700 ps
CPU time 31.62 seconds
Started Jun 11 03:01:14 PM PDT 24
Finished Jun 11 03:01:46 PM PDT 24
Peak memory 275272 kb
Host smart-82ff11c2-d7f8-41bc-806f-efde38b1e7b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478222755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3478222755
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.568304278
Short name T94
Test name
Test status
Simulation time 104180700 ps
CPU time 35.17 seconds
Started Jun 11 03:01:14 PM PDT 24
Finished Jun 11 03:01:50 PM PDT 24
Peak memory 277092 kb
Host smart-ba0c092d-7d62-4d8c-bea6-cf7e6484ccc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568304278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_re_evict.568304278
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.1581808114
Short name T671
Test name
Test status
Simulation time 34336000 ps
CPU time 22.38 seconds
Started Jun 11 03:01:05 PM PDT 24
Finished Jun 11 03:01:28 PM PDT 24
Peak memory 265820 kb
Host smart-7cc95076-93dc-4100-bce4-065df5b8cd72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581808114 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.1581808114
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.2317318613
Short name T60
Test name
Test status
Simulation time 459913400 ps
CPU time 161.7 seconds
Started Jun 11 03:00:48 PM PDT 24
Finished Jun 11 03:03:31 PM PDT 24
Peak memory 282212 kb
Host smart-952a7fef-a229-4c08-8629-87dfac7db95a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317318613 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.2317318613
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.2877504061
Short name T689
Test name
Test status
Simulation time 560889400 ps
CPU time 148.64 seconds
Started Jun 11 03:00:56 PM PDT 24
Finished Jun 11 03:03:26 PM PDT 24
Peak memory 295404 kb
Host smart-f560d306-3975-4bb1-8953-1e99f08f4ee8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877504061 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.2877504061
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.2312853251
Short name T824
Test name
Test status
Simulation time 8754069000 ps
CPU time 566.59 seconds
Started Jun 11 03:00:57 PM PDT 24
Finished Jun 11 03:10:25 PM PDT 24
Peak memory 310036 kb
Host smart-9b02225b-10a4-432c-a8ad-9baeb468382d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312853251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.2312853251
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2990024637
Short name T171
Test name
Test status
Simulation time 20561221100 ps
CPU time 632.15 seconds
Started Jun 11 03:01:05 PM PDT 24
Finished Jun 11 03:11:38 PM PDT 24
Peak memory 315028 kb
Host smart-c014eb7a-841a-454f-a656-06cbebe25da5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990024637 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.2990024637
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.45988972
Short name T280
Test name
Test status
Simulation time 77309000 ps
CPU time 28.16 seconds
Started Jun 11 03:01:15 PM PDT 24
Finished Jun 11 03:01:44 PM PDT 24
Peak memory 267876 kb
Host smart-f0a9b10a-e95c-4642-8508-acee43b71d38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45988972 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.45988972
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.1920746977
Short name T1020
Test name
Test status
Simulation time 3766094700 ps
CPU time 608.77 seconds
Started Jun 11 03:00:55 PM PDT 24
Finished Jun 11 03:11:05 PM PDT 24
Peak memory 321064 kb
Host smart-221e3262-95c9-4421-9322-e67295b99478
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920746977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.1920746977
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.2482861477
Short name T98
Test name
Test status
Simulation time 1086199300 ps
CPU time 51.64 seconds
Started Jun 11 03:00:55 PM PDT 24
Finished Jun 11 03:01:48 PM PDT 24
Peak memory 265796 kb
Host smart-aa3b4d72-fc0f-40c5-a56f-dff2ad375a8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482861477 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.2482861477
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.2041600228
Short name T514
Test name
Test status
Simulation time 4683350600 ps
CPU time 75.31 seconds
Started Jun 11 03:00:56 PM PDT 24
Finished Jun 11 03:02:13 PM PDT 24
Peak memory 273984 kb
Host smart-044c9f24-9127-4419-b1ce-2da5b422fbde
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041600228 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.2041600228
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.571745098
Short name T636
Test name
Test status
Simulation time 23366900 ps
CPU time 74.45 seconds
Started Jun 11 03:00:22 PM PDT 24
Finished Jun 11 03:01:38 PM PDT 24
Peak memory 276824 kb
Host smart-4685aeb2-0a82-455f-9332-1699c15fac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571745098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.571745098
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2243929733
Short name T58
Test name
Test status
Simulation time 183545200 ps
CPU time 23.62 seconds
Started Jun 11 03:00:21 PM PDT 24
Finished Jun 11 03:00:46 PM PDT 24
Peak memory 259960 kb
Host smart-f8a45351-202c-470d-b9a5-706df9570c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243929733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2243929733
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2672856700
Short name T1008
Test name
Test status
Simulation time 57042300 ps
CPU time 137.23 seconds
Started Jun 11 03:01:14 PM PDT 24
Finished Jun 11 03:03:33 PM PDT 24
Peak memory 270100 kb
Host smart-339936c6-3413-41f2-a9a4-49b7cbff197d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672856700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2672856700
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3026157369
Short name T472
Test name
Test status
Simulation time 47054100 ps
CPU time 26.47 seconds
Started Jun 11 03:00:32 PM PDT 24
Finished Jun 11 03:01:00 PM PDT 24
Peak memory 262444 kb
Host smart-abe61d7e-8b95-4f01-b81e-e5c5cbd163fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026157369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3026157369
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2986430612
Short name T449
Test name
Test status
Simulation time 2376859600 ps
CPU time 205.59 seconds
Started Jun 11 03:00:46 PM PDT 24
Finished Jun 11 03:04:12 PM PDT 24
Peak memory 265128 kb
Host smart-824b2b0f-cf5e-4523-b5e2-b885056a2c72
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986430612 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.2986430612
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.3367808204
Short name T743
Test name
Test status
Simulation time 38209500 ps
CPU time 13.78 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:11:48 PM PDT 24
Peak memory 258688 kb
Host smart-66733eed-3a18-480f-bab3-6f9de96df6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367808204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
3367808204
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.764019640
Short name T1026
Test name
Test status
Simulation time 18432300 ps
CPU time 13.14 seconds
Started Jun 11 03:11:25 PM PDT 24
Finished Jun 11 03:11:39 PM PDT 24
Peak memory 284632 kb
Host smart-45fdc715-6fe7-4472-ae01-7d5007a9d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764019640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.764019640
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.1693050197
Short name T384
Test name
Test status
Simulation time 22030800 ps
CPU time 22.26 seconds
Started Jun 11 03:11:23 PM PDT 24
Finished Jun 11 03:11:46 PM PDT 24
Peak memory 274004 kb
Host smart-151c7bb2-8362-49a4-a274-49525631169c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693050197 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.1693050197
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.664154339
Short name T584
Test name
Test status
Simulation time 4986296600 ps
CPU time 65.26 seconds
Started Jun 11 03:11:24 PM PDT 24
Finished Jun 11 03:12:31 PM PDT 24
Peak memory 263496 kb
Host smart-47cffa84-496a-4d6a-bd51-098f938b3fe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664154339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_h
w_sec_otp.664154339
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.937142137
Short name T1055
Test name
Test status
Simulation time 8783916300 ps
CPU time 159.07 seconds
Started Jun 11 03:11:25 PM PDT 24
Finished Jun 11 03:14:05 PM PDT 24
Peak memory 292676 kb
Host smart-b6562704-7c0c-4eb4-aa0d-ba126b85575a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937142137 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.937142137
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2323752200
Short name T911
Test name
Test status
Simulation time 74824400 ps
CPU time 131.66 seconds
Started Jun 11 03:11:25 PM PDT 24
Finished Jun 11 03:13:38 PM PDT 24
Peak memory 260380 kb
Host smart-74431c02-10f5-45fb-9521-57d430733df0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323752200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2323752200
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.3408725787
Short name T494
Test name
Test status
Simulation time 2242785900 ps
CPU time 195.34 seconds
Started Jun 11 03:11:25 PM PDT 24
Finished Jun 11 03:14:41 PM PDT 24
Peak memory 259940 kb
Host smart-744f8936-cb07-48f6-ae7c-fdfa13f5cca9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408725787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.3408725787
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1442385601
Short name T888
Test name
Test status
Simulation time 184832700 ps
CPU time 30.75 seconds
Started Jun 11 03:11:26 PM PDT 24
Finished Jun 11 03:11:57 PM PDT 24
Peak memory 275232 kb
Host smart-f77a706e-d21e-4ed1-9d62-b7ab920f437a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442385601 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1442385601
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3470846748
Short name T207
Test name
Test status
Simulation time 453347900 ps
CPU time 61.89 seconds
Started Jun 11 03:11:25 PM PDT 24
Finished Jun 11 03:12:28 PM PDT 24
Peak memory 263720 kb
Host smart-33d2d462-7c00-4954-9159-2a1711bdc32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470846748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3470846748
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1520842966
Short name T850
Test name
Test status
Simulation time 112356100 ps
CPU time 144.01 seconds
Started Jun 11 03:11:26 PM PDT 24
Finished Jun 11 03:13:51 PM PDT 24
Peak memory 277156 kb
Host smart-acb72a43-7b66-4d82-aa90-d8c3c0058caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520842966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1520842966
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.215809779
Short name T502
Test name
Test status
Simulation time 161730900 ps
CPU time 13.78 seconds
Started Jun 11 03:11:34 PM PDT 24
Finished Jun 11 03:11:50 PM PDT 24
Peak memory 258600 kb
Host smart-e5a94012-a127-4ad5-b37e-81d785727539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215809779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.215809779
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.666040545
Short name T474
Test name
Test status
Simulation time 21207800 ps
CPU time 13.36 seconds
Started Jun 11 03:11:34 PM PDT 24
Finished Jun 11 03:11:50 PM PDT 24
Peak memory 275228 kb
Host smart-1533cc8c-a221-4f40-8901-b1b46505ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666040545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.666040545
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3576087132
Short name T308
Test name
Test status
Simulation time 28236300 ps
CPU time 21.73 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:11:56 PM PDT 24
Peak memory 274144 kb
Host smart-771064e3-ca04-497f-a6e5-af8199eda3a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576087132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3576087132
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1831591776
Short name T803
Test name
Test status
Simulation time 6612510900 ps
CPU time 266.8 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:16:02 PM PDT 24
Peak memory 263488 kb
Host smart-5c30eb64-166d-469c-9afe-e0109a5958ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831591776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1831591776
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1667809598
Short name T842
Test name
Test status
Simulation time 2564559100 ps
CPU time 136.3 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:13:51 PM PDT 24
Peak memory 285208 kb
Host smart-0c9ec9c5-e03e-4506-8ab3-00331c9f2b72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667809598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1667809598
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.4157441555
Short name T447
Test name
Test status
Simulation time 6884524400 ps
CPU time 144.52 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:14:00 PM PDT 24
Peak memory 293032 kb
Host smart-c4b1b78b-9627-4813-943f-fe3c08a3abbe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157441555 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.4157441555
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2291904704
Short name T1019
Test name
Test status
Simulation time 42854800 ps
CPU time 130.14 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:13:44 PM PDT 24
Peak memory 260384 kb
Host smart-9db0fbf2-5399-4459-acd6-a4b0260b8736
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291904704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2291904704
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.140645596
Short name T756
Test name
Test status
Simulation time 2096336400 ps
CPU time 177.51 seconds
Started Jun 11 03:11:34 PM PDT 24
Finished Jun 11 03:14:34 PM PDT 24
Peak memory 265216 kb
Host smart-0f85651e-c8f6-4526-8a8c-983922188db2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140645596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.140645596
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.1664499747
Short name T286
Test name
Test status
Simulation time 31596300 ps
CPU time 27.86 seconds
Started Jun 11 03:11:34 PM PDT 24
Finished Jun 11 03:12:03 PM PDT 24
Peak memory 277668 kb
Host smart-322ab64b-be52-4204-b060-c356b4384ed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664499747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.1664499747
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3737243634
Short name T53
Test name
Test status
Simulation time 79591300 ps
CPU time 31.06 seconds
Started Jun 11 03:11:34 PM PDT 24
Finished Jun 11 03:12:07 PM PDT 24
Peak memory 275104 kb
Host smart-90d666a8-988d-4ec0-8712-40a763f1a1dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737243634 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3737243634
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1256227683
Short name T421
Test name
Test status
Simulation time 53975400 ps
CPU time 169.53 seconds
Started Jun 11 03:11:33 PM PDT 24
Finished Jun 11 03:14:25 PM PDT 24
Peak memory 280032 kb
Host smart-f549eb52-f92b-4510-a31c-f8aa43b8d6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256227683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1256227683
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.25056848
Short name T785
Test name
Test status
Simulation time 39117900 ps
CPU time 13.48 seconds
Started Jun 11 03:11:46 PM PDT 24
Finished Jun 11 03:12:00 PM PDT 24
Peak memory 258552 kb
Host smart-9c606a6b-ee88-44bc-b1db-8ba65dc9b99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.25056848
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.3065591810
Short name T1087
Test name
Test status
Simulation time 22267600 ps
CPU time 13.42 seconds
Started Jun 11 03:11:46 PM PDT 24
Finished Jun 11 03:12:00 PM PDT 24
Peak memory 284556 kb
Host smart-e6677251-ed63-4f99-a66d-69f80a2b8b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065591810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3065591810
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.946546377
Short name T782
Test name
Test status
Simulation time 93941500 ps
CPU time 21.78 seconds
Started Jun 11 03:11:41 PM PDT 24
Finished Jun 11 03:12:04 PM PDT 24
Peak memory 265720 kb
Host smart-907b60ef-dc4e-4f6b-b8ac-c0e0774fc8c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946546377 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.946546377
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3939169924
Short name T1009
Test name
Test status
Simulation time 9883898500 ps
CPU time 208.83 seconds
Started Jun 11 03:11:43 PM PDT 24
Finished Jun 11 03:15:12 PM PDT 24
Peak memory 263384 kb
Host smart-d8f2adb8-e903-4d6c-89d3-f76e87a57351
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939169924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.3939169924
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.796059128
Short name T886
Test name
Test status
Simulation time 1635649800 ps
CPU time 228.92 seconds
Started Jun 11 03:11:41 PM PDT 24
Finished Jun 11 03:15:31 PM PDT 24
Peak memory 285268 kb
Host smart-010c2080-a3f4-412e-a7f5-0d574b70a3ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796059128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.796059128
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.214888213
Short name T36
Test name
Test status
Simulation time 170444154100 ps
CPU time 361.22 seconds
Started Jun 11 03:11:42 PM PDT 24
Finished Jun 11 03:17:45 PM PDT 24
Peak memory 293264 kb
Host smart-a80da897-9169-4958-b7d3-295196962fc6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214888213 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.214888213
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.4224381400
Short name T985
Test name
Test status
Simulation time 57338700 ps
CPU time 13.41 seconds
Started Jun 11 03:11:41 PM PDT 24
Finished Jun 11 03:11:56 PM PDT 24
Peak memory 259136 kb
Host smart-d0f481e1-826d-4a35-9fb5-37b18137a580
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224381400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.4224381400
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1481804015
Short name T836
Test name
Test status
Simulation time 75409900 ps
CPU time 30.95 seconds
Started Jun 11 03:11:42 PM PDT 24
Finished Jun 11 03:12:14 PM PDT 24
Peak memory 270116 kb
Host smart-a255a3d9-e955-4b50-ba2d-180d26cbbb59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481804015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1481804015
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.1077437723
Short name T443
Test name
Test status
Simulation time 30923300 ps
CPU time 31.49 seconds
Started Jun 11 03:11:44 PM PDT 24
Finished Jun 11 03:12:16 PM PDT 24
Peak memory 267860 kb
Host smart-d4f6b152-0a04-4b6c-957d-506541e4c2f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077437723 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.1077437723
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1148424189
Short name T393
Test name
Test status
Simulation time 3299969700 ps
CPU time 76.74 seconds
Started Jun 11 03:11:45 PM PDT 24
Finished Jun 11 03:13:03 PM PDT 24
Peak memory 263980 kb
Host smart-796ddfdd-7f9d-4758-af4a-d387a511cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148424189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1148424189
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3283105892
Short name T533
Test name
Test status
Simulation time 135913100 ps
CPU time 99.11 seconds
Started Jun 11 03:11:42 PM PDT 24
Finished Jun 11 03:13:22 PM PDT 24
Peak memory 277056 kb
Host smart-3a120fe0-e25e-45cb-8208-dafa54896f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283105892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3283105892
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1272493020
Short name T931
Test name
Test status
Simulation time 26463800 ps
CPU time 13.68 seconds
Started Jun 11 03:11:50 PM PDT 24
Finished Jun 11 03:12:05 PM PDT 24
Peak memory 265568 kb
Host smart-dec95b2a-2d86-476b-a6ef-6a68b8f21f4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272493020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1272493020
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.146203511
Short name T580
Test name
Test status
Simulation time 47719200 ps
CPU time 15.6 seconds
Started Jun 11 03:11:50 PM PDT 24
Finished Jun 11 03:12:06 PM PDT 24
Peak memory 275212 kb
Host smart-bfe53b5d-ce86-402d-a86b-c94f170abe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146203511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.146203511
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.9423003
Short name T1005
Test name
Test status
Simulation time 7682260700 ps
CPU time 161.49 seconds
Started Jun 11 03:11:51 PM PDT 24
Finished Jun 11 03:14:33 PM PDT 24
Peak memory 263356 kb
Host smart-84293186-eef0-4b88-9f27-8376a1c506f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9423003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_
sec_otp.9423003
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2077400384
Short name T900
Test name
Test status
Simulation time 20733458300 ps
CPU time 294.29 seconds
Started Jun 11 03:11:50 PM PDT 24
Finished Jun 11 03:16:44 PM PDT 24
Peak memory 285228 kb
Host smart-fba50d0d-c49e-4012-b271-e350ee353d60
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077400384 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2077400384
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.23590928
Short name T597
Test name
Test status
Simulation time 140127000 ps
CPU time 131.17 seconds
Started Jun 11 03:11:51 PM PDT 24
Finished Jun 11 03:14:03 PM PDT 24
Peak memory 261400 kb
Host smart-ca1cc727-a838-42b6-b517-517c79bb2faa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23590928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp
_reset.23590928
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3606962172
Short name T925
Test name
Test status
Simulation time 9439209700 ps
CPU time 221.72 seconds
Started Jun 11 03:11:51 PM PDT 24
Finished Jun 11 03:15:33 PM PDT 24
Peak memory 259932 kb
Host smart-41de9d11-7b46-40e0-ba40-55e79c70e244
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606962172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3606962172
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.653254950
Short name T821
Test name
Test status
Simulation time 26757600 ps
CPU time 30.09 seconds
Started Jun 11 03:11:52 PM PDT 24
Finished Jun 11 03:12:23 PM PDT 24
Peak memory 275300 kb
Host smart-fe017abd-1e7c-4d08-9c0c-8fcb3ee00ee1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653254950 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.653254950
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.391156905
Short name T733
Test name
Test status
Simulation time 180657900 ps
CPU time 144.04 seconds
Started Jun 11 03:11:42 PM PDT 24
Finished Jun 11 03:14:07 PM PDT 24
Peak memory 277072 kb
Host smart-c04d1fdd-933d-40ff-92ef-2633191390e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391156905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.391156905
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.1818889177
Short name T435
Test name
Test status
Simulation time 62010800 ps
CPU time 13.75 seconds
Started Jun 11 03:12:10 PM PDT 24
Finished Jun 11 03:12:25 PM PDT 24
Peak memory 258588 kb
Host smart-07040fbe-0fb9-4880-bdb9-c05a495a4da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818889177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
1818889177
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.1174293712
Short name T461
Test name
Test status
Simulation time 28498400 ps
CPU time 15.73 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:12:26 PM PDT 24
Peak memory 275056 kb
Host smart-f1ff0be8-ac20-4e2e-980d-1e8c331ddb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174293712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1174293712
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3344224464
Short name T373
Test name
Test status
Simulation time 31271600 ps
CPU time 21.64 seconds
Started Jun 11 03:12:10 PM PDT 24
Finished Jun 11 03:12:32 PM PDT 24
Peak memory 274000 kb
Host smart-3afd1f19-0f88-4792-a8d3-0b45063ad8fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344224464 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3344224464
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3405361305
Short name T416
Test name
Test status
Simulation time 4609198700 ps
CPU time 131.86 seconds
Started Jun 11 03:12:00 PM PDT 24
Finished Jun 11 03:14:12 PM PDT 24
Peak memory 262908 kb
Host smart-14e08cce-6765-439e-8326-a48bab9483fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405361305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.3405361305
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1224909479
Short name T881
Test name
Test status
Simulation time 3580178300 ps
CPU time 211.65 seconds
Started Jun 11 03:12:01 PM PDT 24
Finished Jun 11 03:15:33 PM PDT 24
Peak memory 285332 kb
Host smart-2520c478-61a7-408f-b18e-21bec11162b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224909479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1224909479
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3710768104
Short name T1011
Test name
Test status
Simulation time 5677879000 ps
CPU time 145.17 seconds
Started Jun 11 03:11:59 PM PDT 24
Finished Jun 11 03:14:25 PM PDT 24
Peak memory 292884 kb
Host smart-6ee78e4d-0559-47a8-9654-121b19b6d074
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710768104 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3710768104
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.4039181897
Short name T316
Test name
Test status
Simulation time 61256800 ps
CPU time 109.61 seconds
Started Jun 11 03:12:00 PM PDT 24
Finished Jun 11 03:13:51 PM PDT 24
Peak memory 261476 kb
Host smart-03f24258-bd28-432e-a379-7e3e7f422a14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039181897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.4039181897
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.104308980
Short name T714
Test name
Test status
Simulation time 18302800 ps
CPU time 13.93 seconds
Started Jun 11 03:12:00 PM PDT 24
Finished Jun 11 03:12:15 PM PDT 24
Peak memory 259028 kb
Host smart-30bc707c-da3b-4d05-a1b1-fdbf94f3b289
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104308980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_res
et.104308980
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3433033777
Short name T1059
Test name
Test status
Simulation time 31201500 ps
CPU time 31.8 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:12:42 PM PDT 24
Peak memory 268040 kb
Host smart-9996b67c-160b-491e-90ba-7cad178a2403
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433033777 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3433033777
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2167616367
Short name T647
Test name
Test status
Simulation time 3507527200 ps
CPU time 76.71 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:13:27 PM PDT 24
Peak memory 264828 kb
Host smart-731d60f0-3742-435c-9715-a8efd52494f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167616367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2167616367
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1018230761
Short name T520
Test name
Test status
Simulation time 19712900 ps
CPU time 99.36 seconds
Started Jun 11 03:12:00 PM PDT 24
Finished Jun 11 03:13:40 PM PDT 24
Peak memory 270024 kb
Host smart-228dd6ca-cd81-4ab1-8221-8954d0a1b441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018230761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1018230761
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.1295506178
Short name T1016
Test name
Test status
Simulation time 89119800 ps
CPU time 13.8 seconds
Started Jun 11 03:12:19 PM PDT 24
Finished Jun 11 03:12:34 PM PDT 24
Peak memory 258528 kb
Host smart-6fce79a0-730c-458a-8794-55cc847f6f08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295506178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
1295506178
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.560770668
Short name T638
Test name
Test status
Simulation time 16394100 ps
CPU time 21.85 seconds
Started Jun 11 03:12:18 PM PDT 24
Finished Jun 11 03:12:41 PM PDT 24
Peak memory 265436 kb
Host smart-3bc882a4-34c3-4c2a-9ac9-829f153b4672
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560770668 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.560770668
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.371863726
Short name T692
Test name
Test status
Simulation time 8885774400 ps
CPU time 175.53 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:15:06 PM PDT 24
Peak memory 263392 kb
Host smart-a666473f-ba97-497a-a2c5-788f9fc2ad1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371863726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_h
w_sec_otp.371863726
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.1734030481
Short name T964
Test name
Test status
Simulation time 1424589300 ps
CPU time 130.99 seconds
Started Jun 11 03:12:10 PM PDT 24
Finished Jun 11 03:14:22 PM PDT 24
Peak memory 295404 kb
Host smart-af677e8c-f9b9-4e14-8d18-0ce15e508652
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734030481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.1734030481
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3905280631
Short name T825
Test name
Test status
Simulation time 137460761100 ps
CPU time 299.15 seconds
Started Jun 11 03:12:12 PM PDT 24
Finished Jun 11 03:17:12 PM PDT 24
Peak memory 285232 kb
Host smart-ab049262-e35f-49c8-93a2-22429ca05ed1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905280631 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3905280631
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.3210464103
Short name T135
Test name
Test status
Simulation time 144722600 ps
CPU time 134.92 seconds
Started Jun 11 03:12:10 PM PDT 24
Finished Jun 11 03:14:26 PM PDT 24
Peak memory 260504 kb
Host smart-75d6dd45-36d5-4d36-b739-165451aead59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210464103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.3210464103
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.8064224
Short name T796
Test name
Test status
Simulation time 2667668200 ps
CPU time 235.23 seconds
Started Jun 11 03:12:11 PM PDT 24
Finished Jun 11 03:16:07 PM PDT 24
Peak memory 259956 kb
Host smart-881087c2-ee64-4622-9901-3d347d0a0919
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8064224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_re
set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.8064224
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3075954998
Short name T872
Test name
Test status
Simulation time 69478600 ps
CPU time 30.93 seconds
Started Jun 11 03:12:11 PM PDT 24
Finished Jun 11 03:12:42 PM PDT 24
Peak memory 275720 kb
Host smart-edb18830-3ae0-4b10-b176-b02a21bab4dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075954998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3075954998
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2836923093
Short name T169
Test name
Test status
Simulation time 79121500 ps
CPU time 31.68 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:12:41 PM PDT 24
Peak memory 268104 kb
Host smart-0b56c956-2630-4de8-8010-cdc7377d284e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836923093 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2836923093
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.3808120255
Short name T388
Test name
Test status
Simulation time 1868528100 ps
CPU time 56.89 seconds
Started Jun 11 03:12:18 PM PDT 24
Finished Jun 11 03:13:16 PM PDT 24
Peak memory 265520 kb
Host smart-366201b5-c220-4876-b19e-72e5e382477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808120255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3808120255
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1831463059
Short name T838
Test name
Test status
Simulation time 5245985800 ps
CPU time 291.9 seconds
Started Jun 11 03:12:09 PM PDT 24
Finished Jun 11 03:17:02 PM PDT 24
Peak memory 281916 kb
Host smart-6dc3c720-dd46-46d1-867a-746165d8bcc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831463059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1831463059
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.674422566
Short name T613
Test name
Test status
Simulation time 52726100 ps
CPU time 13.44 seconds
Started Jun 11 03:12:29 PM PDT 24
Finished Jun 11 03:12:43 PM PDT 24
Peak memory 265552 kb
Host smart-41b1edbf-1410-4db9-92f8-e17470312a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674422566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.674422566
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.3630395223
Short name T624
Test name
Test status
Simulation time 22499800 ps
CPU time 13.41 seconds
Started Jun 11 03:12:28 PM PDT 24
Finished Jun 11 03:12:42 PM PDT 24
Peak memory 284512 kb
Host smart-6189c300-26b1-47e0-85b1-6c53858f9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630395223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3630395223
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3521067954
Short name T727
Test name
Test status
Simulation time 38778900 ps
CPU time 21.89 seconds
Started Jun 11 03:12:21 PM PDT 24
Finished Jun 11 03:12:44 PM PDT 24
Peak memory 265848 kb
Host smart-c149d366-f74a-49b3-b7f3-368b942c4119
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521067954 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3521067954
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2624392317
Short name T541
Test name
Test status
Simulation time 9756920600 ps
CPU time 93.66 seconds
Started Jun 11 03:12:21 PM PDT 24
Finished Jun 11 03:13:55 PM PDT 24
Peak memory 263420 kb
Host smart-a147cae8-f76f-45e5-9734-9a5e5ee518f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624392317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.2624392317
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3965659281
Short name T940
Test name
Test status
Simulation time 3057191500 ps
CPU time 132.51 seconds
Started Jun 11 03:12:19 PM PDT 24
Finished Jun 11 03:14:33 PM PDT 24
Peak memory 293988 kb
Host smart-e1cc4779-87c4-4382-bd0d-fd3a2e860c2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965659281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3965659281
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.160622368
Short name T558
Test name
Test status
Simulation time 49205987700 ps
CPU time 332.63 seconds
Started Jun 11 03:12:18 PM PDT 24
Finished Jun 11 03:17:52 PM PDT 24
Peak memory 285284 kb
Host smart-efe4a61e-d194-4b2e-a803-419f70ecd241
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160622368 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.160622368
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.4245475434
Short name T605
Test name
Test status
Simulation time 254524300 ps
CPU time 13.96 seconds
Started Jun 11 03:12:22 PM PDT 24
Finished Jun 11 03:12:37 PM PDT 24
Peak memory 265584 kb
Host smart-148f63e2-1a67-4b5a-ac21-0176c3b443f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245475434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.4245475434
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3878609262
Short name T402
Test name
Test status
Simulation time 20149296300 ps
CPU time 93.32 seconds
Started Jun 11 03:12:28 PM PDT 24
Finished Jun 11 03:14:03 PM PDT 24
Peak memory 259868 kb
Host smart-0c52e2d9-5d56-4946-8cdb-7e1aecd96886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878609262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3878609262
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3690293245
Short name T684
Test name
Test status
Simulation time 3635356000 ps
CPU time 195.73 seconds
Started Jun 11 03:12:19 PM PDT 24
Finished Jun 11 03:15:36 PM PDT 24
Peak memory 281844 kb
Host smart-135c2497-f479-4cec-b14b-368614b8be77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690293245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3690293245
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1870899274
Short name T464
Test name
Test status
Simulation time 327818900 ps
CPU time 13.99 seconds
Started Jun 11 03:12:38 PM PDT 24
Finished Jun 11 03:12:53 PM PDT 24
Peak memory 265552 kb
Host smart-b0431c26-c9a0-443b-8e90-53a0389b473b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870899274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1870899274
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3946463289
Short name T419
Test name
Test status
Simulation time 25085900 ps
CPU time 16.03 seconds
Started Jun 11 03:12:41 PM PDT 24
Finished Jun 11 03:12:57 PM PDT 24
Peak memory 284476 kb
Host smart-95926e35-c7f0-46bd-ab8b-d83a18cec637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946463289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3946463289
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.241870503
Short name T801
Test name
Test status
Simulation time 36780800 ps
CPU time 22.33 seconds
Started Jun 11 03:12:36 PM PDT 24
Finished Jun 11 03:13:00 PM PDT 24
Peak memory 273932 kb
Host smart-dda7e704-73f9-40f6-8807-e5dc88cafde0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241870503 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.241870503
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.254581440
Short name T847
Test name
Test status
Simulation time 1762481400 ps
CPU time 82.75 seconds
Started Jun 11 03:12:26 PM PDT 24
Finished Jun 11 03:13:50 PM PDT 24
Peak memory 263308 kb
Host smart-e3eea522-103f-46a1-9aec-a50c36b554e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254581440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.254581440
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1539676241
Short name T182
Test name
Test status
Simulation time 34564115200 ps
CPU time 249.23 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:16:47 PM PDT 24
Peak memory 292676 kb
Host smart-1e905522-7d6f-4ad8-a6ed-af1857816670
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539676241 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1539676241
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.2519137123
Short name T121
Test name
Test status
Simulation time 41648300 ps
CPU time 132.21 seconds
Started Jun 11 03:12:29 PM PDT 24
Finished Jun 11 03:14:44 PM PDT 24
Peak memory 260548 kb
Host smart-0f625281-719b-4da3-8fed-99ff51ebb5c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519137123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.2519137123
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.224712348
Short name T868
Test name
Test status
Simulation time 60080300 ps
CPU time 13.41 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:12:52 PM PDT 24
Peak memory 265412 kb
Host smart-f37bcaae-a5ab-4fc2-a069-de0d79232683
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224712348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.224712348
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.440163532
Short name T974
Test name
Test status
Simulation time 31729100 ps
CPU time 28.78 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:13:06 PM PDT 24
Peak memory 275720 kb
Host smart-c97085b9-f47d-4c13-a529-b3679c652308
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440163532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.440163532
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3578168268
Short name T682
Test name
Test status
Simulation time 66996700 ps
CPU time 31.14 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:13:09 PM PDT 24
Peak memory 267808 kb
Host smart-ea22a1e4-fae8-4520-a2ae-631eb516347b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578168268 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3578168268
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.2963793514
Short name T389
Test name
Test status
Simulation time 2475962300 ps
CPU time 56.06 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:13:35 PM PDT 24
Peak memory 263376 kb
Host smart-d5415ebe-9f2d-4b2f-a1b3-c5158839049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963793514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2963793514
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.1971018859
Short name T1031
Test name
Test status
Simulation time 61675700 ps
CPU time 190.25 seconds
Started Jun 11 03:12:28 PM PDT 24
Finished Jun 11 03:15:39 PM PDT 24
Peak memory 281396 kb
Host smart-ba710828-c9af-494a-9ff3-f98be2fa6b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971018859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1971018859
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1619111245
Short name T612
Test name
Test status
Simulation time 38602400 ps
CPU time 13.46 seconds
Started Jun 11 03:12:48 PM PDT 24
Finished Jun 11 03:13:03 PM PDT 24
Peak memory 258524 kb
Host smart-495110fe-f9e1-42ff-b18c-9541078d71fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619111245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1619111245
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1546479722
Short name T765
Test name
Test status
Simulation time 23564100 ps
CPU time 16.07 seconds
Started Jun 11 03:12:48 PM PDT 24
Finished Jun 11 03:13:06 PM PDT 24
Peak memory 275276 kb
Host smart-c6a015a8-b35a-44e8-9d70-d94b508b4bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546479722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1546479722
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3781623637
Short name T1049
Test name
Test status
Simulation time 2269947000 ps
CPU time 59.07 seconds
Started Jun 11 03:12:39 PM PDT 24
Finished Jun 11 03:13:39 PM PDT 24
Peak memory 262952 kb
Host smart-4fd33bc6-c18f-497f-a936-bd3c1c8e0e0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781623637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3781623637
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.4154251398
Short name T906
Test name
Test status
Simulation time 10324628900 ps
CPU time 155.08 seconds
Started Jun 11 03:12:39 PM PDT 24
Finished Jun 11 03:15:15 PM PDT 24
Peak memory 292932 kb
Host smart-757fd356-b9f6-43fe-8477-42fee01c3806
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154251398 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.4154251398
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.3847724205
Short name T486
Test name
Test status
Simulation time 39588000 ps
CPU time 132.14 seconds
Started Jun 11 03:12:39 PM PDT 24
Finished Jun 11 03:14:52 PM PDT 24
Peak memory 265920 kb
Host smart-78186b90-348a-4687-b125-bc65ded2d53f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847724205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.3847724205
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2464818844
Short name T1032
Test name
Test status
Simulation time 9389620900 ps
CPU time 159.76 seconds
Started Jun 11 03:12:37 PM PDT 24
Finished Jun 11 03:15:18 PM PDT 24
Peak memory 265664 kb
Host smart-d17b4089-d4e9-4baa-b60e-8193033de8d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464818844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2464818844
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3364551945
Short name T329
Test name
Test status
Simulation time 71367300 ps
CPU time 30.95 seconds
Started Jun 11 03:12:36 PM PDT 24
Finished Jun 11 03:13:08 PM PDT 24
Peak memory 275192 kb
Host smart-55d391a4-57c7-4bc2-95f0-80ae45d27452
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364551945 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3364551945
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.4078563110
Short name T398
Test name
Test status
Simulation time 23090618900 ps
CPU time 92.11 seconds
Started Jun 11 03:12:50 PM PDT 24
Finished Jun 11 03:14:23 PM PDT 24
Peak memory 265708 kb
Host smart-081d6760-c292-4fd3-b962-021dcf228c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078563110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4078563110
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.150285463
Short name T854
Test name
Test status
Simulation time 45221800 ps
CPU time 120.09 seconds
Started Jun 11 03:12:40 PM PDT 24
Finished Jun 11 03:14:41 PM PDT 24
Peak memory 277676 kb
Host smart-17e78032-e650-4a2f-ba22-6bc2c15c3701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150285463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.150285463
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3400953089
Short name T991
Test name
Test status
Simulation time 227562800 ps
CPU time 14.23 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:13:14 PM PDT 24
Peak memory 258536 kb
Host smart-49eea93f-07f0-4553-b247-b4edc3e68dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400953089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3400953089
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.4158511617
Short name T204
Test name
Test status
Simulation time 13637200 ps
CPU time 15.73 seconds
Started Jun 11 03:12:49 PM PDT 24
Finished Jun 11 03:13:07 PM PDT 24
Peak memory 275052 kb
Host smart-44ea6079-30e2-4864-a978-a3272a0e0dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158511617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.4158511617
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3931069357
Short name T600
Test name
Test status
Simulation time 2268733200 ps
CPU time 198.81 seconds
Started Jun 11 03:12:50 PM PDT 24
Finished Jun 11 03:16:10 PM PDT 24
Peak memory 263412 kb
Host smart-31c00e03-4e83-4008-bf12-409b5f1bafd7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931069357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3931069357
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1193439754
Short name T921
Test name
Test status
Simulation time 989997200 ps
CPU time 127.57 seconds
Started Jun 11 03:12:49 PM PDT 24
Finished Jun 11 03:14:58 PM PDT 24
Peak memory 294516 kb
Host smart-da30ca39-1d06-45f0-8a40-b636ef8ecd2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193439754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1193439754
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2045346920
Short name T38
Test name
Test status
Simulation time 17259538700 ps
CPU time 290.44 seconds
Started Jun 11 03:12:51 PM PDT 24
Finished Jun 11 03:17:43 PM PDT 24
Peak memory 291336 kb
Host smart-ba49f07e-380b-4872-b4ab-f19eac72818d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045346920 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.2045346920
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.3325583836
Short name T591
Test name
Test status
Simulation time 66862500 ps
CPU time 134.16 seconds
Started Jun 11 03:12:49 PM PDT 24
Finished Jun 11 03:15:05 PM PDT 24
Peak memory 265652 kb
Host smart-c48461bf-a7f8-4df7-a71e-1f33dad5e5a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325583836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.3325583836
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3143123715
Short name T440
Test name
Test status
Simulation time 60587200 ps
CPU time 14.09 seconds
Started Jun 11 03:12:49 PM PDT 24
Finished Jun 11 03:13:05 PM PDT 24
Peak memory 265452 kb
Host smart-7f0fcb81-3d35-4283-bdfb-da06b9b8d0ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143123715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3143123715
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.611267411
Short name T105
Test name
Test status
Simulation time 30808300 ps
CPU time 31.56 seconds
Started Jun 11 03:12:49 PM PDT 24
Finished Jun 11 03:13:22 PM PDT 24
Peak memory 276096 kb
Host smart-c549c8c5-cec9-4b39-9a9d-12db6cb26134
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611267411 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.611267411
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2271093561
Short name T396
Test name
Test status
Simulation time 5284128400 ps
CPU time 72.37 seconds
Started Jun 11 03:12:48 PM PDT 24
Finished Jun 11 03:14:02 PM PDT 24
Peak memory 263856 kb
Host smart-d06dec99-eaad-41cb-a990-e8b921b376f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271093561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2271093561
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.553646539
Short name T562
Test name
Test status
Simulation time 91728200 ps
CPU time 74.87 seconds
Started Jun 11 03:12:48 PM PDT 24
Finished Jun 11 03:14:05 PM PDT 24
Peak memory 275808 kb
Host smart-3afd0244-cace-49ba-896d-6cc4cda2b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553646539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.553646539
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.414785627
Short name T530
Test name
Test status
Simulation time 41767600 ps
CPU time 13.54 seconds
Started Jun 11 03:02:38 PM PDT 24
Finished Jun 11 03:02:53 PM PDT 24
Peak memory 258644 kb
Host smart-870b87ed-dff6-4fe6-8354-02e600255762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414785627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.414785627
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2312944129
Short name T1015
Test name
Test status
Simulation time 40962800 ps
CPU time 15.69 seconds
Started Jun 11 03:02:26 PM PDT 24
Finished Jun 11 03:02:43 PM PDT 24
Peak memory 275120 kb
Host smart-f13ba00f-8e72-4842-b354-ce7406150305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312944129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2312944129
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.658445744
Short name T258
Test name
Test status
Simulation time 180972500 ps
CPU time 102.53 seconds
Started Jun 11 03:02:19 PM PDT 24
Finished Jun 11 03:04:03 PM PDT 24
Peak memory 281200 kb
Host smart-a7f8660f-6d85-4d84-9149-0f6095af7989
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658445744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_derr_detect.658445744
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.1608283713
Short name T956
Test name
Test status
Simulation time 16284700 ps
CPU time 21.51 seconds
Started Jun 11 03:02:27 PM PDT 24
Finished Jun 11 03:02:50 PM PDT 24
Peak memory 265844 kb
Host smart-90972304-fada-4ad3-afc3-4f43da5ba453
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608283713 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.1608283713
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2988801440
Short name T739
Test name
Test status
Simulation time 5610335300 ps
CPU time 476.48 seconds
Started Jun 11 03:01:50 PM PDT 24
Finished Jun 11 03:09:47 PM PDT 24
Peak memory 263632 kb
Host smart-2357075a-6d7d-4781-9b87-4e86700e1c64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988801440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2988801440
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2055160137
Short name T237
Test name
Test status
Simulation time 16792529400 ps
CPU time 2204.88 seconds
Started Jun 11 03:02:00 PM PDT 24
Finished Jun 11 03:38:46 PM PDT 24
Peak memory 264864 kb
Host smart-73879e46-e0be-4df8-9009-d8dd41183db5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055160137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2055160137
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.1369870404
Short name T948
Test name
Test status
Simulation time 1737039600 ps
CPU time 2662.59 seconds
Started Jun 11 03:01:56 PM PDT 24
Finished Jun 11 03:46:20 PM PDT 24
Peak memory 262132 kb
Host smart-3cbf4175-3a25-4589-9425-9859bddf7a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369870404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.1369870404
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.4074929421
Short name T832
Test name
Test status
Simulation time 901778100 ps
CPU time 917.88 seconds
Started Jun 11 03:01:56 PM PDT 24
Finished Jun 11 03:17:15 PM PDT 24
Peak memory 270632 kb
Host smart-6b192f2e-bdcd-4e02-b59c-b19697d78ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074929421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.4074929421
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2683308089
Short name T39
Test name
Test status
Simulation time 3294261000 ps
CPU time 38.56 seconds
Started Jun 11 03:02:30 PM PDT 24
Finished Jun 11 03:03:10 PM PDT 24
Peak memory 263252 kb
Host smart-e9d14d0d-6d6b-48de-81bb-2fef000b055f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683308089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2683308089
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2624188852
Short name T87
Test name
Test status
Simulation time 50869725900 ps
CPU time 4288.07 seconds
Started Jun 11 03:02:00 PM PDT 24
Finished Jun 11 04:13:30 PM PDT 24
Peak memory 265560 kb
Host smart-5d6f9144-ec0f-40be-b8c7-f5944a85f6d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624188852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2624188852
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3617501512
Short name T861
Test name
Test status
Simulation time 1486983673500 ps
CPU time 2428.27 seconds
Started Jun 11 03:01:49 PM PDT 24
Finished Jun 11 03:42:19 PM PDT 24
Peak memory 264316 kb
Host smart-baf88e69-a276-4713-bb9c-7e8f22ce4ecf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617501512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3617501512
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.815478036
Short name T426
Test name
Test status
Simulation time 67011600 ps
CPU time 113.24 seconds
Started Jun 11 03:01:49 PM PDT 24
Finished Jun 11 03:03:43 PM PDT 24
Peak memory 265552 kb
Host smart-2903542e-9ee6-4a50-be14-ae1a42e00e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815478036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.815478036
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.808168335
Short name T857
Test name
Test status
Simulation time 10012635500 ps
CPU time 322.29 seconds
Started Jun 11 03:02:36 PM PDT 24
Finished Jun 11 03:07:59 PM PDT 24
Peak memory 309900 kb
Host smart-203346c2-98ea-4cf5-8f17-b4d6fdffbded
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808168335 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.808168335
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.307028594
Short name T878
Test name
Test status
Simulation time 14682100 ps
CPU time 13.34 seconds
Started Jun 11 03:02:34 PM PDT 24
Finished Jun 11 03:02:49 PM PDT 24
Peak memory 265240 kb
Host smart-4a2d5464-ec7d-40ee-af66-ae123d438461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307028594 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.307028594
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.1260835855
Short name T575
Test name
Test status
Simulation time 160193053600 ps
CPU time 881.54 seconds
Started Jun 11 03:01:48 PM PDT 24
Finished Jun 11 03:16:30 PM PDT 24
Peak memory 264136 kb
Host smart-e372a768-67b3-482e-891a-d804c5e5bb4e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260835855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.1260835855
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1539251453
Short name T413
Test name
Test status
Simulation time 18601082200 ps
CPU time 267.49 seconds
Started Jun 11 03:01:49 PM PDT 24
Finished Jun 11 03:06:17 PM PDT 24
Peak memory 263340 kb
Host smart-2a1a4f06-4b9c-4ec9-a005-2c1d65fd36ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539251453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1539251453
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.1715640994
Short name T794
Test name
Test status
Simulation time 6175448300 ps
CPU time 194.82 seconds
Started Jun 11 03:02:22 PM PDT 24
Finished Jun 11 03:05:39 PM PDT 24
Peak memory 284936 kb
Host smart-afc53eaa-097f-41f9-9dac-58818d582a6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715640994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.1715640994
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1119177893
Short name T564
Test name
Test status
Simulation time 80400337900 ps
CPU time 210.7 seconds
Started Jun 11 03:02:30 PM PDT 24
Finished Jun 11 03:06:02 PM PDT 24
Peak memory 265484 kb
Host smart-b6322f3b-daa4-419a-b9ce-9b031a412ba7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111
9177893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1119177893
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.830736925
Short name T102
Test name
Test status
Simulation time 1944315100 ps
CPU time 63.26 seconds
Started Jun 11 03:02:10 PM PDT 24
Finished Jun 11 03:03:14 PM PDT 24
Peak memory 260736 kb
Host smart-d1220647-c43c-4ad9-ad64-50d5eb3488b3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830736925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.830736925
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3291529721
Short name T747
Test name
Test status
Simulation time 25781500 ps
CPU time 13.28 seconds
Started Jun 11 03:02:37 PM PDT 24
Finished Jun 11 03:02:51 PM PDT 24
Peak memory 260200 kb
Host smart-f45ade3b-9cce-4fda-8afb-592ecd524643
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291529721 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3291529721
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.806069358
Short name T827
Test name
Test status
Simulation time 4280840000 ps
CPU time 72.14 seconds
Started Jun 11 03:02:08 PM PDT 24
Finished Jun 11 03:03:21 PM PDT 24
Peak memory 260940 kb
Host smart-7a3da0f6-2c5b-455c-9e32-7f89e3b85014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806069358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.806069358
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.3615004429
Short name T104
Test name
Test status
Simulation time 2720237400 ps
CPU time 230.59 seconds
Started Jun 11 03:01:49 PM PDT 24
Finished Jun 11 03:05:41 PM PDT 24
Peak memory 265516 kb
Host smart-3cd6f3d8-75f5-4e23-aa76-66dcaefd0701
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615004429 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.3615004429
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.2898934248
Short name T645
Test name
Test status
Simulation time 60374400 ps
CPU time 130.71 seconds
Started Jun 11 03:01:50 PM PDT 24
Finished Jun 11 03:04:01 PM PDT 24
Peak memory 265436 kb
Host smart-bc826bc3-1f75-43e3-b4de-298b29b8dbc3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898934248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.2898934248
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.3499397565
Short name T568
Test name
Test status
Simulation time 2029216200 ps
CPU time 190.57 seconds
Started Jun 11 03:02:21 PM PDT 24
Finished Jun 11 03:05:34 PM PDT 24
Peak memory 295496 kb
Host smart-edca06ea-3ba6-4b57-b455-bebdec6077ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499397565 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.3499397565
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1058948185
Short name T606
Test name
Test status
Simulation time 254817300 ps
CPU time 313.4 seconds
Started Jun 11 03:01:48 PM PDT 24
Finished Jun 11 03:07:03 PM PDT 24
Peak memory 263316 kb
Host smart-1bd75f8d-f3e8-4da1-80ef-1b96f32f648c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058948185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1058948185
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.2873100077
Short name T1048
Test name
Test status
Simulation time 38301400 ps
CPU time 13.51 seconds
Started Jun 11 03:02:26 PM PDT 24
Finished Jun 11 03:02:41 PM PDT 24
Peak memory 259252 kb
Host smart-edcc7d30-b1ca-4a0a-99f9-eab6827c6b09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873100077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.2873100077
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.4165967118
Short name T42
Test name
Test status
Simulation time 290432000 ps
CPU time 661.14 seconds
Started Jun 11 03:01:41 PM PDT 24
Finished Jun 11 03:12:43 PM PDT 24
Peak memory 284024 kb
Host smart-7790e5ac-8238-4af5-8fc1-476422ca92d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165967118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.4165967118
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2175328817
Short name T283
Test name
Test status
Simulation time 3058150200 ps
CPU time 112.47 seconds
Started Jun 11 03:01:51 PM PDT 24
Finished Jun 11 03:03:44 PM PDT 24
Peak memory 262956 kb
Host smart-1130be71-1e77-4b31-b149-75a655d82872
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2175328817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2175328817
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.2116138587
Short name T710
Test name
Test status
Simulation time 1354137100 ps
CPU time 36.52 seconds
Started Jun 11 03:02:27 PM PDT 24
Finished Jun 11 03:03:05 PM PDT 24
Peak memory 278128 kb
Host smart-707bff3f-1f1b-4b33-a110-d596c430ef26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116138587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.2116138587
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3706221309
Short name T40
Test name
Test status
Simulation time 19578700 ps
CPU time 22.71 seconds
Started Jun 11 03:02:18 PM PDT 24
Finished Jun 11 03:02:42 PM PDT 24
Peak memory 265728 kb
Host smart-9042e5fa-b765-44b5-b310-846f73aa03d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706221309 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3706221309
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.3832068021
Short name T693
Test name
Test status
Simulation time 31116600 ps
CPU time 21.19 seconds
Started Jun 11 03:02:19 PM PDT 24
Finished Jun 11 03:02:41 PM PDT 24
Peak memory 265684 kb
Host smart-d3b23f06-41f0-4655-93fe-de09d227cc2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832068021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.3832068021
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.277317529
Short name T695
Test name
Test status
Simulation time 578093100 ps
CPU time 129.94 seconds
Started Jun 11 03:02:19 PM PDT 24
Finished Jun 11 03:04:30 PM PDT 24
Peak memory 282268 kb
Host smart-bbdf21e7-6a69-4979-a32e-8a1d25aea518
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277317529 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_ro.277317529
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2288866568
Short name T1070
Test name
Test status
Simulation time 6356715900 ps
CPU time 137.24 seconds
Started Jun 11 03:02:21 PM PDT 24
Finished Jun 11 03:04:41 PM PDT 24
Peak memory 282248 kb
Host smart-6d57a9e8-516e-436f-8763-d2c3ad0212b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2288866568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2288866568
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.531752467
Short name T508
Test name
Test status
Simulation time 572226000 ps
CPU time 150.46 seconds
Started Jun 11 03:02:21 PM PDT 24
Finished Jun 11 03:04:54 PM PDT 24
Peak memory 282248 kb
Host smart-5c30cbf7-546d-484a-bf39-b9c8dec4dc6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531752467 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.531752467
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.740407901
Short name T76
Test name
Test status
Simulation time 12984487300 ps
CPU time 645.53 seconds
Started Jun 11 03:02:18 PM PDT 24
Finished Jun 11 03:13:06 PM PDT 24
Peak memory 314992 kb
Host smart-6e35c03d-1b20-4dcf-a3f7-cdafbf2d02d4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740407901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_rw.740407901
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.3326533354
Short name T766
Test name
Test status
Simulation time 139264900 ps
CPU time 31.51 seconds
Started Jun 11 03:02:25 PM PDT 24
Finished Jun 11 03:02:58 PM PDT 24
Peak memory 277480 kb
Host smart-9fac265a-3218-4c44-a5a6-fc0feb846c93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326533354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.3326533354
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2252841244
Short name T1003
Test name
Test status
Simulation time 123437300 ps
CPU time 28.51 seconds
Started Jun 11 03:02:27 PM PDT 24
Finished Jun 11 03:02:57 PM PDT 24
Peak memory 267924 kb
Host smart-8d66194d-6a86-48b9-b073-495465f97113
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252841244 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2252841244
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.3971629222
Short name T509
Test name
Test status
Simulation time 1193741100 ps
CPU time 67.35 seconds
Started Jun 11 03:02:25 PM PDT 24
Finished Jun 11 03:03:34 PM PDT 24
Peak memory 263924 kb
Host smart-4fbbd9e0-cb33-4e24-9a0b-ff1868fc637b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971629222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3971629222
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2468031654
Short name T577
Test name
Test status
Simulation time 986229500 ps
CPU time 107.67 seconds
Started Jun 11 03:02:21 PM PDT 24
Finished Jun 11 03:04:11 PM PDT 24
Peak memory 265352 kb
Host smart-8402535c-1c77-4d68-97bd-c03f69099846
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468031654 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2468031654
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.1536065764
Short name T892
Test name
Test status
Simulation time 2480828000 ps
CPU time 104.1 seconds
Started Jun 11 03:02:20 PM PDT 24
Finished Jun 11 03:04:06 PM PDT 24
Peak memory 276952 kb
Host smart-b200bc25-92c5-496b-8480-c57d1dd57066
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536065764 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.1536065764
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.852083472
Short name T243
Test name
Test status
Simulation time 136423300 ps
CPU time 97.04 seconds
Started Jun 11 03:01:40 PM PDT 24
Finished Jun 11 03:03:19 PM PDT 24
Peak memory 277168 kb
Host smart-92759f59-96b6-4b49-87a9-bfefb5649192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852083472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.852083472
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.2402827705
Short name T487
Test name
Test status
Simulation time 27736200 ps
CPU time 25.74 seconds
Started Jun 11 03:01:40 PM PDT 24
Finished Jun 11 03:02:07 PM PDT 24
Peak memory 259980 kb
Host smart-5b04ba84-48af-42af-ac29-388bdf129f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402827705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2402827705
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.3245982628
Short name T496
Test name
Test status
Simulation time 240483900 ps
CPU time 243.58 seconds
Started Jun 11 03:02:29 PM PDT 24
Finished Jun 11 03:06:34 PM PDT 24
Peak memory 274696 kb
Host smart-958afe2d-4d5c-41a2-b733-07b36819be6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245982628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.3245982628
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.727152392
Short name T491
Test name
Test status
Simulation time 23860800 ps
CPU time 24.79 seconds
Started Jun 11 03:01:41 PM PDT 24
Finished Jun 11 03:02:07 PM PDT 24
Peak memory 262708 kb
Host smart-1af89484-1608-4916-b5f1-eb0e2ff4840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727152392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.727152392
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.3958214947
Short name T1057
Test name
Test status
Simulation time 3330714800 ps
CPU time 179.84 seconds
Started Jun 11 03:02:17 PM PDT 24
Finished Jun 11 03:05:18 PM PDT 24
Peak memory 265696 kb
Host smart-d4237984-7c07-4ad8-b9ff-a8dd30afd213
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958214947 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.3958214947
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1574478708
Short name T807
Test name
Test status
Simulation time 38553400 ps
CPU time 13.7 seconds
Started Jun 11 03:13:00 PM PDT 24
Finished Jun 11 03:13:15 PM PDT 24
Peak memory 258612 kb
Host smart-176bc1c8-0309-4c96-838a-6fd624fd6e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574478708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1574478708
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2191408182
Short name T448
Test name
Test status
Simulation time 16098100 ps
CPU time 13.55 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:13:14 PM PDT 24
Peak memory 275084 kb
Host smart-3df5ddbd-fdaa-42b7-82e5-f17ddfeacc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191408182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2191408182
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2277405537
Short name T279
Test name
Test status
Simulation time 15998900 ps
CPU time 21.03 seconds
Started Jun 11 03:13:04 PM PDT 24
Finished Jun 11 03:13:26 PM PDT 24
Peak memory 274032 kb
Host smart-f8008d95-a4b0-4b3f-9ed3-1f596871732d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277405537 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2277405537
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1610301026
Short name T742
Test name
Test status
Simulation time 14431918400 ps
CPU time 63.92 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:14:04 PM PDT 24
Peak memory 263380 kb
Host smart-916dda04-1a04-4931-9b76-0a819666035c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610301026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1610301026
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.913334184
Short name T945
Test name
Test status
Simulation time 1222339600 ps
CPU time 160.45 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:15:41 PM PDT 24
Peak memory 285568 kb
Host smart-4ea9f8fd-310f-4c30-bfac-7c4c64fbb4f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913334184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas
h_ctrl_intr_rd.913334184
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3369223891
Short name T355
Test name
Test status
Simulation time 161005193200 ps
CPU time 339.59 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:18:40 PM PDT 24
Peak memory 291368 kb
Host smart-d2571c3b-a0ec-4baa-841e-88fabd007a01
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369223891 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3369223891
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1579480066
Short name T789
Test name
Test status
Simulation time 130897200 ps
CPU time 109.71 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:14:50 PM PDT 24
Peak memory 265124 kb
Host smart-65c61a24-bc61-4aef-8dac-a0471d7b3cda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579480066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1579480066
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2255361940
Short name T51
Test name
Test status
Simulation time 60956900 ps
CPU time 30.53 seconds
Started Jun 11 03:12:59 PM PDT 24
Finished Jun 11 03:13:31 PM PDT 24
Peak memory 275660 kb
Host smart-dfea6f08-dc18-443d-ad6a-b693a8e65c7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255361940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2255361940
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3048097375
Short name T863
Test name
Test status
Simulation time 60915500 ps
CPU time 30.67 seconds
Started Jun 11 03:12:58 PM PDT 24
Finished Jun 11 03:13:30 PM PDT 24
Peak memory 268156 kb
Host smart-576858ce-9d44-4a95-a212-2893844f7ec2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048097375 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3048097375
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.284551554
Short name T663
Test name
Test status
Simulation time 3334573600 ps
CPU time 80.09 seconds
Started Jun 11 03:13:01 PM PDT 24
Finished Jun 11 03:14:22 PM PDT 24
Peak memory 264968 kb
Host smart-cc87dc44-6cc1-4f90-8c2d-93f37002ddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284551554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.284551554
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3712638276
Short name T860
Test name
Test status
Simulation time 77215000 ps
CPU time 215.88 seconds
Started Jun 11 03:13:01 PM PDT 24
Finished Jun 11 03:16:38 PM PDT 24
Peak memory 280044 kb
Host smart-817d8696-8948-484a-ab87-79cb0d9b938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712638276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3712638276
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.317275079
Short name T101
Test name
Test status
Simulation time 58064800 ps
CPU time 13.77 seconds
Started Jun 11 03:13:09 PM PDT 24
Finished Jun 11 03:13:24 PM PDT 24
Peak memory 265520 kb
Host smart-a04e8545-b12c-490a-927d-f5d88c359af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317275079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.317275079
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3673582255
Short name T852
Test name
Test status
Simulation time 21671800 ps
CPU time 15.75 seconds
Started Jun 11 03:13:11 PM PDT 24
Finished Jun 11 03:13:28 PM PDT 24
Peak memory 275272 kb
Host smart-176e8a02-f5c5-486f-9c8b-839036c60f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673582255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3673582255
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1813653867
Short name T764
Test name
Test status
Simulation time 37833800 ps
CPU time 22.13 seconds
Started Jun 11 03:13:09 PM PDT 24
Finished Jun 11 03:13:31 PM PDT 24
Peak memory 273944 kb
Host smart-0b942864-8922-45fc-bdef-19f1c55b55f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813653867 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1813653867
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1449047278
Short name T853
Test name
Test status
Simulation time 3687524700 ps
CPU time 232.94 seconds
Started Jun 11 03:13:10 PM PDT 24
Finished Jun 11 03:17:04 PM PDT 24
Peak memory 263388 kb
Host smart-5ceb4eca-995d-4397-b76d-acdd06cfa3e4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449047278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.1449047278
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1187163197
Short name T596
Test name
Test status
Simulation time 1147989800 ps
CPU time 155.68 seconds
Started Jun 11 03:13:09 PM PDT 24
Finished Jun 11 03:15:46 PM PDT 24
Peak memory 294508 kb
Host smart-0dfe79f0-6f4d-442c-bac6-b1df6ecc36a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187163197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1187163197
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.435390809
Short name T941
Test name
Test status
Simulation time 18400019800 ps
CPU time 210.85 seconds
Started Jun 11 03:13:07 PM PDT 24
Finished Jun 11 03:16:39 PM PDT 24
Peak memory 291356 kb
Host smart-f6e59bc5-a97e-4dc3-b50d-481a0a0ceaf1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435390809 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.435390809
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.1204721331
Short name T130
Test name
Test status
Simulation time 40673700 ps
CPU time 131.96 seconds
Started Jun 11 03:13:08 PM PDT 24
Finished Jun 11 03:15:21 PM PDT 24
Peak memory 265448 kb
Host smart-5223fa33-2889-4320-9574-4c65610f9eb8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204721331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.1204721331
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.207117575
Short name T1028
Test name
Test status
Simulation time 64357200 ps
CPU time 30.35 seconds
Started Jun 11 03:13:09 PM PDT 24
Finished Jun 11 03:13:40 PM PDT 24
Peak memory 275660 kb
Host smart-ebb99abd-7f08-4629-b9e1-ef7025196bc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207117575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.207117575
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2405896156
Short name T607
Test name
Test status
Simulation time 28965200 ps
CPU time 28.41 seconds
Started Jun 11 03:13:10 PM PDT 24
Finished Jun 11 03:13:40 PM PDT 24
Peak memory 267824 kb
Host smart-aedb78bb-0f21-490e-8396-9c2e18ca6188
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405896156 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2405896156
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.3181508736
Short name T648
Test name
Test status
Simulation time 24711000 ps
CPU time 51.82 seconds
Started Jun 11 03:13:01 PM PDT 24
Finished Jun 11 03:13:53 PM PDT 24
Peak memory 271452 kb
Host smart-fcf0d55d-5d27-47fc-be1f-61c4927eb35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181508736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3181508736
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2959231872
Short name T609
Test name
Test status
Simulation time 55679100 ps
CPU time 13.68 seconds
Started Jun 11 03:13:20 PM PDT 24
Finished Jun 11 03:13:34 PM PDT 24
Peak memory 258564 kb
Host smart-cb69a76a-30b6-4de8-a7d8-fbe2e9ba811b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959231872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2959231872
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2966834466
Short name T951
Test name
Test status
Simulation time 153259500 ps
CPU time 13.57 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:13:34 PM PDT 24
Peak memory 275084 kb
Host smart-393702c6-a1bb-4c22-b457-3de7a4a84132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966834466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2966834466
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3041857894
Short name T83
Test name
Test status
Simulation time 20932700 ps
CPU time 20.18 seconds
Started Jun 11 03:13:21 PM PDT 24
Finished Jun 11 03:13:42 PM PDT 24
Peak memory 273952 kb
Host smart-206d6121-7842-4bec-a746-f7d6e6a144d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041857894 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3041857894
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1003723699
Short name T683
Test name
Test status
Simulation time 9659233800 ps
CPU time 179.52 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:16:19 PM PDT 24
Peak memory 262928 kb
Host smart-9485c9ba-6e9b-4e36-83bf-601f84fea057
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003723699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.1003723699
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2881876018
Short name T1079
Test name
Test status
Simulation time 513726700 ps
CPU time 127.12 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 294496 kb
Host smart-ba3a5339-e883-4731-9e44-00eb0f266e38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881876018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2881876018
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2429148817
Short name T840
Test name
Test status
Simulation time 27554746600 ps
CPU time 142.45 seconds
Started Jun 11 03:13:20 PM PDT 24
Finished Jun 11 03:15:43 PM PDT 24
Peak memory 293380 kb
Host smart-6d2b60e5-3435-47c0-aa39-e0de04b95d3e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429148817 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2429148817
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.125803600
Short name T720
Test name
Test status
Simulation time 144514500 ps
CPU time 131.75 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:15:32 PM PDT 24
Peak memory 260476 kb
Host smart-29382086-c733-4633-8a2e-07c7643cb3fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125803600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.125803600
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2406543691
Short name T955
Test name
Test status
Simulation time 27947100 ps
CPU time 30.69 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:13:51 PM PDT 24
Peak memory 275844 kb
Host smart-f6d86693-58ab-49c4-b617-eb3331b3709d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406543691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2406543691
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.2056509884
Short name T1039
Test name
Test status
Simulation time 113356700 ps
CPU time 31.07 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:13:50 PM PDT 24
Peak memory 275228 kb
Host smart-9f11f220-4c07-41dd-bdd4-4c994636ef26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056509884 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2056509884
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.783975131
Short name T437
Test name
Test status
Simulation time 4489081100 ps
CPU time 84.67 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:14:45 PM PDT 24
Peak memory 263916 kb
Host smart-0106eacf-b318-4896-a35d-4e8d2781ff12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783975131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.783975131
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.965042671
Short name T377
Test name
Test status
Simulation time 37197800 ps
CPU time 51.75 seconds
Started Jun 11 03:13:21 PM PDT 24
Finished Jun 11 03:14:13 PM PDT 24
Peak memory 271380 kb
Host smart-6da340eb-3005-47d6-ba85-bcaa5c61c252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965042671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.965042671
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.794512180
Short name T458
Test name
Test status
Simulation time 120202300 ps
CPU time 14.39 seconds
Started Jun 11 03:13:28 PM PDT 24
Finished Jun 11 03:13:43 PM PDT 24
Peak memory 258536 kb
Host smart-1bb11ebf-f6fc-4c03-971b-8546c2d68c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794512180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.794512180
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.3750786186
Short name T1042
Test name
Test status
Simulation time 76405400 ps
CPU time 13.61 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:13:44 PM PDT 24
Peak memory 275140 kb
Host smart-688a5014-86c8-4821-8c37-659b102edd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750786186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3750786186
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4200279291
Short name T633
Test name
Test status
Simulation time 39347688200 ps
CPU time 233.08 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:17:13 PM PDT 24
Peak memory 263416 kb
Host smart-328fe0f6-f182-4f02-9031-9e7169d127b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200279291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.4200279291
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2549764790
Short name T350
Test name
Test status
Simulation time 2828180400 ps
CPU time 127.08 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:15:26 PM PDT 24
Peak memory 285648 kb
Host smart-476ed502-158f-464f-a503-9b836d257e5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549764790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2549764790
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3007918352
Short name T534
Test name
Test status
Simulation time 13238124900 ps
CPU time 314.6 seconds
Started Jun 11 03:13:19 PM PDT 24
Finished Jun 11 03:18:35 PM PDT 24
Peak memory 291352 kb
Host smart-2630cddf-d002-4d93-830b-b693903aa43e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007918352 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3007918352
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1540023773
Short name T547
Test name
Test status
Simulation time 75043400 ps
CPU time 130.81 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:15:29 PM PDT 24
Peak memory 261408 kb
Host smart-163acae6-0e45-4712-828d-4492b1805a70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540023773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1540023773
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1747024665
Short name T1013
Test name
Test status
Simulation time 28385600 ps
CPU time 30.94 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:14:01 PM PDT 24
Peak memory 275776 kb
Host smart-15b37272-bfac-49d0-8c65-4d69c437e9f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747024665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1747024665
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2571325694
Short name T814
Test name
Test status
Simulation time 67816600 ps
CPU time 28.82 seconds
Started Jun 11 03:13:27 PM PDT 24
Finished Jun 11 03:13:56 PM PDT 24
Peak memory 275220 kb
Host smart-19656f44-5760-4ee6-bee2-9125b2a9fd2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571325694 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2571325694
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.84888452
Short name T34
Test name
Test status
Simulation time 1929938100 ps
CPU time 77.88 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:14:48 PM PDT 24
Peak memory 263272 kb
Host smart-35504241-360b-49a0-86a5-fcae446ca8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84888452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.84888452
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.134157438
Short name T722
Test name
Test status
Simulation time 26805700 ps
CPU time 147.5 seconds
Started Jun 11 03:13:18 PM PDT 24
Finished Jun 11 03:15:46 PM PDT 24
Peak memory 270084 kb
Host smart-a8c61860-8d2f-441a-9320-82dc95818000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134157438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.134157438
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.4137562466
Short name T477
Test name
Test status
Simulation time 163871400 ps
CPU time 13.65 seconds
Started Jun 11 03:13:39 PM PDT 24
Finished Jun 11 03:13:55 PM PDT 24
Peak memory 265592 kb
Host smart-9c0bef14-08a5-4816-82f3-49e14637e836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137562466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
4137562466
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1897680792
Short name T493
Test name
Test status
Simulation time 15377600 ps
CPU time 16.33 seconds
Started Jun 11 03:13:38 PM PDT 24
Finished Jun 11 03:13:57 PM PDT 24
Peak memory 274980 kb
Host smart-91c6454d-e3f2-4836-84cb-bbe0856cc2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897680792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1897680792
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2240873208
Short name T372
Test name
Test status
Simulation time 11302000 ps
CPU time 20.51 seconds
Started Jun 11 03:13:28 PM PDT 24
Finished Jun 11 03:13:50 PM PDT 24
Peak memory 273932 kb
Host smart-70d3f663-be50-4360-ba6a-88ae307b3cc3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240873208 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2240873208
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1668406518
Short name T553
Test name
Test status
Simulation time 949541200 ps
CPU time 51.85 seconds
Started Jun 11 03:13:28 PM PDT 24
Finished Jun 11 03:14:20 PM PDT 24
Peak memory 263416 kb
Host smart-c484413d-f908-4289-a218-0c3af532fc79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668406518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1668406518
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2735775533
Short name T252
Test name
Test status
Simulation time 6827821000 ps
CPU time 217.01 seconds
Started Jun 11 03:13:28 PM PDT 24
Finished Jun 11 03:17:07 PM PDT 24
Peak memory 285092 kb
Host smart-a2b2f37d-a15d-410e-87fb-d99f5dfc324d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735775533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2735775533
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2490995126
Short name T351
Test name
Test status
Simulation time 53542597400 ps
CPU time 321.05 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:18:52 PM PDT 24
Peak memory 285332 kb
Host smart-4a528b01-fc39-47b1-8b2d-25f70c03a92a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490995126 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.2490995126
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.2551494756
Short name T52
Test name
Test status
Simulation time 111513600 ps
CPU time 30.96 seconds
Started Jun 11 03:13:31 PM PDT 24
Finished Jun 11 03:14:02 PM PDT 24
Peak memory 275664 kb
Host smart-1b4adab8-6dce-400e-bae3-25a304531af0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551494756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.2551494756
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.3182875868
Short name T325
Test name
Test status
Simulation time 143007800 ps
CPU time 31.39 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:14:02 PM PDT 24
Peak memory 275336 kb
Host smart-3e91ca9f-9ebd-421a-a708-127cc235309e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182875868 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.3182875868
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.610429297
Short name T867
Test name
Test status
Simulation time 2406894200 ps
CPU time 70.66 seconds
Started Jun 11 03:13:29 PM PDT 24
Finished Jun 11 03:14:41 PM PDT 24
Peak memory 263980 kb
Host smart-61c7c828-6f32-42d2-9654-1c5075ea46b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610429297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.610429297
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1981567105
Short name T518
Test name
Test status
Simulation time 78041700 ps
CPU time 74.5 seconds
Started Jun 11 03:13:28 PM PDT 24
Finished Jun 11 03:14:44 PM PDT 24
Peak memory 276752 kb
Host smart-a89f5b23-1953-4a63-9c1a-1f641602bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981567105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1981567105
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.2941934187
Short name T659
Test name
Test status
Simulation time 30297500 ps
CPU time 13.59 seconds
Started Jun 11 03:13:40 PM PDT 24
Finished Jun 11 03:13:56 PM PDT 24
Peak memory 258488 kb
Host smart-75175ccd-f9c1-4468-ba56-6e206180b911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941934187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
2941934187
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2033340803
Short name T549
Test name
Test status
Simulation time 28627300 ps
CPU time 15.82 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:13:55 PM PDT 24
Peak memory 284432 kb
Host smart-c4257327-832b-4291-bda1-4e67a534723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033340803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2033340803
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.4189156963
Short name T142
Test name
Test status
Simulation time 28140400 ps
CPU time 21.5 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:14:01 PM PDT 24
Peak memory 274100 kb
Host smart-13ce9505-05ef-4d32-8d73-804a6281c6bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189156963 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.4189156963
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3909328300
Short name T983
Test name
Test status
Simulation time 9278658600 ps
CPU time 74.09 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:14:53 PM PDT 24
Peak memory 263504 kb
Host smart-db10f7c5-cb95-43c5-ac16-9432a5e785f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909328300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3909328300
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.2185687497
Short name T669
Test name
Test status
Simulation time 5523232600 ps
CPU time 198.75 seconds
Started Jun 11 03:13:38 PM PDT 24
Finished Jun 11 03:16:59 PM PDT 24
Peak memory 285148 kb
Host smart-297a9b9b-f2cc-47b4-b9c3-835c3d83f29a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185687497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.2185687497
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.28927569
Short name T344
Test name
Test status
Simulation time 23782787900 ps
CPU time 158.2 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:16:17 PM PDT 24
Peak memory 294408 kb
Host smart-4acce591-68b8-4512-928f-d8cb494b4478
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927569 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.28927569
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.3625648780
Short name T994
Test name
Test status
Simulation time 274606900 ps
CPU time 110.18 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:15:29 PM PDT 24
Peak memory 260416 kb
Host smart-cce38ac3-62f4-4fdd-8075-72181057bb1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625648780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.3625648780
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3647724288
Short name T331
Test name
Test status
Simulation time 36697100 ps
CPU time 30.52 seconds
Started Jun 11 03:13:38 PM PDT 24
Finished Jun 11 03:14:11 PM PDT 24
Peak memory 275840 kb
Host smart-69240252-8094-434f-a0cc-43923e099cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647724288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3647724288
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1231583198
Short name T856
Test name
Test status
Simulation time 155700300 ps
CPU time 31.4 seconds
Started Jun 11 03:13:38 PM PDT 24
Finished Jun 11 03:14:12 PM PDT 24
Peak memory 268000 kb
Host smart-d4e61487-67ef-4053-8151-494c0338047b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231583198 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1231583198
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2145479991
Short name T1007
Test name
Test status
Simulation time 451690000 ps
CPU time 67.25 seconds
Started Jun 11 03:13:37 PM PDT 24
Finished Jun 11 03:14:45 PM PDT 24
Peak memory 263940 kb
Host smart-b6afd56f-d44f-4aa4-9aca-13c5294488ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145479991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2145479991
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3352303260
Short name T741
Test name
Test status
Simulation time 252353200 ps
CPU time 170.83 seconds
Started Jun 11 03:13:38 PM PDT 24
Finished Jun 11 03:16:31 PM PDT 24
Peak memory 277520 kb
Host smart-511c0b5d-0aab-4552-a0eb-9ef84d2728a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352303260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3352303260
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1509610986
Short name T999
Test name
Test status
Simulation time 36543300 ps
CPU time 13.82 seconds
Started Jun 11 03:13:46 PM PDT 24
Finished Jun 11 03:14:01 PM PDT 24
Peak memory 258452 kb
Host smart-e39f1b1c-6bbe-4b38-bf02-b70bb960f087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509610986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1509610986
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.958978447
Short name T1078
Test name
Test status
Simulation time 15597200 ps
CPU time 15.62 seconds
Started Jun 11 03:13:45 PM PDT 24
Finished Jun 11 03:14:02 PM PDT 24
Peak memory 275136 kb
Host smart-07591d80-2bda-45b2-afd6-15af48ad7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958978447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.958978447
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1863484262
Short name T379
Test name
Test status
Simulation time 24902800 ps
CPU time 21.75 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:14:10 PM PDT 24
Peak memory 273952 kb
Host smart-2aa81644-173c-4bc3-9120-9b26c8fd4f7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863484262 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1863484262
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.739456718
Short name T615
Test name
Test status
Simulation time 2871871000 ps
CPU time 72.17 seconds
Started Jun 11 03:13:46 PM PDT 24
Finished Jun 11 03:14:59 PM PDT 24
Peak memory 263480 kb
Host smart-e22e1e25-487a-458f-ada0-1ed450939acb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739456718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h
w_sec_otp.739456718
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.1684340344
Short name T746
Test name
Test status
Simulation time 2643339500 ps
CPU time 142.41 seconds
Started Jun 11 03:13:45 PM PDT 24
Finished Jun 11 03:16:08 PM PDT 24
Peak memory 295548 kb
Host smart-ed83560a-391d-4cd7-abfa-9e01e220cd5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684340344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.1684340344
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2787964146
Short name T1024
Test name
Test status
Simulation time 25034826800 ps
CPU time 292.35 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:18:40 PM PDT 24
Peak memory 285304 kb
Host smart-3416a1c5-bb7d-4eed-a4e6-02053251c626
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787964146 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2787964146
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2637381209
Short name T1063
Test name
Test status
Simulation time 205823400 ps
CPU time 132.22 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:16:00 PM PDT 24
Peak memory 260368 kb
Host smart-15303070-49ef-4273-b0d2-ef456fbd7b87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637381209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2637381209
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.4055957891
Short name T849
Test name
Test status
Simulation time 5707525100 ps
CPU time 66.62 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:14:55 PM PDT 24
Peak memory 263348 kb
Host smart-79a6e1af-57ff-4fb9-a7a7-9ed9af61d772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055957891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.4055957891
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2614472102
Short name T704
Test name
Test status
Simulation time 24014700 ps
CPU time 48.93 seconds
Started Jun 11 03:13:35 PM PDT 24
Finished Jun 11 03:14:25 PM PDT 24
Peak memory 271404 kb
Host smart-f94c976c-7b38-46a1-8ca7-e2ce16867cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614472102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2614472102
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.362690226
Short name T1066
Test name
Test status
Simulation time 28864400 ps
CPU time 14.12 seconds
Started Jun 11 03:13:57 PM PDT 24
Finished Jun 11 03:14:12 PM PDT 24
Peak memory 265628 kb
Host smart-15465a9e-76d9-4a39-b938-9409afeceffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362690226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.362690226
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1212109958
Short name T554
Test name
Test status
Simulation time 15146700 ps
CPU time 16 seconds
Started Jun 11 03:13:54 PM PDT 24
Finished Jun 11 03:14:11 PM PDT 24
Peak memory 275148 kb
Host smart-fe300ada-e1ae-4f16-b5ea-705111f90700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212109958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1212109958
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2579586870
Short name T199
Test name
Test status
Simulation time 18517100 ps
CPU time 21.01 seconds
Started Jun 11 03:13:55 PM PDT 24
Finished Jun 11 03:14:17 PM PDT 24
Peak memory 274104 kb
Host smart-29998fcd-3f36-47ad-8ad0-cc140ebf51a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579586870 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2579586870
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3543563122
Short name T315
Test name
Test status
Simulation time 6478545200 ps
CPU time 277.68 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:18:25 PM PDT 24
Peak memory 263424 kb
Host smart-62575076-fc09-472e-9579-1fef9d4f6cd5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543563122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.3543563122
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.2070509417
Short name T653
Test name
Test status
Simulation time 711684100 ps
CPU time 167.84 seconds
Started Jun 11 03:13:46 PM PDT 24
Finished Jun 11 03:16:35 PM PDT 24
Peak memory 293140 kb
Host smart-5518a09b-3d7e-42cf-aaf4-3946f15d58a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070509417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.2070509417
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.58353143
Short name T1033
Test name
Test status
Simulation time 51986510100 ps
CPU time 161.3 seconds
Started Jun 11 03:13:55 PM PDT 24
Finished Jun 11 03:16:38 PM PDT 24
Peak memory 294356 kb
Host smart-165927f3-ef2e-41e4-a26d-5d8a21a98001
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58353143 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.58353143
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.1462831131
Short name T915
Test name
Test status
Simulation time 75517100 ps
CPU time 134.26 seconds
Started Jun 11 03:13:45 PM PDT 24
Finished Jun 11 03:16:01 PM PDT 24
Peak memory 260708 kb
Host smart-e14a15cb-9c04-4d96-b57e-1a9c96da6f55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462831131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.1462831131
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2532661917
Short name T253
Test name
Test status
Simulation time 31136400 ps
CPU time 31.06 seconds
Started Jun 11 03:13:55 PM PDT 24
Finished Jun 11 03:14:27 PM PDT 24
Peak memory 275412 kb
Host smart-2e2a9e29-6573-473d-9193-0b4b233074bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532661917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2532661917
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2509038755
Short name T759
Test name
Test status
Simulation time 119817000 ps
CPU time 29.09 seconds
Started Jun 11 03:13:57 PM PDT 24
Finished Jun 11 03:14:27 PM PDT 24
Peak memory 275232 kb
Host smart-fd0f2365-d7dd-499d-aa99-9ba75c76f4d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509038755 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2509038755
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3194257823
Short name T843
Test name
Test status
Simulation time 2530130100 ps
CPU time 71.82 seconds
Started Jun 11 03:13:56 PM PDT 24
Finished Jun 11 03:15:09 PM PDT 24
Peak memory 264460 kb
Host smart-ab6ec6c2-a71d-43be-b114-3374a4350977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194257823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3194257823
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.384403983
Short name T908
Test name
Test status
Simulation time 50568700 ps
CPU time 97.61 seconds
Started Jun 11 03:13:47 PM PDT 24
Finished Jun 11 03:15:25 PM PDT 24
Peak memory 277332 kb
Host smart-424e3eb7-b658-43fd-a025-2208d61ebbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384403983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.384403983
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3823336098
Short name T451
Test name
Test status
Simulation time 148496500 ps
CPU time 13.64 seconds
Started Jun 11 03:14:02 PM PDT 24
Finished Jun 11 03:14:17 PM PDT 24
Peak memory 258588 kb
Host smart-b3f1c75f-ec87-40f5-87d7-f564742ac62d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823336098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3823336098
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.1813614577
Short name T1074
Test name
Test status
Simulation time 16484500 ps
CPU time 13.36 seconds
Started Jun 11 03:14:06 PM PDT 24
Finished Jun 11 03:14:20 PM PDT 24
Peak memory 275068 kb
Host smart-45fe8d4e-73ac-4d12-ae6f-7e7c867bb0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813614577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1813614577
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.1816357901
Short name T966
Test name
Test status
Simulation time 37805200 ps
CPU time 21.61 seconds
Started Jun 11 03:14:02 PM PDT 24
Finished Jun 11 03:14:24 PM PDT 24
Peak memory 273968 kb
Host smart-c0017cf9-87af-4574-997d-9e860738187f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816357901 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.1816357901
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.4054195143
Short name T1040
Test name
Test status
Simulation time 2457436700 ps
CPU time 162.34 seconds
Started Jun 11 03:13:59 PM PDT 24
Finished Jun 11 03:16:42 PM PDT 24
Peak memory 295512 kb
Host smart-f4263855-ebbe-4a3c-b97b-cb352bf3d4b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054195143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.4054195143
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.4024047637
Short name T8
Test name
Test status
Simulation time 23440580700 ps
CPU time 145.51 seconds
Started Jun 11 03:13:54 PM PDT 24
Finished Jun 11 03:16:21 PM PDT 24
Peak memory 292844 kb
Host smart-2a0902bf-a9f6-4d3b-aa90-d1a1fd8e2967
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024047637 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.4024047637
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1911626660
Short name T958
Test name
Test status
Simulation time 41222400 ps
CPU time 112.37 seconds
Started Jun 11 03:13:54 PM PDT 24
Finished Jun 11 03:15:47 PM PDT 24
Peak memory 265108 kb
Host smart-6b68f85e-01fc-42fe-86f5-812eb81723b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911626660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1911626660
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1120936355
Short name T466
Test name
Test status
Simulation time 29252200 ps
CPU time 31.57 seconds
Started Jun 11 03:13:56 PM PDT 24
Finished Jun 11 03:14:29 PM PDT 24
Peak memory 275768 kb
Host smart-559e6ed8-b651-4cfc-b25f-4cb2ac4e5e73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120936355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1120936355
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.2540137591
Short name T865
Test name
Test status
Simulation time 2139836600 ps
CPU time 74.44 seconds
Started Jun 11 03:14:02 PM PDT 24
Finished Jun 11 03:15:17 PM PDT 24
Peak memory 259864 kb
Host smart-b7f60504-1224-4445-a6d7-1b7efe6354f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540137591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2540137591
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.226675376
Short name T428
Test name
Test status
Simulation time 50164000 ps
CPU time 120.68 seconds
Started Jun 11 03:13:58 PM PDT 24
Finished Jun 11 03:15:59 PM PDT 24
Peak memory 276500 kb
Host smart-62e255eb-24b4-4642-9a83-71e9f3d8a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226675376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.226675376
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.2030446642
Short name T19
Test name
Test status
Simulation time 38958400 ps
CPU time 14.24 seconds
Started Jun 11 03:14:14 PM PDT 24
Finished Jun 11 03:14:30 PM PDT 24
Peak memory 265592 kb
Host smart-5e166c03-5356-4f8d-a440-a7a5d0633dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030446642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
2030446642
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3220163580
Short name T422
Test name
Test status
Simulation time 47891000 ps
CPU time 15.95 seconds
Started Jun 11 03:14:13 PM PDT 24
Finished Jun 11 03:14:31 PM PDT 24
Peak memory 275016 kb
Host smart-fc16307b-86fe-4b2e-bdc7-96c94725291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220163580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3220163580
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.915321685
Short name T1068
Test name
Test status
Simulation time 35245100 ps
CPU time 22.27 seconds
Started Jun 11 03:14:16 PM PDT 24
Finished Jun 11 03:14:40 PM PDT 24
Peak memory 273988 kb
Host smart-4000bea7-5ac6-4ced-a411-ad4626605e01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915321685 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.915321685
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1174226400
Short name T1018
Test name
Test status
Simulation time 26193961400 ps
CPU time 194.23 seconds
Started Jun 11 03:14:06 PM PDT 24
Finished Jun 11 03:17:21 PM PDT 24
Peak memory 285032 kb
Host smart-1cb02cb0-6e03-4304-9701-ce04c806c3cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174226400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1174226400
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2872616551
Short name T317
Test name
Test status
Simulation time 11808378300 ps
CPU time 130.68 seconds
Started Jun 11 03:14:06 PM PDT 24
Finished Jun 11 03:16:17 PM PDT 24
Peak memory 293288 kb
Host smart-80a95e59-a107-4a12-b109-4ebbc39cb869
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872616551 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2872616551
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.469277356
Short name T118
Test name
Test status
Simulation time 651745600 ps
CPU time 105.87 seconds
Started Jun 11 03:14:06 PM PDT 24
Finished Jun 11 03:15:52 PM PDT 24
Peak memory 261244 kb
Host smart-55d8bfe4-0b79-4ec8-9a72-d8fdb9b484ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469277356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ot
p_reset.469277356
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.4085846881
Short name T937
Test name
Test status
Simulation time 45140000 ps
CPU time 30.89 seconds
Started Jun 11 03:14:05 PM PDT 24
Finished Jun 11 03:14:36 PM PDT 24
Peak memory 275180 kb
Host smart-0ca446f6-9101-45c3-82e4-da7bca395892
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085846881 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.4085846881
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.307251587
Short name T403
Test name
Test status
Simulation time 778074000 ps
CPU time 60.81 seconds
Started Jun 11 03:14:14 PM PDT 24
Finished Jun 11 03:15:16 PM PDT 24
Peak memory 264904 kb
Host smart-3adab92b-1676-4f6a-91da-ae5b387767c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307251587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.307251587
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.316062827
Short name T910
Test name
Test status
Simulation time 64431300 ps
CPU time 76.87 seconds
Started Jun 11 03:14:02 PM PDT 24
Finished Jun 11 03:15:20 PM PDT 24
Peak memory 275696 kb
Host smart-30469603-4126-4d23-b574-4d70a974651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316062827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.316062827
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3894106985
Short name T730
Test name
Test status
Simulation time 59085500 ps
CPU time 13.74 seconds
Started Jun 11 03:03:55 PM PDT 24
Finished Jun 11 03:04:10 PM PDT 24
Peak memory 258628 kb
Host smart-0ed12429-8d56-4854-868f-b3c68fca7d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894106985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
894106985
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.154211408
Short name T235
Test name
Test status
Simulation time 21155500 ps
CPU time 13.73 seconds
Started Jun 11 03:03:45 PM PDT 24
Finished Jun 11 03:04:00 PM PDT 24
Peak memory 265724 kb
Host smart-7354f3c1-1152-484e-8d5d-5fd2d60ef075
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154211408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.154211408
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1222495320
Short name T1041
Test name
Test status
Simulation time 17409900 ps
CPU time 15.7 seconds
Started Jun 11 03:03:37 PM PDT 24
Finished Jun 11 03:03:54 PM PDT 24
Peak memory 275012 kb
Host smart-ae8a266e-bf64-461f-8f13-8b07a1338b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222495320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1222495320
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1329392236
Short name T697
Test name
Test status
Simulation time 122352200 ps
CPU time 105.79 seconds
Started Jun 11 03:03:30 PM PDT 24
Finished Jun 11 03:05:17 PM PDT 24
Peak memory 281560 kb
Host smart-4e23cc90-45ed-4ab6-abb4-f24ea7634411
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329392236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1329392236
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.4239257721
Short name T141
Test name
Test status
Simulation time 37081700 ps
CPU time 21.11 seconds
Started Jun 11 03:03:36 PM PDT 24
Finished Jun 11 03:03:58 PM PDT 24
Peak memory 274084 kb
Host smart-575a583d-516d-46e9-9621-5ae4afd52f23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239257721 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.4239257721
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2539862818
Short name T690
Test name
Test status
Simulation time 3821972400 ps
CPU time 565.26 seconds
Started Jun 11 03:02:52 PM PDT 24
Finished Jun 11 03:12:18 PM PDT 24
Peak memory 263620 kb
Host smart-98a52e81-bb69-43a5-b320-1a7c188dfe40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2539862818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2539862818
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.1948705247
Short name T251
Test name
Test status
Simulation time 33610703900 ps
CPU time 2219.86 seconds
Started Jun 11 03:03:10 PM PDT 24
Finished Jun 11 03:40:11 PM PDT 24
Peak memory 265012 kb
Host smart-d8309379-d335-4d73-bf86-1fb3f79113e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948705247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.1948705247
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.2166933146
Short name T960
Test name
Test status
Simulation time 731323600 ps
CPU time 2208.02 seconds
Started Jun 11 03:03:10 PM PDT 24
Finished Jun 11 03:39:59 PM PDT 24
Peak memory 263440 kb
Host smart-85ac1bda-793a-411b-b193-b6f288edbca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166933146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2166933146
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.4162996460
Short name T295
Test name
Test status
Simulation time 1362191500 ps
CPU time 853.86 seconds
Started Jun 11 03:03:09 PM PDT 24
Finished Jun 11 03:17:23 PM PDT 24
Peak memory 273740 kb
Host smart-055f783f-0e85-465d-98c6-46d85d237335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162996460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.4162996460
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2896391388
Short name T65
Test name
Test status
Simulation time 295400100 ps
CPU time 21.89 seconds
Started Jun 11 03:03:05 PM PDT 24
Finished Jun 11 03:03:28 PM PDT 24
Peak memory 262692 kb
Host smart-f1368126-b688-4897-afed-9ff95eca4290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896391388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2896391388
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.3894780016
Short name T949
Test name
Test status
Simulation time 3453319700 ps
CPU time 47.36 seconds
Started Jun 11 03:03:36 PM PDT 24
Finished Jun 11 03:04:25 PM PDT 24
Peak memory 265748 kb
Host smart-57add71c-8fe2-486a-aa17-b6ae9b31b05f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894780016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.3894780016
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.172238652
Short name T183
Test name
Test status
Simulation time 159599217300 ps
CPU time 2804.48 seconds
Started Jun 11 03:03:05 PM PDT 24
Finished Jun 11 03:49:51 PM PDT 24
Peak memory 263556 kb
Host smart-2cd1fb95-a1ba-40da-adf7-5015d7b61c94
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172238652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_full_mem_access.172238652
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2042845735
Short name T41
Test name
Test status
Simulation time 42735800 ps
CPU time 24.08 seconds
Started Jun 11 03:02:51 PM PDT 24
Finished Jun 11 03:03:16 PM PDT 24
Peak memory 265568 kb
Host smart-12cf8ea0-53c8-4508-8509-0477a1f36160
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042845735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2042845735
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1092273455
Short name T146
Test name
Test status
Simulation time 10012558800 ps
CPU time 149.95 seconds
Started Jun 11 03:03:54 PM PDT 24
Finished Jun 11 03:06:25 PM PDT 24
Peak memory 385888 kb
Host smart-94e9108a-8650-4177-aad5-5be4b46c6e27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092273455 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1092273455
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.338762310
Short name T354
Test name
Test status
Simulation time 14905500 ps
CPU time 13.35 seconds
Started Jun 11 03:03:45 PM PDT 24
Finished Jun 11 03:04:00 PM PDT 24
Peak memory 259784 kb
Host smart-b57657dc-4962-41e8-9a6e-88500907b26d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338762310 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.338762310
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2982600887
Short name T145
Test name
Test status
Simulation time 100160095900 ps
CPU time 902.76 seconds
Started Jun 11 03:02:54 PM PDT 24
Finished Jun 11 03:17:57 PM PDT 24
Peak memory 264400 kb
Host smart-5edaad4b-df99-4390-a74c-1c3e7465d86c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982600887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2982600887
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2429279311
Short name T699
Test name
Test status
Simulation time 4064239600 ps
CPU time 82.12 seconds
Started Jun 11 03:02:54 PM PDT 24
Finished Jun 11 03:04:17 PM PDT 24
Peak memory 263320 kb
Host smart-4acb4eb7-3b7a-4a6f-830d-41e0d22ede32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429279311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.2429279311
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.4211673979
Short name T254
Test name
Test status
Simulation time 15970363400 ps
CPU time 792.5 seconds
Started Jun 11 03:03:28 PM PDT 24
Finished Jun 11 03:16:42 PM PDT 24
Peak memory 339432 kb
Host smart-7c5ddf6e-5808-4020-a7b7-3fd23e63f13f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211673979 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.4211673979
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1324195850
Short name T618
Test name
Test status
Simulation time 4599776300 ps
CPU time 197.69 seconds
Started Jun 11 03:03:28 PM PDT 24
Finished Jun 11 03:06:47 PM PDT 24
Peak memory 285180 kb
Host smart-34d3c428-de60-41f8-b886-bf1374fc4acc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324195850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1324195850
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2668176284
Short name T685
Test name
Test status
Simulation time 29944940900 ps
CPU time 295.23 seconds
Started Jun 11 03:03:36 PM PDT 24
Finished Jun 11 03:08:32 PM PDT 24
Peak memory 292064 kb
Host smart-2dd5528d-1d5b-4b96-b7c0-f1392f2e7075
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668176284 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2668176284
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.2903424681
Short name T499
Test name
Test status
Simulation time 9907519800 ps
CPU time 77.77 seconds
Started Jun 11 03:03:37 PM PDT 24
Finished Jun 11 03:04:56 PM PDT 24
Peak memory 260264 kb
Host smart-8fca8964-7e84-4187-bf96-45394fc932a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903424681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.2903424681
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3160886190
Short name T732
Test name
Test status
Simulation time 102214753200 ps
CPU time 270.09 seconds
Started Jun 11 03:03:37 PM PDT 24
Finished Jun 11 03:08:08 PM PDT 24
Peak memory 260496 kb
Host smart-94aa9388-31ba-4fbe-9549-658c1eeb5336
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316
0886190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3160886190
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2620853533
Short name T1072
Test name
Test status
Simulation time 1956367100 ps
CPU time 87.11 seconds
Started Jun 11 03:03:10 PM PDT 24
Finished Jun 11 03:04:38 PM PDT 24
Peak memory 260720 kb
Host smart-85f11d5a-7f39-42f5-9fab-87f775634521
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620853533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2620853533
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2404509185
Short name T712
Test name
Test status
Simulation time 25517000 ps
CPU time 13.24 seconds
Started Jun 11 03:03:44 PM PDT 24
Finished Jun 11 03:03:59 PM PDT 24
Peak memory 265288 kb
Host smart-dece50a7-8f67-43a4-87de-1b9d76027669
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404509185 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2404509185
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.968310257
Short name T1076
Test name
Test status
Simulation time 31976126900 ps
CPU time 1040.18 seconds
Started Jun 11 03:03:04 PM PDT 24
Finished Jun 11 03:20:25 PM PDT 24
Peak memory 274964 kb
Host smart-15708565-611f-4967-b9b7-9f65cd1d9e92
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968310257 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.968310257
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2068983069
Short name T791
Test name
Test status
Simulation time 123139200 ps
CPU time 130.6 seconds
Started Jun 11 03:02:52 PM PDT 24
Finished Jun 11 03:05:04 PM PDT 24
Peak memory 260316 kb
Host smart-53031c6c-dea6-4794-9ef9-5f616dc7f6bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068983069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2068983069
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3386036887
Short name T47
Test name
Test status
Simulation time 24500800 ps
CPU time 13.7 seconds
Started Jun 11 03:03:46 PM PDT 24
Finished Jun 11 03:04:01 PM PDT 24
Peak memory 279720 kb
Host smart-e0e0e09a-bed2-43a4-9812-a5c415466fd8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3386036887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3386036887
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.4262569738
Short name T71
Test name
Test status
Simulation time 1637409400 ps
CPU time 359.65 seconds
Started Jun 11 03:02:42 PM PDT 24
Finished Jun 11 03:08:43 PM PDT 24
Peak memory 263448 kb
Host smart-fa18936a-4bc0-4de2-af26-812a9b136eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4262569738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.4262569738
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.3295575742
Short name T989
Test name
Test status
Simulation time 178612300 ps
CPU time 13.68 seconds
Started Jun 11 03:03:38 PM PDT 24
Finished Jun 11 03:03:52 PM PDT 24
Peak memory 265572 kb
Host smart-c2aba65f-8442-4821-a8c5-7d1a7679ebf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295575742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.3295575742
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.1670047918
Short name T504
Test name
Test status
Simulation time 128318400 ps
CPU time 392.27 seconds
Started Jun 11 03:02:43 PM PDT 24
Finished Jun 11 03:09:16 PM PDT 24
Peak memory 276820 kb
Host smart-41baca08-ea00-44ad-a126-6c29f0aee756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670047918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.1670047918
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2027661205
Short name T236
Test name
Test status
Simulation time 718494700 ps
CPU time 142.12 seconds
Started Jun 11 03:02:49 PM PDT 24
Finished Jun 11 03:05:12 PM PDT 24
Peak memory 262972 kb
Host smart-87b7d19a-801b-4d05-8b6e-d98a7b0dc87b
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2027661205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2027661205
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3215803689
Short name T889
Test name
Test status
Simulation time 216794300 ps
CPU time 35.19 seconds
Started Jun 11 03:03:41 PM PDT 24
Finished Jun 11 03:04:17 PM PDT 24
Peak memory 277068 kb
Host smart-0cb9ec54-f23f-49c4-a3e0-a8f569a7b0a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215803689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3215803689
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2872802666
Short name T587
Test name
Test status
Simulation time 46569600 ps
CPU time 22.98 seconds
Started Jun 11 03:03:23 PM PDT 24
Finished Jun 11 03:03:47 PM PDT 24
Peak memory 265760 kb
Host smart-d06487e4-011a-46f3-a8e5-8ee9fcabfa2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872802666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2872802666
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.2068495294
Short name T1038
Test name
Test status
Simulation time 627921200 ps
CPU time 136.49 seconds
Started Jun 11 03:03:22 PM PDT 24
Finished Jun 11 03:05:40 PM PDT 24
Peak memory 282132 kb
Host smart-824fb59d-fa45-4a8e-94b3-d8880d0398c4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068495294 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.2068495294
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2459251509
Short name T1035
Test name
Test status
Simulation time 1193468100 ps
CPU time 127.76 seconds
Started Jun 11 03:03:30 PM PDT 24
Finished Jun 11 03:05:40 PM PDT 24
Peak memory 282268 kb
Host smart-6e9f3e83-c101-47fa-8db2-ee4a39475309
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2459251509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2459251509
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3207946205
Short name T614
Test name
Test status
Simulation time 733190400 ps
CPU time 163 seconds
Started Jun 11 03:03:21 PM PDT 24
Finished Jun 11 03:06:05 PM PDT 24
Peak memory 282264 kb
Host smart-3448b6d2-a22b-4b08-a582-8428fcbf9f29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207946205 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3207946205
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3276358949
Short name T874
Test name
Test status
Simulation time 7383319400 ps
CPU time 729.15 seconds
Started Jun 11 03:03:22 PM PDT 24
Finished Jun 11 03:15:33 PM PDT 24
Peak memory 314452 kb
Host smart-76a965ea-aae5-4f65-8d49-2359c5875830
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276358949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.3276358949
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.617830868
Short name T698
Test name
Test status
Simulation time 68418500 ps
CPU time 27.99 seconds
Started Jun 11 03:03:36 PM PDT 24
Finished Jun 11 03:04:05 PM PDT 24
Peak memory 275824 kb
Host smart-80693086-418e-4f0e-b49d-3acf6794ee0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617830868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.617830868
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.833664041
Short name T749
Test name
Test status
Simulation time 32949300 ps
CPU time 31.53 seconds
Started Jun 11 03:03:37 PM PDT 24
Finished Jun 11 03:04:09 PM PDT 24
Peak memory 275192 kb
Host smart-d1c15083-c349-4c39-8dcc-4e894f60e87e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833664041 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.833664041
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.2184862080
Short name T649
Test name
Test status
Simulation time 14321734800 ps
CPU time 676.79 seconds
Started Jun 11 03:03:31 PM PDT 24
Finished Jun 11 03:14:49 PM PDT 24
Peak memory 313252 kb
Host smart-904918a1-7da3-4c7a-bbf0-ee237001fc38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184862080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.2184862080
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.190546186
Short name T385
Test name
Test status
Simulation time 385872800 ps
CPU time 59 seconds
Started Jun 11 03:03:37 PM PDT 24
Finished Jun 11 03:04:37 PM PDT 24
Peak memory 263976 kb
Host smart-74b8bc70-db99-4c0b-a3a2-1329fbce39c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190546186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.190546186
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3072884090
Short name T947
Test name
Test status
Simulation time 25544100 ps
CPU time 100.78 seconds
Started Jun 11 03:02:47 PM PDT 24
Finished Jun 11 03:04:28 PM PDT 24
Peak memory 276084 kb
Host smart-04a7df21-0540-4d31-a9b5-49e6174bdae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072884090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3072884090
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.3109761021
Short name T772
Test name
Test status
Simulation time 31922900 ps
CPU time 25.76 seconds
Started Jun 11 03:02:44 PM PDT 24
Finished Jun 11 03:03:10 PM PDT 24
Peak memory 259928 kb
Host smart-fafb79ce-197b-4e83-b39f-6f7e9c9f8353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109761021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3109761021
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.3023802081
Short name T550
Test name
Test status
Simulation time 214936700 ps
CPU time 1265.27 seconds
Started Jun 11 03:03:38 PM PDT 24
Finished Jun 11 03:24:44 PM PDT 24
Peak memory 296680 kb
Host smart-65d19f64-f6a6-485b-949d-d2b716e8bcd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023802081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.3023802081
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2093510682
Short name T445
Test name
Test status
Simulation time 33365400 ps
CPU time 23.9 seconds
Started Jun 11 03:02:43 PM PDT 24
Finished Jun 11 03:03:08 PM PDT 24
Peak memory 259920 kb
Host smart-ae2c6797-00e9-4b61-817b-32afc48e7720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093510682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2093510682
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1674101528
Short name T478
Test name
Test status
Simulation time 9511035700 ps
CPU time 196.57 seconds
Started Jun 11 03:03:10 PM PDT 24
Finished Jun 11 03:06:28 PM PDT 24
Peak memory 260252 kb
Host smart-82c9b593-5122-44e9-b965-196d2bd4ffc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674101528 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.1674101528
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.2882103328
Short name T716
Test name
Test status
Simulation time 74458600 ps
CPU time 13.46 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:14:40 PM PDT 24
Peak memory 258536 kb
Host smart-c9e7c4bf-c1b1-46aa-b5db-807478f391d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882103328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
2882103328
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.3770465288
Short name T309
Test name
Test status
Simulation time 27926800 ps
CPU time 13.63 seconds
Started Jun 11 03:14:12 PM PDT 24
Finished Jun 11 03:14:27 PM PDT 24
Peak memory 275124 kb
Host smart-4702a477-e91d-4d05-a564-30f560ba530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770465288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.3770465288
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.2362387107
Short name T1086
Test name
Test status
Simulation time 29610000 ps
CPU time 21.78 seconds
Started Jun 11 03:14:15 PM PDT 24
Finished Jun 11 03:14:38 PM PDT 24
Peak memory 274040 kb
Host smart-e7bee716-4b96-40c6-b605-925c650f4840
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362387107 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.2362387107
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.2554912024
Short name T529
Test name
Test status
Simulation time 6351331900 ps
CPU time 143.1 seconds
Started Jun 11 03:14:13 PM PDT 24
Finished Jun 11 03:16:38 PM PDT 24
Peak memory 263652 kb
Host smart-544f6cb6-b740-4966-906d-c37ff7e2e4dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554912024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.2554912024
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.895932135
Short name T834
Test name
Test status
Simulation time 133438100 ps
CPU time 133.31 seconds
Started Jun 11 03:14:13 PM PDT 24
Finished Jun 11 03:16:28 PM PDT 24
Peak memory 261440 kb
Host smart-b27fedfd-ab9f-4965-bc51-dce746127c7e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895932135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.895932135
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1799271409
Short name T790
Test name
Test status
Simulation time 1717159500 ps
CPU time 67.94 seconds
Started Jun 11 03:14:14 PM PDT 24
Finished Jun 11 03:15:24 PM PDT 24
Peak memory 263848 kb
Host smart-d3986143-aaa6-4b7a-a699-16c946df0e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799271409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1799271409
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2161691055
Short name T837
Test name
Test status
Simulation time 18522200 ps
CPU time 145.44 seconds
Started Jun 11 03:14:12 PM PDT 24
Finished Jun 11 03:16:39 PM PDT 24
Peak memory 278212 kb
Host smart-e03a46cb-ec71-4c13-931d-8becbe53970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161691055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2161691055
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2862973839
Short name T417
Test name
Test status
Simulation time 161964100 ps
CPU time 13.35 seconds
Started Jun 11 03:14:23 PM PDT 24
Finished Jun 11 03:14:37 PM PDT 24
Peak memory 265424 kb
Host smart-708787e3-3e1c-44e3-9fc8-89d6ba944705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862973839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2862973839
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2546313025
Short name T525
Test name
Test status
Simulation time 51777500 ps
CPU time 15.75 seconds
Started Jun 11 03:14:24 PM PDT 24
Finished Jun 11 03:14:41 PM PDT 24
Peak memory 275196 kb
Host smart-0d8d4fea-7322-4540-9235-3f88d0ce8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546313025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2546313025
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.1056811533
Short name T581
Test name
Test status
Simulation time 12660700 ps
CPU time 21.98 seconds
Started Jun 11 03:14:24 PM PDT 24
Finished Jun 11 03:14:48 PM PDT 24
Peak memory 274056 kb
Host smart-b5ff3151-95d0-4ac2-949f-659e82cda95e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056811533 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.1056811533
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1102353347
Short name T830
Test name
Test status
Simulation time 2221782100 ps
CPU time 93.65 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:16:00 PM PDT 24
Peak memory 261048 kb
Host smart-52c2a054-3efb-405b-87d6-d7d229ba257e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102353347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1102353347
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2364862474
Short name T883
Test name
Test status
Simulation time 33333600 ps
CPU time 132.85 seconds
Started Jun 11 03:14:24 PM PDT 24
Finished Jun 11 03:16:38 PM PDT 24
Peak memory 260368 kb
Host smart-49071975-5647-4371-8ae0-7af0b5ef50cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364862474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2364862474
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.1130139101
Short name T922
Test name
Test status
Simulation time 524635300 ps
CPU time 59.53 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:15:26 PM PDT 24
Peak memory 263916 kb
Host smart-594b9ca1-5be6-4c7b-b243-ead5577776db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130139101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1130139101
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1234404926
Short name T726
Test name
Test status
Simulation time 704857300 ps
CPU time 196.29 seconds
Started Jun 11 03:14:23 PM PDT 24
Finished Jun 11 03:17:40 PM PDT 24
Peak memory 281648 kb
Host smart-ded8f754-edd5-4d20-87dd-4f40a0f4d22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234404926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1234404926
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.680226280
Short name T745
Test name
Test status
Simulation time 36386200 ps
CPU time 13.52 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:14:40 PM PDT 24
Peak memory 258544 kb
Host smart-4e4c6f43-0264-4760-8d03-db28f585d840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680226280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.680226280
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.440604986
Short name T432
Test name
Test status
Simulation time 17405100 ps
CPU time 15.94 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:14:42 PM PDT 24
Peak memory 275224 kb
Host smart-cc73b088-634e-4784-be34-03d615722d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440604986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.440604986
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3094312350
Short name T555
Test name
Test status
Simulation time 23649400 ps
CPU time 20.65 seconds
Started Jun 11 03:14:24 PM PDT 24
Finished Jun 11 03:14:46 PM PDT 24
Peak memory 274024 kb
Host smart-9900081b-e430-4bc3-bae8-585960f9c7a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094312350 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3094312350
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2278303695
Short name T196
Test name
Test status
Simulation time 5136467400 ps
CPU time 124.2 seconds
Started Jun 11 03:14:24 PM PDT 24
Finished Jun 11 03:16:30 PM PDT 24
Peak memory 263352 kb
Host smart-2d08b757-277d-4bef-b000-a7ea1e0daa6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278303695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2278303695
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.4165331557
Short name T970
Test name
Test status
Simulation time 56746700 ps
CPU time 132.07 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:16:39 PM PDT 24
Peak memory 264996 kb
Host smart-7b2f1db7-eef2-4c22-853e-371033e3a5ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165331557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.4165331557
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2520760451
Short name T524
Test name
Test status
Simulation time 8271245800 ps
CPU time 83.09 seconds
Started Jun 11 03:14:27 PM PDT 24
Finished Jun 11 03:15:51 PM PDT 24
Peak memory 263352 kb
Host smart-f5f310c5-4848-4a10-a22e-da7ff3e6fc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520760451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2520760451
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1335666388
Short name T717
Test name
Test status
Simulation time 349399700 ps
CPU time 121.86 seconds
Started Jun 11 03:14:25 PM PDT 24
Finished Jun 11 03:16:28 PM PDT 24
Peak memory 276868 kb
Host smart-b9360f36-8aaa-422b-b8fd-aa0eaad05118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335666388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1335666388
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.3291006733
Short name T517
Test name
Test status
Simulation time 126339500 ps
CPU time 13.43 seconds
Started Jun 11 03:14:33 PM PDT 24
Finished Jun 11 03:14:48 PM PDT 24
Peak memory 258588 kb
Host smart-1f8910c9-b39a-4ae0-ae72-ff07cbaa52f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291006733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
3291006733
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3429192155
Short name T200
Test name
Test status
Simulation time 27548200 ps
CPU time 13.54 seconds
Started Jun 11 03:14:32 PM PDT 24
Finished Jun 11 03:14:46 PM PDT 24
Peak memory 274976 kb
Host smart-590172ce-dbc1-48ef-b62d-25e29d1790ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429192155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3429192155
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2205284925
Short name T626
Test name
Test status
Simulation time 18205700 ps
CPU time 20.8 seconds
Started Jun 11 03:14:32 PM PDT 24
Finished Jun 11 03:14:54 PM PDT 24
Peak memory 265272 kb
Host smart-aa61a5a6-24e8-4a3c-9c6c-450827612e17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205284925 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2205284925
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.895496521
Short name T644
Test name
Test status
Simulation time 6677507600 ps
CPU time 265.3 seconds
Started Jun 11 03:14:33 PM PDT 24
Finished Jun 11 03:19:00 PM PDT 24
Peak memory 262940 kb
Host smart-0d87143f-ce41-4c3b-b7f0-b016bdd2207b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895496521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.895496521
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1061085082
Short name T820
Test name
Test status
Simulation time 78232300 ps
CPU time 131.49 seconds
Started Jun 11 03:14:31 PM PDT 24
Finished Jun 11 03:16:44 PM PDT 24
Peak memory 261356 kb
Host smart-66157d1e-82b5-40ad-9dce-bc59e7082875
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061085082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1061085082
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2545483888
Short name T497
Test name
Test status
Simulation time 8665602600 ps
CPU time 79.78 seconds
Started Jun 11 03:14:34 PM PDT 24
Finished Jun 11 03:15:55 PM PDT 24
Peak memory 265556 kb
Host smart-e6451633-a4ab-47df-8473-df144d51a133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545483888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2545483888
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2175424845
Short name T628
Test name
Test status
Simulation time 24445800 ps
CPU time 169.75 seconds
Started Jun 11 03:14:33 PM PDT 24
Finished Jun 11 03:17:24 PM PDT 24
Peak memory 279344 kb
Host smart-349115f6-5610-40dd-9d99-71b400258d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175424845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2175424845
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.4048662729
Short name T431
Test name
Test status
Simulation time 34677700 ps
CPU time 13.77 seconds
Started Jun 11 03:14:34 PM PDT 24
Finished Jun 11 03:14:49 PM PDT 24
Peak memory 258592 kb
Host smart-03c58307-c503-46c5-92c8-dbaecc146954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048662729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
4048662729
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3774452076
Short name T887
Test name
Test status
Simulation time 25142500 ps
CPU time 13.17 seconds
Started Jun 11 03:14:33 PM PDT 24
Finished Jun 11 03:14:48 PM PDT 24
Peak memory 275124 kb
Host smart-107a3b91-4c41-4c40-922c-f7e9cf72ef66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774452076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3774452076
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3827684973
Short name T1065
Test name
Test status
Simulation time 27948600 ps
CPU time 21.86 seconds
Started Jun 11 03:14:35 PM PDT 24
Finished Jun 11 03:14:58 PM PDT 24
Peak memory 265868 kb
Host smart-63491117-92ab-4c81-b441-429444ac885c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827684973 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3827684973
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1928336771
Short name T783
Test name
Test status
Simulation time 3330841800 ps
CPU time 140.37 seconds
Started Jun 11 03:14:34 PM PDT 24
Finished Jun 11 03:16:56 PM PDT 24
Peak memory 263360 kb
Host smart-93d55f2f-42eb-4ad9-a423-76fbe65eb0e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928336771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1928336771
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.222187318
Short name T632
Test name
Test status
Simulation time 72854700 ps
CPU time 133.24 seconds
Started Jun 11 03:14:32 PM PDT 24
Finished Jun 11 03:16:46 PM PDT 24
Peak memory 261460 kb
Host smart-3c9f9561-e97c-495b-adcc-9957d2e5e36a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222187318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.222187318
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.2154615004
Short name T627
Test name
Test status
Simulation time 128148200 ps
CPU time 98.49 seconds
Started Jun 11 03:14:32 PM PDT 24
Finished Jun 11 03:16:11 PM PDT 24
Peak memory 276500 kb
Host smart-c08b2a25-1b41-45e1-85a2-7e9cb72704aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154615004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2154615004
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.447263899
Short name T855
Test name
Test status
Simulation time 97073200 ps
CPU time 14.03 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:14:57 PM PDT 24
Peak memory 258524 kb
Host smart-b2ff1c66-6f82-4fdc-a466-91c55a76aafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447263899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.447263899
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.106306475
Short name T763
Test name
Test status
Simulation time 15434500 ps
CPU time 13.48 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:14:56 PM PDT 24
Peak memory 274996 kb
Host smart-4919cb38-2dc5-42d5-aa26-83ecb779a3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106306475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.106306475
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.262091652
Short name T62
Test name
Test status
Simulation time 41012700 ps
CPU time 21.03 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:15:04 PM PDT 24
Peak memory 274052 kb
Host smart-fcc877ee-723a-45af-904f-f70fe1294296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262091652 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.262091652
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.645909485
Short name T658
Test name
Test status
Simulation time 3279782900 ps
CPU time 136.01 seconds
Started Jun 11 03:14:32 PM PDT 24
Finished Jun 11 03:16:49 PM PDT 24
Peak memory 262864 kb
Host smart-262ec63c-7c48-4746-b953-8deb192b1c50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645909485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_h
w_sec_otp.645909485
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1920816503
Short name T1023
Test name
Test status
Simulation time 147629800 ps
CPU time 132.09 seconds
Started Jun 11 03:14:40 PM PDT 24
Finished Jun 11 03:16:53 PM PDT 24
Peak memory 261400 kb
Host smart-dbaed811-b0e4-426d-9a20-109e491f0eec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920816503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1920816503
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1360146646
Short name T444
Test name
Test status
Simulation time 2349149800 ps
CPU time 62.47 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:15:46 PM PDT 24
Peak memory 264876 kb
Host smart-1b87fcb8-1de3-4a05-a262-d038c7363837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360146646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1360146646
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.267502949
Short name T913
Test name
Test status
Simulation time 92119900 ps
CPU time 121.97 seconds
Started Jun 11 03:14:34 PM PDT 24
Finished Jun 11 03:16:37 PM PDT 24
Peak memory 276540 kb
Host smart-70f0a63d-3429-41e9-858b-e69d88b95eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267502949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.267502949
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1556156925
Short name T1075
Test name
Test status
Simulation time 52895400 ps
CPU time 13.61 seconds
Started Jun 11 03:14:45 PM PDT 24
Finished Jun 11 03:14:59 PM PDT 24
Peak memory 265540 kb
Host smart-a2fb5c7c-f0c5-41fa-98fd-ab689d1a2b8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556156925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1556156925
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2431854469
Short name T768
Test name
Test status
Simulation time 16762000 ps
CPU time 16.18 seconds
Started Jun 11 03:14:41 PM PDT 24
Finished Jun 11 03:14:59 PM PDT 24
Peak memory 275164 kb
Host smart-88dc0b1c-aeb1-4fe7-8186-8b3a2ae96ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431854469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2431854469
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.668542867
Short name T383
Test name
Test status
Simulation time 11447000 ps
CPU time 21.61 seconds
Started Jun 11 03:14:45 PM PDT 24
Finished Jun 11 03:15:08 PM PDT 24
Peak memory 265308 kb
Host smart-13c5a688-b4cf-4875-81a2-5b792a38fbb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668542867 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.668542867
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2298594841
Short name T423
Test name
Test status
Simulation time 16327839000 ps
CPU time 125.37 seconds
Started Jun 11 03:14:44 PM PDT 24
Finished Jun 11 03:16:50 PM PDT 24
Peak memory 261056 kb
Host smart-e1a25cc1-7cb5-4e34-958d-7470d8d8a3d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298594841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2298594841
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3413826728
Short name T1027
Test name
Test status
Simulation time 110513100 ps
CPU time 129.6 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:16:54 PM PDT 24
Peak memory 261260 kb
Host smart-2ee396b0-20ee-45ad-b1ab-789f025eae48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413826728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3413826728
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2753630280
Short name T932
Test name
Test status
Simulation time 6502354900 ps
CPU time 71.69 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:15:55 PM PDT 24
Peak memory 263980 kb
Host smart-b4c4608a-0a42-4e52-b9b2-4ea7eb20d76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753630280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2753630280
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3045095007
Short name T470
Test name
Test status
Simulation time 28632800 ps
CPU time 96.32 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:16:20 PM PDT 24
Peak memory 276140 kb
Host smart-43a8c7cf-9708-415e-80e8-18dbf22a5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045095007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3045095007
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.662992794
Short name T1073
Test name
Test status
Simulation time 29910800 ps
CPU time 13.54 seconds
Started Jun 11 03:14:46 PM PDT 24
Finished Jun 11 03:15:01 PM PDT 24
Peak memory 258576 kb
Host smart-2b652967-f442-44d1-ac89-1e04b48b7198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662992794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.662992794
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2783217916
Short name T99
Test name
Test status
Simulation time 39705400 ps
CPU time 13.68 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:14:56 PM PDT 24
Peak memory 275228 kb
Host smart-2fb07323-1eac-41a1-829c-fb0a20ba74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783217916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2783217916
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.3769772391
Short name T140
Test name
Test status
Simulation time 40076000 ps
CPU time 21.6 seconds
Started Jun 11 03:14:46 PM PDT 24
Finished Jun 11 03:15:09 PM PDT 24
Peak memory 274068 kb
Host smart-20db8f61-422b-42bd-98ab-c99fe40e64ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769772391 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.3769772391
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1177016398
Short name T80
Test name
Test status
Simulation time 2269177000 ps
CPU time 89.04 seconds
Started Jun 11 03:14:44 PM PDT 24
Finished Jun 11 03:16:14 PM PDT 24
Peak memory 262800 kb
Host smart-544f1b6a-96b4-4fab-b303-629f503b594c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177016398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1177016398
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.380076039
Short name T495
Test name
Test status
Simulation time 74779000 ps
CPU time 109.85 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:16:34 PM PDT 24
Peak memory 261516 kb
Host smart-c8949075-0745-4794-9aaf-5a059a7bd86d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380076039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.380076039
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.3105656187
Short name T475
Test name
Test status
Simulation time 2123982300 ps
CPU time 79.36 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:16:04 PM PDT 24
Peak memory 259936 kb
Host smart-3f5d9708-7c41-44ca-9afd-ff07de811ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105656187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3105656187
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2128310237
Short name T552
Test name
Test status
Simulation time 78912200 ps
CPU time 122.88 seconds
Started Jun 11 03:14:41 PM PDT 24
Finished Jun 11 03:16:45 PM PDT 24
Peak memory 276292 kb
Host smart-5f17a935-f0ff-45bf-a0f6-1200b3245104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128310237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2128310237
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.4139237376
Short name T724
Test name
Test status
Simulation time 79651000 ps
CPU time 13.83 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:14:58 PM PDT 24
Peak memory 265480 kb
Host smart-06b668a6-b7d4-41ff-97cc-0d313b20c61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139237376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
4139237376
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1665492550
Short name T573
Test name
Test status
Simulation time 14627300 ps
CPU time 13.49 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:14:56 PM PDT 24
Peak memory 275288 kb
Host smart-89fa4013-f557-4cb9-8a8b-6a4ac222140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665492550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1665492550
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.3772662535
Short name T198
Test name
Test status
Simulation time 41613700 ps
CPU time 21.62 seconds
Started Jun 11 03:14:44 PM PDT 24
Finished Jun 11 03:15:06 PM PDT 24
Peak memory 274092 kb
Host smart-c28cf324-7135-436c-8d5d-eaf0cb517d1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772662535 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.3772662535
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1702712762
Short name T313
Test name
Test status
Simulation time 7385533700 ps
CPU time 161.09 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:17:25 PM PDT 24
Peak memory 263284 kb
Host smart-1cbb01cd-9dcb-4580-9d42-0ef40a453564
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702712762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.1702712762
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2527405705
Short name T986
Test name
Test status
Simulation time 542808700 ps
CPU time 132.37 seconds
Started Jun 11 03:14:42 PM PDT 24
Finished Jun 11 03:16:56 PM PDT 24
Peak memory 265600 kb
Host smart-e2b7ff60-f407-4588-9aa1-319d7ec33061
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527405705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2527405705
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3392653592
Short name T787
Test name
Test status
Simulation time 6158397100 ps
CPU time 75.27 seconds
Started Jun 11 03:14:41 PM PDT 24
Finished Jun 11 03:15:57 PM PDT 24
Peak memory 263920 kb
Host smart-62fc4ab4-b223-4630-8825-ae55bd58f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392653592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3392653592
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3431776684
Short name T971
Test name
Test status
Simulation time 74800100 ps
CPU time 75.14 seconds
Started Jun 11 03:14:43 PM PDT 24
Finished Jun 11 03:15:59 PM PDT 24
Peak memory 276816 kb
Host smart-485ed2f3-d9a5-4715-807b-8662e371c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431776684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3431776684
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.593999541
Short name T702
Test name
Test status
Simulation time 53080700 ps
CPU time 13.44 seconds
Started Jun 11 03:14:53 PM PDT 24
Finished Jun 11 03:15:07 PM PDT 24
Peak memory 265512 kb
Host smart-8b58d919-d9cc-426c-a9b4-eb1ae842f022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593999541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.593999541
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.1052802500
Short name T957
Test name
Test status
Simulation time 114197500 ps
CPU time 16.18 seconds
Started Jun 11 03:14:53 PM PDT 24
Finished Jun 11 03:15:10 PM PDT 24
Peak memory 275072 kb
Host smart-9c6c60b6-fb81-4dc3-8ee3-367c14ef4e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052802500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1052802500
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.3100520990
Short name T708
Test name
Test status
Simulation time 30569400 ps
CPU time 21.74 seconds
Started Jun 11 03:14:54 PM PDT 24
Finished Jun 11 03:15:17 PM PDT 24
Peak memory 265324 kb
Host smart-14c4f615-72e6-48d8-9278-d3191013fd3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100520990 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.3100520990
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.4156711085
Short name T454
Test name
Test status
Simulation time 1637768600 ps
CPU time 48.78 seconds
Started Jun 11 03:14:52 PM PDT 24
Finished Jun 11 03:15:41 PM PDT 24
Peak memory 262996 kb
Host smart-bdfb2945-3088-487c-bb2d-409817b56420
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156711085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.4156711085
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.276624147
Short name T498
Test name
Test status
Simulation time 83602800 ps
CPU time 130.11 seconds
Started Jun 11 03:14:52 PM PDT 24
Finished Jun 11 03:17:03 PM PDT 24
Peak memory 261372 kb
Host smart-cc1a7cf4-b40e-4205-b211-85c02251655a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276624147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.276624147
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.4193190042
Short name T223
Test name
Test status
Simulation time 3637860900 ps
CPU time 70.85 seconds
Started Jun 11 03:14:55 PM PDT 24
Finished Jun 11 03:16:07 PM PDT 24
Peak memory 259808 kb
Host smart-17634271-7e46-4196-9cfa-740f056c0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193190042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.4193190042
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1140921940
Short name T707
Test name
Test status
Simulation time 33491400 ps
CPU time 97.08 seconds
Started Jun 11 03:14:52 PM PDT 24
Finished Jun 11 03:16:30 PM PDT 24
Peak memory 277380 kb
Host smart-61735b3d-2e57-43d3-b26e-4c96117e0d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140921940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1140921940
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.145818441
Short name T687
Test name
Test status
Simulation time 89677900 ps
CPU time 13.79 seconds
Started Jun 11 03:04:36 PM PDT 24
Finished Jun 11 03:04:51 PM PDT 24
Peak memory 258548 kb
Host smart-927e321c-236c-4857-829d-facf7dc2669f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145818441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.145818441
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.388314049
Short name T473
Test name
Test status
Simulation time 29800300 ps
CPU time 15.71 seconds
Started Jun 11 03:04:36 PM PDT 24
Finished Jun 11 03:04:53 PM PDT 24
Peak memory 275140 kb
Host smart-a3d97368-9a17-41e1-b46c-27ed3dee1e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388314049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.388314049
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.2693329108
Short name T734
Test name
Test status
Simulation time 11887000 ps
CPU time 22.1 seconds
Started Jun 11 03:04:36 PM PDT 24
Finished Jun 11 03:05:00 PM PDT 24
Peak memory 274332 kb
Host smart-c268cb30-e5cd-4ca8-95da-f6e0b4c82c65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693329108 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.2693329108
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.170224287
Short name T2
Test name
Test status
Simulation time 2590827600 ps
CPU time 2146.64 seconds
Started Jun 11 03:04:03 PM PDT 24
Finished Jun 11 03:39:51 PM PDT 24
Peak memory 263076 kb
Host smart-7ba87235-e8c7-466f-ac17-1c8eab74eae9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170224287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_erro
r_mp.170224287
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.3470386741
Short name T917
Test name
Test status
Simulation time 2603455000 ps
CPU time 736.28 seconds
Started Jun 11 03:04:03 PM PDT 24
Finished Jun 11 03:16:20 PM PDT 24
Peak memory 272832 kb
Host smart-d42792e2-b953-42b1-877a-b1ee700e5e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470386741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3470386741
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2401168204
Short name T67
Test name
Test status
Simulation time 1373821200 ps
CPU time 27.07 seconds
Started Jun 11 03:04:04 PM PDT 24
Finished Jun 11 03:04:32 PM PDT 24
Peak memory 262816 kb
Host smart-453c6a9a-46dc-43a9-87c7-3e163272c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401168204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2401168204
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4269449285
Short name T290
Test name
Test status
Simulation time 10137591000 ps
CPU time 41.46 seconds
Started Jun 11 03:04:34 PM PDT 24
Finished Jun 11 03:05:17 PM PDT 24
Peak memory 262816 kb
Host smart-63ed7919-390a-465e-90ad-02abe23b6d49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269449285 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4269449285
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.4050911614
Short name T1004
Test name
Test status
Simulation time 46651400 ps
CPU time 13.38 seconds
Started Jun 11 03:04:36 PM PDT 24
Finished Jun 11 03:04:52 PM PDT 24
Peak memory 259676 kb
Host smart-b437d6ae-4d4a-40a0-9502-cf772030dbce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050911614 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.4050911614
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.606790080
Short name T1037
Test name
Test status
Simulation time 160163256000 ps
CPU time 835.27 seconds
Started Jun 11 03:03:54 PM PDT 24
Finished Jun 11 03:17:51 PM PDT 24
Peak memory 264680 kb
Host smart-d32f84a2-ffdd-4e7e-a788-ad5b9cbe81bf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606790080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.606790080
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1255997577
Short name T212
Test name
Test status
Simulation time 2272543300 ps
CPU time 91.74 seconds
Started Jun 11 03:03:54 PM PDT 24
Finished Jun 11 03:05:27 PM PDT 24
Peak memory 263472 kb
Host smart-fa46aa5f-90da-48ab-926a-2e6ed222cb31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255997577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1255997577
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.4213234103
Short name T934
Test name
Test status
Simulation time 1479714500 ps
CPU time 165.32 seconds
Started Jun 11 03:04:15 PM PDT 24
Finished Jun 11 03:07:01 PM PDT 24
Peak memory 294472 kb
Host smart-eab724ab-d911-4ca6-bcc5-140af760a3e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213234103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.4213234103
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1419646244
Short name T346
Test name
Test status
Simulation time 8555946200 ps
CPU time 240.77 seconds
Started Jun 11 03:04:27 PM PDT 24
Finished Jun 11 03:08:28 PM PDT 24
Peak memory 293460 kb
Host smart-b37c5a52-7d65-417a-b1db-be6b306cfa70
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419646244 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1419646244
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2803097692
Short name T33
Test name
Test status
Simulation time 2915684200 ps
CPU time 69.34 seconds
Started Jun 11 03:04:15 PM PDT 24
Finished Jun 11 03:05:25 PM PDT 24
Peak memory 260840 kb
Host smart-59b9d2f9-b236-456a-8796-54011893c8e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803097692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2803097692
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.113290285
Short name T31
Test name
Test status
Simulation time 53894416700 ps
CPU time 261.15 seconds
Started Jun 11 03:04:29 PM PDT 24
Finished Jun 11 03:08:51 PM PDT 24
Peak memory 265532 kb
Host smart-1c20adda-e64f-440b-9ddf-6820fe79b9cc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113
290285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.113290285
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.766004523
Short name T292
Test name
Test status
Simulation time 47259100 ps
CPU time 13.64 seconds
Started Jun 11 03:04:36 PM PDT 24
Finished Jun 11 03:04:52 PM PDT 24
Peak memory 260176 kb
Host smart-d3de80f8-3f71-4b27-aa29-dff91330a6e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766004523 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.766004523
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.704462498
Short name T713
Test name
Test status
Simulation time 8452770100 ps
CPU time 160.31 seconds
Started Jun 11 03:04:04 PM PDT 24
Finished Jun 11 03:06:45 PM PDT 24
Peak memory 265532 kb
Host smart-f813dd8d-c8a7-47d7-85c1-f5eae3a58488
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704462498 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_mp_regions.704462498
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.3716871179
Short name T228
Test name
Test status
Simulation time 902479300 ps
CPU time 371.73 seconds
Started Jun 11 03:03:55 PM PDT 24
Finished Jun 11 03:10:08 PM PDT 24
Peak memory 263332 kb
Host smart-860f16ce-c10e-48a0-af5a-6596c168a807
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716871179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3716871179
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2943740562
Short name T773
Test name
Test status
Simulation time 5750388900 ps
CPU time 221.94 seconds
Started Jun 11 03:04:27 PM PDT 24
Finished Jun 11 03:08:09 PM PDT 24
Peak memory 265400 kb
Host smart-5c4f8b11-7919-4d26-bc97-89d3f2671eec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943740562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.2943740562
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.2096746437
Short name T777
Test name
Test status
Simulation time 157841900 ps
CPU time 414.22 seconds
Started Jun 11 03:03:55 PM PDT 24
Finished Jun 11 03:10:50 PM PDT 24
Peak memory 281956 kb
Host smart-57e088c6-a953-407c-8abe-133d113ee87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096746437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2096746437
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2838183548
Short name T642
Test name
Test status
Simulation time 109320800 ps
CPU time 33.65 seconds
Started Jun 11 03:04:28 PM PDT 24
Finished Jun 11 03:05:03 PM PDT 24
Peak memory 275748 kb
Host smart-8e03b81e-1bc4-4acf-b66d-c2b2c7f20d0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838183548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2838183548
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.923742069
Short name T811
Test name
Test status
Simulation time 2249217400 ps
CPU time 162.54 seconds
Started Jun 11 03:04:13 PM PDT 24
Finished Jun 11 03:06:57 PM PDT 24
Peak memory 282320 kb
Host smart-86345a91-aa19-4710-bc7d-c554133f509d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
923742069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.923742069
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2993510678
Short name T532
Test name
Test status
Simulation time 2510512700 ps
CPU time 139.32 seconds
Started Jun 11 03:04:15 PM PDT 24
Finished Jun 11 03:06:36 PM PDT 24
Peak memory 282248 kb
Host smart-c45bdcc7-4eb2-4377-bcac-da0237e39fb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993510678 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2993510678
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.166004729
Short name T762
Test name
Test status
Simulation time 28536494200 ps
CPU time 573.84 seconds
Started Jun 11 03:04:15 PM PDT 24
Finished Jun 11 03:13:50 PM PDT 24
Peak memory 314408 kb
Host smart-68246ae7-7a30-4c06-9723-e9ba662d63e1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166004729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_rw.166004729
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.1069838447
Short name T981
Test name
Test status
Simulation time 4325138200 ps
CPU time 585.72 seconds
Started Jun 11 03:04:14 PM PDT 24
Finished Jun 11 03:14:01 PM PDT 24
Peak memory 319204 kb
Host smart-9d9f9d1c-077f-4366-addc-b7b01a28cc39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069838447 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.1069838447
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.3950114777
Short name T333
Test name
Test status
Simulation time 31855400 ps
CPU time 31.87 seconds
Started Jun 11 03:04:29 PM PDT 24
Finished Jun 11 03:05:02 PM PDT 24
Peak memory 275800 kb
Host smart-cceb4511-8f87-43a5-8e00-f14125142646
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950114777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.3950114777
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.1349745350
Short name T327
Test name
Test status
Simulation time 31245000 ps
CPU time 31.09 seconds
Started Jun 11 03:04:29 PM PDT 24
Finished Jun 11 03:05:01 PM PDT 24
Peak memory 267856 kb
Host smart-7e93af4a-ba7b-4ecd-a1a8-8a141342bcf8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349745350 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.1349745350
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.513525750
Short name T397
Test name
Test status
Simulation time 3559761600 ps
CPU time 72.27 seconds
Started Jun 11 03:04:38 PM PDT 24
Finished Jun 11 03:05:52 PM PDT 24
Peak memory 263304 kb
Host smart-80939c05-0e88-4953-bdec-519549e9cd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513525750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.513525750
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2466299041
Short name T232
Test name
Test status
Simulation time 56691100 ps
CPU time 124.72 seconds
Started Jun 11 03:03:54 PM PDT 24
Finished Jun 11 03:06:00 PM PDT 24
Peak memory 276524 kb
Host smart-1c1d3ddc-c552-469f-9550-7f8ce19616d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466299041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2466299041
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3710075867
Short name T559
Test name
Test status
Simulation time 9287976300 ps
CPU time 175.07 seconds
Started Jun 11 03:04:04 PM PDT 24
Finished Jun 11 03:07:01 PM PDT 24
Peak memory 259708 kb
Host smart-b89c193f-9ffe-478f-a40c-de8cc9cee91f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710075867 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.3710075867
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1858501466
Short name T429
Test name
Test status
Simulation time 21317700 ps
CPU time 13.85 seconds
Started Jun 11 03:14:54 PM PDT 24
Finished Jun 11 03:15:09 PM PDT 24
Peak memory 284536 kb
Host smart-370021ab-48e9-4e5d-855a-39dab48db26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858501466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1858501466
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.1508006940
Short name T667
Test name
Test status
Simulation time 75974700 ps
CPU time 131.46 seconds
Started Jun 11 03:14:52 PM PDT 24
Finished Jun 11 03:17:04 PM PDT 24
Peak memory 261240 kb
Host smart-dc5a4279-ef81-40ca-b0c5-ce1bc80defb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508006940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.1508006940
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3879536471
Short name T725
Test name
Test status
Simulation time 53858800 ps
CPU time 16.22 seconds
Started Jun 11 03:14:53 PM PDT 24
Finished Jun 11 03:15:10 PM PDT 24
Peak memory 275124 kb
Host smart-5a878626-97ae-4fe0-95c0-daa5ebe15295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879536471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3879536471
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.1874530430
Short name T650
Test name
Test status
Simulation time 226877700 ps
CPU time 109.6 seconds
Started Jun 11 03:14:54 PM PDT 24
Finished Jun 11 03:16:44 PM PDT 24
Peak memory 265124 kb
Host smart-69215ce5-6562-464f-870a-88cd4f5821e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874530430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.1874530430
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.2802935997
Short name T543
Test name
Test status
Simulation time 14868700 ps
CPU time 15.74 seconds
Started Jun 11 03:14:53 PM PDT 24
Finished Jun 11 03:15:09 PM PDT 24
Peak memory 275144 kb
Host smart-569c55bf-8a8a-47e8-83c4-cbc88f4d0d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802935997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2802935997
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.766618276
Short name T420
Test name
Test status
Simulation time 37435900 ps
CPU time 132.92 seconds
Started Jun 11 03:14:54 PM PDT 24
Finished Jun 11 03:17:08 PM PDT 24
Peak memory 260260 kb
Host smart-af36fdf5-0cdd-4840-95ce-aef4bd41ea2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766618276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot
p_reset.766618276
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.220638007
Short name T1077
Test name
Test status
Simulation time 139899900 ps
CPU time 15.95 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:15:19 PM PDT 24
Peak memory 275024 kb
Host smart-9c567e97-2c18-40d2-928c-76d73e915e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220638007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.220638007
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.3420872478
Short name T674
Test name
Test status
Simulation time 106558000 ps
CPU time 131.64 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:17:14 PM PDT 24
Peak memory 260740 kb
Host smart-8cf186b1-68fd-42cc-91a9-1d19d4ae36f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420872478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.3420872478
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1036716847
Short name T1064
Test name
Test status
Simulation time 39063300 ps
CPU time 13.16 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:15:16 PM PDT 24
Peak memory 274996 kb
Host smart-ee6ff67d-f069-4e8e-9f19-9a74598eab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036716847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1036716847
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1407245035
Short name T304
Test name
Test status
Simulation time 159180500 ps
CPU time 133 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:17:16 PM PDT 24
Peak memory 261320 kb
Host smart-3bae5342-6fb7-485d-92f1-e9b05fb085bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407245035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1407245035
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.2486497996
Short name T655
Test name
Test status
Simulation time 66594300 ps
CPU time 15.94 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:15:20 PM PDT 24
Peak memory 275120 kb
Host smart-20325cbb-d67c-4344-9d14-db991fc089f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486497996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2486497996
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2899323157
Short name T848
Test name
Test status
Simulation time 42851300 ps
CPU time 131.58 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:17:15 PM PDT 24
Peak memory 260696 kb
Host smart-ac72de0a-224c-4ac8-aaf9-b9fc1063d5dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899323157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2899323157
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2269427851
Short name T1021
Test name
Test status
Simulation time 14246800 ps
CPU time 13.31 seconds
Started Jun 11 03:15:05 PM PDT 24
Finished Jun 11 03:15:19 PM PDT 24
Peak memory 274944 kb
Host smart-bda26980-d350-4123-8d7d-33377b705348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269427851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2269427851
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1664826571
Short name T456
Test name
Test status
Simulation time 124884900 ps
CPU time 13.33 seconds
Started Jun 11 03:15:03 PM PDT 24
Finished Jun 11 03:15:17 PM PDT 24
Peak memory 284552 kb
Host smart-abfce52e-90b5-43fb-9c8a-1a3b3a608f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664826571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1664826571
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3800732982
Short name T740
Test name
Test status
Simulation time 37492800 ps
CPU time 128.76 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:17:11 PM PDT 24
Peak memory 265652 kb
Host smart-15d78d31-e4ea-44e3-8a76-dce9d9302df1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800732982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3800732982
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.2980742067
Short name T418
Test name
Test status
Simulation time 48312600 ps
CPU time 15.82 seconds
Started Jun 11 03:15:05 PM PDT 24
Finished Jun 11 03:15:22 PM PDT 24
Peak memory 275048 kb
Host smart-4ba4f066-ac59-4557-91f9-2939e9e1cc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980742067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2980742067
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.670770041
Short name T905
Test name
Test status
Simulation time 138288700 ps
CPU time 134.36 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:17:18 PM PDT 24
Peak memory 260332 kb
Host smart-ec9c94b8-acfa-485f-8492-dfe216b655d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670770041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.670770041
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.3866947782
Short name T1085
Test name
Test status
Simulation time 48794400 ps
CPU time 13.37 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:15:17 PM PDT 24
Peak memory 275204 kb
Host smart-615a37a9-dcb7-45a5-b385-1f701ea5f601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866947782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.3866947782
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2494813561
Short name T680
Test name
Test status
Simulation time 40728900 ps
CPU time 131.76 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:17:15 PM PDT 24
Peak memory 265604 kb
Host smart-95e5fb73-15f2-4002-9e3f-5bfc677e2d1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494813561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2494813561
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3533313242
Short name T465
Test name
Test status
Simulation time 35278300 ps
CPU time 13.35 seconds
Started Jun 11 03:05:19 PM PDT 24
Finished Jun 11 03:05:34 PM PDT 24
Peak memory 258636 kb
Host smart-a509e5f8-1976-44bd-b582-4994a5fb80cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533313242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
533313242
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.980999088
Short name T488
Test name
Test status
Simulation time 29222200 ps
CPU time 13.18 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:22 PM PDT 24
Peak memory 275020 kb
Host smart-1e986b1b-5031-4f51-8466-882dbc742372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980999088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.980999088
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3044550379
Short name T993
Test name
Test status
Simulation time 20802400 ps
CPU time 22.04 seconds
Started Jun 11 03:05:06 PM PDT 24
Finished Jun 11 03:05:29 PM PDT 24
Peak memory 265836 kb
Host smart-ba353e69-9495-4c12-90d3-2a04ef0e2240
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044550379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3044550379
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2811698258
Short name T721
Test name
Test status
Simulation time 15539013900 ps
CPU time 2365.89 seconds
Started Jun 11 03:04:50 PM PDT 24
Finished Jun 11 03:44:17 PM PDT 24
Peak memory 263012 kb
Host smart-24b36e4d-4737-462f-9cf4-5b7cc850c8e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811698258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.2811698258
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.3038402315
Short name T1030
Test name
Test status
Simulation time 1357678700 ps
CPU time 767.33 seconds
Started Jun 11 03:04:50 PM PDT 24
Finished Jun 11 03:17:38 PM PDT 24
Peak memory 265264 kb
Host smart-f08034e8-5980-4dab-961b-fe05d38e8c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038402315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3038402315
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2307022564
Short name T56
Test name
Test status
Simulation time 672886700 ps
CPU time 27.6 seconds
Started Jun 11 03:04:48 PM PDT 24
Finished Jun 11 03:05:17 PM PDT 24
Peak memory 262772 kb
Host smart-7b46b835-18e9-4785-9fc6-e400b51f7129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307022564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2307022564
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.260348507
Short name T973
Test name
Test status
Simulation time 10014446600 ps
CPU time 87.03 seconds
Started Jun 11 03:05:19 PM PDT 24
Finished Jun 11 03:06:47 PM PDT 24
Peak memory 306936 kb
Host smart-5b2e79d1-409f-4a70-a360-e73c7da40edd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260348507 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.260348507
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3174832170
Short name T288
Test name
Test status
Simulation time 25568600 ps
CPU time 13.41 seconds
Started Jun 11 03:05:19 PM PDT 24
Finished Jun 11 03:05:33 PM PDT 24
Peak memory 265920 kb
Host smart-fe48831a-bea5-4774-80fb-6f352e00ea1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174832170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3174832170
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3075198908
Short name T144
Test name
Test status
Simulation time 40127385900 ps
CPU time 851.59 seconds
Started Jun 11 03:04:48 PM PDT 24
Finished Jun 11 03:19:01 PM PDT 24
Peak memory 263952 kb
Host smart-09b4bd2c-9c8d-49ab-8a69-a32f755f14ea
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075198908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.3075198908
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1950716340
Short name T639
Test name
Test status
Simulation time 50320951400 ps
CPU time 263.41 seconds
Started Jun 11 03:04:45 PM PDT 24
Finished Jun 11 03:09:10 PM PDT 24
Peak memory 263352 kb
Host smart-8300f139-56c6-4a9c-ba39-99e9b1823b5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950716340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1950716340
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.2936375754
Short name T348
Test name
Test status
Simulation time 3148303500 ps
CPU time 153.21 seconds
Started Jun 11 03:04:57 PM PDT 24
Finished Jun 11 03:07:31 PM PDT 24
Peak memory 293640 kb
Host smart-8ff345ab-0099-4f7a-bfe4-cd9a599fbcb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936375754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.2936375754
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.67371492
Short name T608
Test name
Test status
Simulation time 12336999300 ps
CPU time 287.94 seconds
Started Jun 11 03:05:01 PM PDT 24
Finished Jun 11 03:09:50 PM PDT 24
Peak memory 294156 kb
Host smart-3b91df25-e0ea-4f0b-abd6-fd5aadf320de
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67371492 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.67371492
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.4111571246
Short name T469
Test name
Test status
Simulation time 3950728300 ps
CPU time 64.81 seconds
Started Jun 11 03:04:59 PM PDT 24
Finished Jun 11 03:06:05 PM PDT 24
Peak memory 260728 kb
Host smart-0cb08492-f2ec-4415-be23-d903c8a381f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111571246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.4111571246
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2093979154
Short name T804
Test name
Test status
Simulation time 58709243200 ps
CPU time 240.13 seconds
Started Jun 11 03:04:57 PM PDT 24
Finished Jun 11 03:08:58 PM PDT 24
Peak memory 260664 kb
Host smart-80e6bf1f-0e84-44af-8bac-62ea462c0b3b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209
3979154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2093979154
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.3183148925
Short name T408
Test name
Test status
Simulation time 2109946700 ps
CPU time 70.44 seconds
Started Jun 11 03:04:47 PM PDT 24
Finished Jun 11 03:05:59 PM PDT 24
Peak memory 260720 kb
Host smart-c0c83747-313c-42d9-a661-34838e7be031
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183148925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3183148925
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.402754132
Short name T1034
Test name
Test status
Simulation time 25457400 ps
CPU time 13.38 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:21 PM PDT 24
Peak memory 265788 kb
Host smart-f239d5b3-8473-4f58-9d63-b7fa89bd3ad2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402754132 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.402754132
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3408885861
Short name T823
Test name
Test status
Simulation time 4494510100 ps
CPU time 182.31 seconds
Started Jun 11 03:04:47 PM PDT 24
Finished Jun 11 03:07:50 PM PDT 24
Peak memory 265432 kb
Host smart-49dd89ba-9ef7-458f-8d7d-6d2e271f32a9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408885861 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3408885861
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.1868036538
Short name T117
Test name
Test status
Simulation time 38075500 ps
CPU time 131.94 seconds
Started Jun 11 03:04:47 PM PDT 24
Finished Jun 11 03:07:00 PM PDT 24
Peak memory 265456 kb
Host smart-8b34256e-2b5b-493f-84db-0043b5d90719
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868036538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.1868036538
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1742942805
Short name T1060
Test name
Test status
Simulation time 115374000 ps
CPU time 354.66 seconds
Started Jun 11 03:04:49 PM PDT 24
Finished Jun 11 03:10:45 PM PDT 24
Peak memory 263456 kb
Host smart-dcda2078-dc65-4ac7-8aa9-a9b9e533eb60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742942805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1742942805
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.995491032
Short name T483
Test name
Test status
Simulation time 325525400 ps
CPU time 13.95 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:22 PM PDT 24
Peak memory 265476 kb
Host smart-25e88b90-7bc5-49cb-9938-18a9c93f2648
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995491032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_rese
t.995491032
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3650240402
Short name T112
Test name
Test status
Simulation time 114372800 ps
CPU time 443.17 seconds
Started Jun 11 03:04:35 PM PDT 24
Finished Jun 11 03:12:00 PM PDT 24
Peak memory 281120 kb
Host smart-d4696cdf-02c0-4561-9cff-72619462270a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650240402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3650240402
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.1625438415
Short name T172
Test name
Test status
Simulation time 1820288500 ps
CPU time 127.92 seconds
Started Jun 11 03:04:48 PM PDT 24
Finished Jun 11 03:06:57 PM PDT 24
Peak memory 282212 kb
Host smart-90f5e2fd-b0aa-49f1-b6ce-bbc4174d415d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625438415 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.1625438415
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3664916250
Short name T968
Test name
Test status
Simulation time 1268858800 ps
CPU time 151.21 seconds
Started Jun 11 03:04:58 PM PDT 24
Finished Jun 11 03:07:30 PM PDT 24
Peak memory 283480 kb
Host smart-b3161df3-753d-4e2a-bf93-ce68c4ebc0fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3664916250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3664916250
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.629592208
Short name T898
Test name
Test status
Simulation time 1064931300 ps
CPU time 179.94 seconds
Started Jun 11 03:04:47 PM PDT 24
Finished Jun 11 03:07:48 PM PDT 24
Peak memory 295276 kb
Host smart-34e418f6-610d-42d1-b5d9-1b519ac17da4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629592208 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.629592208
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3733799831
Short name T1056
Test name
Test status
Simulation time 76291700 ps
CPU time 31.02 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:39 PM PDT 24
Peak memory 270004 kb
Host smart-ac4b7d8c-6efc-421e-af3d-75c52b6c0633
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733799831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3733799831
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.919007473
Short name T110
Test name
Test status
Simulation time 33548200 ps
CPU time 31.65 seconds
Started Jun 11 03:05:07 PM PDT 24
Finished Jun 11 03:05:39 PM PDT 24
Peak memory 275376 kb
Host smart-696f9538-9bcf-4f41-9d0f-8ee1f0a79d51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919007473 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.919007473
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.2344622434
Short name T631
Test name
Test status
Simulation time 4849642100 ps
CPU time 664.84 seconds
Started Jun 11 03:04:57 PM PDT 24
Finished Jun 11 03:16:03 PM PDT 24
Peak memory 321020 kb
Host smart-532e1035-c7da-44ac-8b2d-2e78dc215f80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344622434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.2344622434
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3876827681
Short name T987
Test name
Test status
Simulation time 2682037000 ps
CPU time 143.86 seconds
Started Jun 11 03:04:37 PM PDT 24
Finished Jun 11 03:07:03 PM PDT 24
Peak memory 281124 kb
Host smart-339eb8f0-f537-4dd2-aa93-dafe235addba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876827681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3876827681
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.895700077
Short name T96
Test name
Test status
Simulation time 2437090900 ps
CPU time 195.15 seconds
Started Jun 11 03:04:47 PM PDT 24
Finished Jun 11 03:08:03 PM PDT 24
Peak memory 265504 kb
Host smart-5358add9-08a0-47f8-ac89-1d987874579f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895700077 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_wo.895700077
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.2171628421
Short name T662
Test name
Test status
Simulation time 66702200 ps
CPU time 13.5 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:15:16 PM PDT 24
Peak memory 284516 kb
Host smart-b0bc6cfb-be9e-40e6-b90d-3d73d9bc142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171628421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.2171628421
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2297600097
Short name T380
Test name
Test status
Simulation time 155726100 ps
CPU time 109.23 seconds
Started Jun 11 03:15:02 PM PDT 24
Finished Jun 11 03:16:53 PM PDT 24
Peak memory 260336 kb
Host smart-81330cb8-625c-4cef-8cee-31e1af831bd8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297600097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2297600097
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2201847989
Short name T535
Test name
Test status
Simulation time 13668700 ps
CPU time 15.96 seconds
Started Jun 11 03:15:11 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 275188 kb
Host smart-e908ac1c-3a49-44ea-8343-738e4c9ade5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201847989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2201847989
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.1961118423
Short name T132
Test name
Test status
Simulation time 132835200 ps
CPU time 131.55 seconds
Started Jun 11 03:15:01 PM PDT 24
Finished Jun 11 03:17:14 PM PDT 24
Peak memory 261316 kb
Host smart-f3b57177-0f68-4d72-97e1-1f62dff84043
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961118423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.1961118423
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3541034073
Short name T539
Test name
Test status
Simulation time 21606500 ps
CPU time 13.68 seconds
Started Jun 11 03:15:10 PM PDT 24
Finished Jun 11 03:15:25 PM PDT 24
Peak memory 275232 kb
Host smart-0ff66507-6142-4ffd-9641-f0d05a2e6a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541034073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3541034073
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3767203306
Short name T641
Test name
Test status
Simulation time 47927300 ps
CPU time 135.38 seconds
Started Jun 11 03:15:12 PM PDT 24
Finished Jun 11 03:17:28 PM PDT 24
Peak memory 260232 kb
Host smart-3f911631-899e-4649-83bb-5c14d3676a17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767203306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3767203306
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.2040318692
Short name T972
Test name
Test status
Simulation time 26929200 ps
CPU time 13.63 seconds
Started Jun 11 03:15:11 PM PDT 24
Finished Jun 11 03:15:26 PM PDT 24
Peak memory 284488 kb
Host smart-b6d4cb9a-402b-477f-9c60-b8b171616049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040318692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2040318692
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1799012232
Short name T657
Test name
Test status
Simulation time 43776700 ps
CPU time 132.06 seconds
Started Jun 11 03:15:11 PM PDT 24
Finished Jun 11 03:17:24 PM PDT 24
Peak memory 261472 kb
Host smart-a7ad7dff-b1bc-455f-9e65-cd3f42b41b2e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799012232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1799012232
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.3550937056
Short name T248
Test name
Test status
Simulation time 188820700 ps
CPU time 15.76 seconds
Started Jun 11 03:15:12 PM PDT 24
Finished Jun 11 03:15:29 PM PDT 24
Peak memory 275080 kb
Host smart-16393136-509c-416c-bc97-18010ee2d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550937056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.3550937056
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2759067417
Short name T314
Test name
Test status
Simulation time 84127600 ps
CPU time 132.67 seconds
Started Jun 11 03:15:12 PM PDT 24
Finished Jun 11 03:17:26 PM PDT 24
Peak memory 260528 kb
Host smart-813a6df8-eb4d-48b5-ad12-325f00b5ef31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759067417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2759067417
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.1334209519
Short name T540
Test name
Test status
Simulation time 15104700 ps
CPU time 15.8 seconds
Started Jun 11 03:15:10 PM PDT 24
Finished Jun 11 03:15:27 PM PDT 24
Peak memory 275200 kb
Host smart-b7340b80-c125-4169-b58d-8b6e7d828579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334209519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1334209519
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1831441255
Short name T129
Test name
Test status
Simulation time 136908300 ps
CPU time 135.83 seconds
Started Jun 11 03:15:12 PM PDT 24
Finished Jun 11 03:17:29 PM PDT 24
Peak memory 260420 kb
Host smart-90a0893f-0da4-4810-a26b-0e8b5d965a12
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831441255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1831441255
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.391566364
Short name T1052
Test name
Test status
Simulation time 13625000 ps
CPU time 15.93 seconds
Started Jun 11 03:15:11 PM PDT 24
Finished Jun 11 03:15:28 PM PDT 24
Peak memory 275276 kb
Host smart-ffe8395c-075b-42b0-a3a6-1b6bd8e01e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391566364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.391566364
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.2075882190
Short name T944
Test name
Test status
Simulation time 132274800 ps
CPU time 132.65 seconds
Started Jun 11 03:15:11 PM PDT 24
Finished Jun 11 03:17:24 PM PDT 24
Peak memory 260172 kb
Host smart-04135b29-4298-4075-93f6-63b3fb6ba971
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075882190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.2075882190
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1451447979
Short name T1012
Test name
Test status
Simulation time 15655000 ps
CPU time 15.75 seconds
Started Jun 11 03:15:12 PM PDT 24
Finished Jun 11 03:15:28 PM PDT 24
Peak memory 275108 kb
Host smart-3d2973ad-f0d7-4105-a7e1-3cbfc79c21e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451447979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1451447979
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.2713282027
Short name T505
Test name
Test status
Simulation time 43477700 ps
CPU time 134.49 seconds
Started Jun 11 03:15:08 PM PDT 24
Finished Jun 11 03:17:24 PM PDT 24
Peak memory 261348 kb
Host smart-97b119f2-71b7-4570-a436-16447144b2fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713282027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.2713282027
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.3460441750
Short name T896
Test name
Test status
Simulation time 25938900 ps
CPU time 15.68 seconds
Started Jun 11 03:15:22 PM PDT 24
Finished Jun 11 03:15:39 PM PDT 24
Peak memory 284428 kb
Host smart-2083083b-6577-4505-91e5-149f5afbbae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460441750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3460441750
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2785483612
Short name T752
Test name
Test status
Simulation time 17363700 ps
CPU time 13.17 seconds
Started Jun 11 03:15:21 PM PDT 24
Finished Jun 11 03:15:35 PM PDT 24
Peak memory 274872 kb
Host smart-cd48cb05-ab2a-442d-968c-2ad2f795b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785483612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2785483612
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.129614254
Short name T969
Test name
Test status
Simulation time 238208400 ps
CPU time 133.73 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:17:35 PM PDT 24
Peak memory 261328 kb
Host smart-bafa63a1-321f-4eec-a5c7-3419bb308e31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129614254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot
p_reset.129614254
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.2688842197
Short name T805
Test name
Test status
Simulation time 47552200 ps
CPU time 14.5 seconds
Started Jun 11 03:06:06 PM PDT 24
Finished Jun 11 03:06:21 PM PDT 24
Peak memory 258448 kb
Host smart-b8e086e2-1c7c-452e-a0db-eeb399e66728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688842197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.2
688842197
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2132190594
Short name T950
Test name
Test status
Simulation time 51538700 ps
CPU time 16.61 seconds
Started Jun 11 03:05:56 PM PDT 24
Finished Jun 11 03:06:13 PM PDT 24
Peak memory 275200 kb
Host smart-ce8d750e-2dc4-40e2-9e2e-af9603003251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132190594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2132190594
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.142935667
Short name T77
Test name
Test status
Simulation time 17460400 ps
CPU time 21.68 seconds
Started Jun 11 03:05:56 PM PDT 24
Finished Jun 11 03:06:18 PM PDT 24
Peak memory 274124 kb
Host smart-18a12e9c-56b9-4955-9a21-127239d8752d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142935667 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.142935667
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.145400877
Short name T914
Test name
Test status
Simulation time 23485982500 ps
CPU time 2270.84 seconds
Started Jun 11 03:05:37 PM PDT 24
Finished Jun 11 03:43:29 PM PDT 24
Peak memory 265240 kb
Host smart-a1d79c7b-56cd-49fb-81a0-f0ebc74f8457
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145400877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_erro
r_mp.145400877
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.95367358
Short name T876
Test name
Test status
Simulation time 3546949500 ps
CPU time 911.71 seconds
Started Jun 11 03:05:36 PM PDT 24
Finished Jun 11 03:20:49 PM PDT 24
Peak memory 273580 kb
Host smart-4a79bd33-a744-43b1-900e-82412cd6f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95367358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.95367358
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.4024868962
Short name T845
Test name
Test status
Simulation time 103009700 ps
CPU time 19.68 seconds
Started Jun 11 03:05:27 PM PDT 24
Finished Jun 11 03:05:48 PM PDT 24
Peak memory 263912 kb
Host smart-fdb8a005-2fbd-4541-bc81-3831427c5dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024868962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.4024868962
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2087636005
Short name T990
Test name
Test status
Simulation time 10013859500 ps
CPU time 109.98 seconds
Started Jun 11 03:06:06 PM PDT 24
Finished Jun 11 03:07:57 PM PDT 24
Peak memory 341324 kb
Host smart-87590083-5ca8-4bd5-9404-83f49cbc9f82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087636005 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2087636005
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.3130810952
Short name T157
Test name
Test status
Simulation time 84042700 ps
CPU time 13.47 seconds
Started Jun 11 03:06:06 PM PDT 24
Finished Jun 11 03:06:20 PM PDT 24
Peak memory 265224 kb
Host smart-bb50ec43-1d50-416c-8cf5-ad18415d4a4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130810952 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.3130810952
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3786549489
Short name T537
Test name
Test status
Simulation time 40122361700 ps
CPU time 821.35 seconds
Started Jun 11 03:05:27 PM PDT 24
Finished Jun 11 03:19:10 PM PDT 24
Peak memory 264524 kb
Host smart-5d5c16d1-01c1-4add-a3f3-58e8ff96944e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786549489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.3786549489
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1439230944
Short name T760
Test name
Test status
Simulation time 1866162800 ps
CPU time 49.34 seconds
Started Jun 11 03:05:27 PM PDT 24
Finished Jun 11 03:06:17 PM PDT 24
Peak memory 262852 kb
Host smart-2052ca00-9052-42aa-bc1e-445079f1eab9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439230944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1439230944
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.850133738
Short name T345
Test name
Test status
Simulation time 15388285100 ps
CPU time 177 seconds
Started Jun 11 03:05:46 PM PDT 24
Finished Jun 11 03:08:44 PM PDT 24
Peak memory 285380 kb
Host smart-aae9e272-49da-4ac2-b1ce-fb08e39f1bc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850133738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.850133738
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.762497660
Short name T754
Test name
Test status
Simulation time 23320061100 ps
CPU time 153.31 seconds
Started Jun 11 03:05:47 PM PDT 24
Finished Jun 11 03:08:21 PM PDT 24
Peak memory 292840 kb
Host smart-de0ce765-74fb-401f-b881-45c3ac1c2fa4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762497660 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.762497660
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.1055615204
Short name T778
Test name
Test status
Simulation time 42941532500 ps
CPU time 90.48 seconds
Started Jun 11 03:05:45 PM PDT 24
Finished Jun 11 03:07:16 PM PDT 24
Peak memory 260396 kb
Host smart-9b2a9a07-77f7-470c-bccf-588145f797e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055615204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.1055615204
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1786640462
Short name T831
Test name
Test status
Simulation time 73991269600 ps
CPU time 205.03 seconds
Started Jun 11 03:05:46 PM PDT 24
Finished Jun 11 03:09:12 PM PDT 24
Peak memory 260824 kb
Host smart-b8d46cdd-11c3-47df-a064-ed0c0c62fd75
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178
6640462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1786640462
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.956965895
Short name T882
Test name
Test status
Simulation time 41582529700 ps
CPU time 72.71 seconds
Started Jun 11 03:05:35 PM PDT 24
Finished Jun 11 03:06:49 PM PDT 24
Peak memory 260700 kb
Host smart-8c1c6003-6ee2-417a-a866-9d157ae53050
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956965895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.956965895
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1146841894
Short name T978
Test name
Test status
Simulation time 25114000 ps
CPU time 13.29 seconds
Started Jun 11 03:06:06 PM PDT 24
Finished Jun 11 03:06:20 PM PDT 24
Peak memory 260144 kb
Host smart-6752b649-5833-4368-8d1c-c569ba7b46ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146841894 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1146841894
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2774734255
Short name T86
Test name
Test status
Simulation time 11726691900 ps
CPU time 323.53 seconds
Started Jun 11 03:05:28 PM PDT 24
Finished Jun 11 03:10:53 PM PDT 24
Peak memory 274408 kb
Host smart-1afc661b-741c-4bbd-848a-ccb051d6682f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774734255 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2774734255
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1225675183
Short name T590
Test name
Test status
Simulation time 156488300 ps
CPU time 136.02 seconds
Started Jun 11 03:05:28 PM PDT 24
Finished Jun 11 03:07:45 PM PDT 24
Peak memory 261452 kb
Host smart-0129720a-1740-44aa-a545-410699b5435e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225675183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1225675183
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.135792325
Short name T1000
Test name
Test status
Simulation time 742299900 ps
CPU time 465.81 seconds
Started Jun 11 03:05:17 PM PDT 24
Finished Jun 11 03:13:04 PM PDT 24
Peak memory 263384 kb
Host smart-c80d27dd-16d9-4e48-996b-109fd3401c46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135792325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.135792325
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3631038979
Short name T471
Test name
Test status
Simulation time 61969000 ps
CPU time 13.34 seconds
Started Jun 11 03:05:47 PM PDT 24
Finished Jun 11 03:06:01 PM PDT 24
Peak memory 258908 kb
Host smart-3ac2fb7a-6ac3-4ec2-81cb-243ff00a6b75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631038979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3631038979
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3089272552
Short name T646
Test name
Test status
Simulation time 608648500 ps
CPU time 342.84 seconds
Started Jun 11 03:05:18 PM PDT 24
Finished Jun 11 03:11:02 PM PDT 24
Peak memory 278064 kb
Host smart-1164310a-23a5-4a1f-8dd5-1b6764d64ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089272552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3089272552
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.4054196452
Short name T701
Test name
Test status
Simulation time 564680900 ps
CPU time 36.36 seconds
Started Jun 11 03:05:57 PM PDT 24
Finished Jun 11 03:06:35 PM PDT 24
Peak memory 275716 kb
Host smart-136b483d-e089-4061-bd2e-283f67732fa1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054196452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.4054196452
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1235616011
Short name T779
Test name
Test status
Simulation time 4604901400 ps
CPU time 151.31 seconds
Started Jun 11 03:05:36 PM PDT 24
Finished Jun 11 03:08:08 PM PDT 24
Peak memory 282172 kb
Host smart-c67c934f-26bb-44fa-ac32-85de80f24898
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235616011 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1235616011
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1019328672
Short name T792
Test name
Test status
Simulation time 2509865400 ps
CPU time 138.09 seconds
Started Jun 11 03:05:38 PM PDT 24
Finished Jun 11 03:07:57 PM PDT 24
Peak memory 282288 kb
Host smart-b263a32c-bb63-4110-8381-4817d7d3b7a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1019328672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1019328672
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.3241377631
Short name T776
Test name
Test status
Simulation time 642943100 ps
CPU time 149.39 seconds
Started Jun 11 03:05:36 PM PDT 24
Finished Jun 11 03:08:07 PM PDT 24
Peak memory 282232 kb
Host smart-7d714d99-4990-4fee-bd9c-628200c472ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241377631 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3241377631
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.838728162
Short name T625
Test name
Test status
Simulation time 6200280900 ps
CPU time 498.65 seconds
Started Jun 11 03:05:38 PM PDT 24
Finished Jun 11 03:13:58 PM PDT 24
Peak memory 314820 kb
Host smart-434f0e74-bb96-4dfc-9bbf-ee2fcf499ad7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838728162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_rw.838728162
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.3736337874
Short name T895
Test name
Test status
Simulation time 2990614300 ps
CPU time 585.13 seconds
Started Jun 11 03:05:46 PM PDT 24
Finished Jun 11 03:15:32 PM PDT 24
Peak memory 330664 kb
Host smart-48657d63-cfcf-4dd2-b821-d01bffdd2636
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736337874 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.3736337874
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.721121532
Short name T30
Test name
Test status
Simulation time 74519400 ps
CPU time 30.15 seconds
Started Jun 11 03:05:56 PM PDT 24
Finished Jun 11 03:06:27 PM PDT 24
Peak memory 275680 kb
Host smart-704b825d-fded-4be0-90cf-b2472746490c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721121532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.721121532
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3153261275
Short name T328
Test name
Test status
Simulation time 95317800 ps
CPU time 32.04 seconds
Started Jun 11 03:05:57 PM PDT 24
Finished Jun 11 03:06:30 PM PDT 24
Peak memory 275144 kb
Host smart-27f579a2-96a0-416a-9660-f0e30152ca46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153261275 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3153261275
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.2595076915
Short name T399
Test name
Test status
Simulation time 2108351900 ps
CPU time 64.51 seconds
Started Jun 11 03:05:57 PM PDT 24
Finished Jun 11 03:07:02 PM PDT 24
Peak memory 259880 kb
Host smart-9127d0ac-d12c-40fe-b694-1b6178712dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595076915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2595076915
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.2432877685
Short name T809
Test name
Test status
Simulation time 17780400 ps
CPU time 147.61 seconds
Started Jun 11 03:05:17 PM PDT 24
Finished Jun 11 03:07:46 PM PDT 24
Peak memory 278144 kb
Host smart-beacaab7-af83-4e39-a3c3-4ce130496f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432877685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2432877685
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.860947121
Short name T565
Test name
Test status
Simulation time 151636000 ps
CPU time 13.41 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:15:34 PM PDT 24
Peak memory 284612 kb
Host smart-588e0d21-0ae6-458d-9488-2dfac6bc6321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860947121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.860947121
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1638074943
Short name T124
Test name
Test status
Simulation time 52217900 ps
CPU time 108.37 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:17:09 PM PDT 24
Peak memory 260456 kb
Host smart-7fba41db-9e1a-4ce1-a797-0df6e3f4f8a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638074943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1638074943
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2642704588
Short name T560
Test name
Test status
Simulation time 52858300 ps
CPU time 15.79 seconds
Started Jun 11 03:15:21 PM PDT 24
Finished Jun 11 03:15:38 PM PDT 24
Peak memory 284448 kb
Host smart-6a167f42-8fd9-4e89-9226-edd6a29706f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642704588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2642704588
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.2923205777
Short name T723
Test name
Test status
Simulation time 69233400 ps
CPU time 110.47 seconds
Started Jun 11 03:15:18 PM PDT 24
Finished Jun 11 03:17:10 PM PDT 24
Peak memory 260196 kb
Host smart-00313230-c4fb-48c1-8159-21d6d36d3efc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923205777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.2923205777
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.328077219
Short name T306
Test name
Test status
Simulation time 26095400 ps
CPU time 15.8 seconds
Started Jun 11 03:15:24 PM PDT 24
Finished Jun 11 03:15:40 PM PDT 24
Peak memory 284604 kb
Host smart-8d787672-620e-4cd5-aac6-a599e87bc175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328077219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.328077219
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2809949487
Short name T694
Test name
Test status
Simulation time 83632100 ps
CPU time 133.52 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:17:34 PM PDT 24
Peak memory 260488 kb
Host smart-88b978ff-8695-4769-86e1-71bb8ca5feef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809949487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2809949487
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3551455434
Short name T841
Test name
Test status
Simulation time 25829600 ps
CPU time 13.18 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:15:34 PM PDT 24
Peak memory 274976 kb
Host smart-82b60367-2357-4d6c-b912-8260f6c9c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551455434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3551455434
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.827497336
Short name T661
Test name
Test status
Simulation time 69479300 ps
CPU time 107.16 seconds
Started Jun 11 03:15:23 PM PDT 24
Finished Jun 11 03:17:11 PM PDT 24
Peak memory 260148 kb
Host smart-504dd29d-1e20-4005-a357-452ec1ad60f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827497336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_ot
p_reset.827497336
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1676558302
Short name T1062
Test name
Test status
Simulation time 14006300 ps
CPU time 15.86 seconds
Started Jun 11 03:15:22 PM PDT 24
Finished Jun 11 03:15:39 PM PDT 24
Peak memory 275088 kb
Host smart-3c559cde-828f-4773-9582-0794c231ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676558302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1676558302
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3598457844
Short name T442
Test name
Test status
Simulation time 85171500 ps
CPU time 131.46 seconds
Started Jun 11 03:15:24 PM PDT 24
Finished Jun 11 03:17:36 PM PDT 24
Peak memory 260336 kb
Host smart-a8ab9ea0-4eb0-43db-8ee9-d02c2c3ae784
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598457844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3598457844
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.3231802642
Short name T1058
Test name
Test status
Simulation time 164523500 ps
CPU time 15.79 seconds
Started Jun 11 03:15:21 PM PDT 24
Finished Jun 11 03:15:39 PM PDT 24
Peak memory 275100 kb
Host smart-33a37239-cef2-4ee8-92ba-c55f259fabbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231802642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3231802642
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.3375783930
Short name T812
Test name
Test status
Simulation time 276458100 ps
CPU time 130.54 seconds
Started Jun 11 03:15:20 PM PDT 24
Finished Jun 11 03:17:31 PM PDT 24
Peak memory 260308 kb
Host smart-cf236d0d-568c-4d55-9ce3-b4e36cdf2877
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375783930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.3375783930
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.1192469006
Short name T311
Test name
Test status
Simulation time 12866400 ps
CPU time 15.82 seconds
Started Jun 11 03:15:21 PM PDT 24
Finished Jun 11 03:15:38 PM PDT 24
Peak memory 284636 kb
Host smart-1fe8fabb-c78e-470c-a31b-f8106379d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192469006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1192469006
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1800149894
Short name T312
Test name
Test status
Simulation time 134405600 ps
CPU time 107.67 seconds
Started Jun 11 03:15:22 PM PDT 24
Finished Jun 11 03:17:11 PM PDT 24
Peak memory 262724 kb
Host smart-d0a1324f-d396-4a8b-bcdc-65870d51073e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800149894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1800149894
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.3301159871
Short name T1080
Test name
Test status
Simulation time 13117400 ps
CPU time 15.81 seconds
Started Jun 11 03:15:21 PM PDT 24
Finished Jun 11 03:15:37 PM PDT 24
Peak memory 284628 kb
Host smart-1550ffe8-b6e2-485e-a2be-0c74c6f018ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301159871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.3301159871
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3332634303
Short name T585
Test name
Test status
Simulation time 19612900 ps
CPU time 13.21 seconds
Started Jun 11 03:15:30 PM PDT 24
Finished Jun 11 03:15:45 PM PDT 24
Peak memory 275096 kb
Host smart-5e014e7e-34b9-43f3-8a68-bcc5b812c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332634303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3332634303
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.1282855920
Short name T675
Test name
Test status
Simulation time 138373900 ps
CPU time 133.49 seconds
Started Jun 11 03:15:29 PM PDT 24
Finished Jun 11 03:17:44 PM PDT 24
Peak memory 260420 kb
Host smart-441f81ba-d022-4a71-a83f-f486db5afcbd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282855920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.1282855920
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.1522160993
Short name T1014
Test name
Test status
Simulation time 124300000 ps
CPU time 16.09 seconds
Started Jun 11 03:15:31 PM PDT 24
Finished Jun 11 03:15:48 PM PDT 24
Peak memory 275088 kb
Host smart-e57576ea-b515-45c2-8ffd-584e37903d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522160993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1522160993
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.4207442557
Short name T758
Test name
Test status
Simulation time 140602500 ps
CPU time 109.33 seconds
Started Jun 11 03:15:30 PM PDT 24
Finished Jun 11 03:17:21 PM PDT 24
Peak memory 261300 kb
Host smart-f9db803e-e9cc-4063-922d-48688838b1c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207442557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.4207442557
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3849920927
Short name T459
Test name
Test status
Simulation time 22496000 ps
CPU time 13.34 seconds
Started Jun 11 03:06:44 PM PDT 24
Finished Jun 11 03:06:59 PM PDT 24
Peak memory 258740 kb
Host smart-a17efb35-6d07-4b4c-97aa-56371e07471c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849920927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
849920927
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2477866799
Short name T467
Test name
Test status
Simulation time 53606600 ps
CPU time 13.89 seconds
Started Jun 11 03:06:47 PM PDT 24
Finished Jun 11 03:07:04 PM PDT 24
Peak memory 274980 kb
Host smart-d4cc1084-8568-4a61-b94e-d103eadf5046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477866799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2477866799
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2759489856
Short name T963
Test name
Test status
Simulation time 4051143700 ps
CPU time 2170.44 seconds
Started Jun 11 03:06:17 PM PDT 24
Finished Jun 11 03:42:29 PM PDT 24
Peak memory 265544 kb
Host smart-8b2b2c52-bd1c-4b67-b58a-990b1a0dfec2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759489856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.2759489856
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3407473988
Short name T691
Test name
Test status
Simulation time 3663863600 ps
CPU time 1087.23 seconds
Started Jun 11 03:06:16 PM PDT 24
Finished Jun 11 03:24:25 PM PDT 24
Peak memory 270736 kb
Host smart-b43b87f0-766f-4692-b320-2d928703c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407473988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3407473988
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2910882299
Short name T576
Test name
Test status
Simulation time 2419888500 ps
CPU time 29.16 seconds
Started Jun 11 03:06:17 PM PDT 24
Finished Jun 11 03:06:47 PM PDT 24
Peak memory 262832 kb
Host smart-57466d04-cf6c-452d-83c2-29656e469fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910882299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2910882299
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3871408380
Short name T879
Test name
Test status
Simulation time 10012091100 ps
CPU time 102.43 seconds
Started Jun 11 03:06:45 PM PDT 24
Finished Jun 11 03:08:31 PM PDT 24
Peak memory 284608 kb
Host smart-5f733d8c-a1eb-49d3-a967-dd5d21d18080
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871408380 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3871408380
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.908983163
Short name T799
Test name
Test status
Simulation time 75053400 ps
CPU time 13.41 seconds
Started Jun 11 03:06:44 PM PDT 24
Finished Jun 11 03:07:00 PM PDT 24
Peak memory 258884 kb
Host smart-455dfb36-8c81-4ce8-9cd8-ca5b76f3b104
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908983163 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.908983163
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1385055013
Short name T871
Test name
Test status
Simulation time 80141531900 ps
CPU time 879.22 seconds
Started Jun 11 03:06:04 PM PDT 24
Finished Jun 11 03:20:45 PM PDT 24
Peak memory 264612 kb
Host smart-bdd8202f-4619-4072-bc8b-c86aed0c6b7f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385055013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.1385055013
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2618008270
Short name T434
Test name
Test status
Simulation time 5015876700 ps
CPU time 158.27 seconds
Started Jun 11 03:06:07 PM PDT 24
Finished Jun 11 03:08:46 PM PDT 24
Peak memory 263244 kb
Host smart-aeb2e485-d891-4c7a-ad6c-257d54f87814
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618008270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2618008270
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2829058122
Short name T744
Test name
Test status
Simulation time 1151484100 ps
CPU time 143.2 seconds
Started Jun 11 03:06:25 PM PDT 24
Finished Jun 11 03:08:49 PM PDT 24
Peak memory 291320 kb
Host smart-4307ddec-3a8f-4926-a943-e26fc7201883
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829058122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2829058122
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1798225500
Short name T928
Test name
Test status
Simulation time 11684336700 ps
CPU time 288.51 seconds
Started Jun 11 03:06:26 PM PDT 24
Finished Jun 11 03:11:15 PM PDT 24
Peak memory 292620 kb
Host smart-b6b15956-3894-48a4-8041-3fc5b7f3c544
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798225500 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1798225500
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.3429597652
Short name T980
Test name
Test status
Simulation time 12881158400 ps
CPU time 80.96 seconds
Started Jun 11 03:06:25 PM PDT 24
Finished Jun 11 03:07:47 PM PDT 24
Peak memory 260908 kb
Host smart-873429e7-f5e9-4755-a3b2-961c2e44bd61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429597652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.3429597652
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3858902023
Short name T877
Test name
Test status
Simulation time 21366930800 ps
CPU time 163.6 seconds
Started Jun 11 03:06:24 PM PDT 24
Finished Jun 11 03:09:09 PM PDT 24
Peak memory 260052 kb
Host smart-6b3df230-9045-4436-84ed-8e79fae84925
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385
8902023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3858902023
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.1757626001
Short name T629
Test name
Test status
Simulation time 1635637100 ps
CPU time 69.72 seconds
Started Jun 11 03:06:18 PM PDT 24
Finished Jun 11 03:07:29 PM PDT 24
Peak memory 260828 kb
Host smart-364c5e43-fb4c-4a79-8a66-7a15bbf37902
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757626001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1757626001
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.33540725
Short name T939
Test name
Test status
Simulation time 15551300 ps
CPU time 13.34 seconds
Started Jun 11 03:06:45 PM PDT 24
Finished Jun 11 03:07:01 PM PDT 24
Peak memory 265096 kb
Host smart-4a7a85df-909c-459f-a8ed-5701c26d30a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33540725 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.33540725
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2180974281
Short name T858
Test name
Test status
Simulation time 15364373900 ps
CPU time 594.91 seconds
Started Jun 11 03:06:16 PM PDT 24
Finished Jun 11 03:16:12 PM PDT 24
Peak memory 274576 kb
Host smart-62fe305e-27b3-4a5c-8e2f-9f95442b013e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180974281 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2180974281
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.2190239981
Short name T635
Test name
Test status
Simulation time 370218600 ps
CPU time 133.65 seconds
Started Jun 11 03:06:18 PM PDT 24
Finished Jun 11 03:08:33 PM PDT 24
Peak memory 260312 kb
Host smart-6753bd27-84f5-42c9-9df6-4c715dd040d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190239981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.2190239981
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3772600911
Short name T899
Test name
Test status
Simulation time 75792800 ps
CPU time 152.54 seconds
Started Jun 11 03:06:07 PM PDT 24
Finished Jun 11 03:08:40 PM PDT 24
Peak memory 263560 kb
Host smart-c6eff310-9d64-43e3-8aeb-5496134b9aaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772600911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3772600911
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.2475873864
Short name T729
Test name
Test status
Simulation time 125968000 ps
CPU time 13.42 seconds
Started Jun 11 03:06:27 PM PDT 24
Finished Jun 11 03:06:41 PM PDT 24
Peak memory 258924 kb
Host smart-a13eb446-55f7-4c0f-89c7-240aee85061d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475873864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.2475873864
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3489717823
Short name T916
Test name
Test status
Simulation time 375971200 ps
CPU time 174.13 seconds
Started Jun 11 03:06:06 PM PDT 24
Finished Jun 11 03:09:01 PM PDT 24
Peak memory 272020 kb
Host smart-3a0d5f05-7216-497d-a20e-a7e4b1888956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489717823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3489717823
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.3931541129
Short name T282
Test name
Test status
Simulation time 237999200 ps
CPU time 34.69 seconds
Started Jun 11 03:06:35 PM PDT 24
Finished Jun 11 03:07:11 PM PDT 24
Peak memory 275736 kb
Host smart-9eb1e72c-434c-46b5-9df7-5a26f6b518df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931541129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.3931541129
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.931214149
Short name T965
Test name
Test status
Simulation time 1880118600 ps
CPU time 136.52 seconds
Started Jun 11 03:06:15 PM PDT 24
Finished Jun 11 03:08:33 PM PDT 24
Peak memory 289540 kb
Host smart-d97fa6a4-908b-44bb-adab-408da0941bdb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931214149 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.931214149
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2272642793
Short name T188
Test name
Test status
Simulation time 4679784100 ps
CPU time 208.62 seconds
Started Jun 11 03:06:25 PM PDT 24
Finished Jun 11 03:09:54 PM PDT 24
Peak memory 290448 kb
Host smart-1535ca4e-c997-426e-83e6-4dacb7755ddf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2272642793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2272642793
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.2254655913
Short name T503
Test name
Test status
Simulation time 1978285100 ps
CPU time 134.87 seconds
Started Jun 11 03:06:25 PM PDT 24
Finished Jun 11 03:08:41 PM PDT 24
Peak memory 282240 kb
Host smart-4d589326-3cd4-40e6-9ce5-ced944bc8215
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254655913 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.2254655913
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.2245730294
Short name T1002
Test name
Test status
Simulation time 5752120800 ps
CPU time 749.4 seconds
Started Jun 11 03:06:32 PM PDT 24
Finished Jun 11 03:19:03 PM PDT 24
Peak memory 336152 kb
Host smart-f7ab3625-653b-4040-8f8b-7d238f4f5ed9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245730294 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.2245730294
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.3293047284
Short name T1046
Test name
Test status
Simulation time 55413600 ps
CPU time 30.68 seconds
Started Jun 11 03:06:35 PM PDT 24
Finished Jun 11 03:07:07 PM PDT 24
Peak memory 275688 kb
Host smart-808814ca-68aa-4bce-bdaf-01d6ba281ed1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293047284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.3293047284
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2701498007
Short name T737
Test name
Test status
Simulation time 208653800 ps
CPU time 30.83 seconds
Started Jun 11 03:06:38 PM PDT 24
Finished Jun 11 03:07:09 PM PDT 24
Peak memory 267776 kb
Host smart-e6fd792f-69ed-4d9b-a484-c53171f6990e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701498007 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.2701498007
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.1448114001
Short name T923
Test name
Test status
Simulation time 3063342300 ps
CPU time 565.94 seconds
Started Jun 11 03:06:25 PM PDT 24
Finished Jun 11 03:15:52 PM PDT 24
Peak memory 321252 kb
Host smart-6fd51399-1ef4-4291-b8dd-2762cb9c8461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448114001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.1448114001
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1983426012
Short name T401
Test name
Test status
Simulation time 726569900 ps
CPU time 59.89 seconds
Started Jun 11 03:06:46 PM PDT 24
Finished Jun 11 03:07:49 PM PDT 24
Peak memory 263980 kb
Host smart-d2d25d67-1935-4c3d-947e-a5542660a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983426012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1983426012
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3176520190
Short name T1061
Test name
Test status
Simulation time 183286200 ps
CPU time 74.89 seconds
Started Jun 11 03:06:07 PM PDT 24
Finished Jun 11 03:07:23 PM PDT 24
Peak memory 275812 kb
Host smart-68a9d892-cdbe-45c6-9f09-97e8ba5eb215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176520190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3176520190
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.2679316196
Short name T688
Test name
Test status
Simulation time 4346116300 ps
CPU time 194.54 seconds
Started Jun 11 03:06:15 PM PDT 24
Finished Jun 11 03:09:31 PM PDT 24
Peak memory 265720 kb
Host smart-49e2d331-605b-410f-8f8c-043c2e186bb1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679316196 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.2679316196
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2762162386
Short name T430
Test name
Test status
Simulation time 29880200 ps
CPU time 13.69 seconds
Started Jun 11 03:07:31 PM PDT 24
Finished Jun 11 03:07:47 PM PDT 24
Peak memory 265492 kb
Host smart-467b6eb5-59d4-4c92-ae14-73c89478afe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762162386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
762162386
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.914459613
Short name T942
Test name
Test status
Simulation time 88835700 ps
CPU time 16.1 seconds
Started Jun 11 03:07:23 PM PDT 24
Finished Jun 11 03:07:40 PM PDT 24
Peak memory 275056 kb
Host smart-9a4c3c92-d3ac-43bd-b0b6-d2638b778c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914459613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.914459613
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2626331950
Short name T375
Test name
Test status
Simulation time 17255500 ps
CPU time 21.7 seconds
Started Jun 11 03:07:21 PM PDT 24
Finished Jun 11 03:07:44 PM PDT 24
Peak memory 265836 kb
Host smart-f7b77f1a-92ce-4c42-8275-cee04e5d827a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626331950 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2626331950
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.2665891203
Short name T893
Test name
Test status
Simulation time 43601209900 ps
CPU time 2594.78 seconds
Started Jun 11 03:07:03 PM PDT 24
Finished Jun 11 03:50:19 PM PDT 24
Peak memory 265500 kb
Host smart-d9b6fb08-db57-4677-913a-848481fae3ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665891203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.2665891203
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2871082670
Short name T296
Test name
Test status
Simulation time 7279085900 ps
CPU time 793.5 seconds
Started Jun 11 03:07:04 PM PDT 24
Finished Jun 11 03:20:19 PM PDT 24
Peak memory 273764 kb
Host smart-9cc26c9e-a8cd-4fc7-8dc6-674e823b6109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871082670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2871082670
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3466111308
Short name T49
Test name
Test status
Simulation time 350615700 ps
CPU time 28.22 seconds
Started Jun 11 03:07:06 PM PDT 24
Finished Jun 11 03:07:35 PM PDT 24
Peak memory 262908 kb
Host smart-3f567d8e-50e8-4315-83cc-117df22ef46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466111308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3466111308
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3116900772
Short name T162
Test name
Test status
Simulation time 10034710200 ps
CPU time 103.17 seconds
Started Jun 11 03:07:31 PM PDT 24
Finished Jun 11 03:09:16 PM PDT 24
Peak memory 274656 kb
Host smart-29f3590c-53ec-4a9f-a027-3bb5277eb89d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116900772 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3116900772
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.244620125
Short name T114
Test name
Test status
Simulation time 15072300 ps
CPU time 13.38 seconds
Started Jun 11 03:07:31 PM PDT 24
Finished Jun 11 03:07:46 PM PDT 24
Peak memory 265744 kb
Host smart-ad0ee197-5fe5-4f20-95dd-751d4ec9a160
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244620125 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.244620125
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.265635579
Short name T26
Test name
Test status
Simulation time 110166169200 ps
CPU time 963.17 seconds
Started Jun 11 03:06:55 PM PDT 24
Finished Jun 11 03:22:59 PM PDT 24
Peak memory 264572 kb
Host smart-8f9d5c1d-a250-48cf-bf50-052041bd2d15
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265635579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.flash_ctrl_hw_rma_reset.265635579
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1334241735
Short name T617
Test name
Test status
Simulation time 2792325200 ps
CPU time 213.07 seconds
Started Jun 11 03:06:54 PM PDT 24
Finished Jun 11 03:10:28 PM PDT 24
Peak memory 263376 kb
Host smart-ed234ea3-1c84-48da-8039-b6cee6dd0f79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334241735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1334241735
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.2665746641
Short name T61
Test name
Test status
Simulation time 1787311600 ps
CPU time 232.8 seconds
Started Jun 11 03:07:14 PM PDT 24
Finished Jun 11 03:11:08 PM PDT 24
Peak memory 285360 kb
Host smart-c676bc49-89ed-46c8-a7e2-290e94f0c5c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665746641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.2665746641
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.967967748
Short name T572
Test name
Test status
Simulation time 73793187200 ps
CPU time 225.08 seconds
Started Jun 11 03:07:13 PM PDT 24
Finished Jun 11 03:10:59 PM PDT 24
Peak memory 292328 kb
Host smart-52a1865c-0576-4bad-891d-dc8a431cd5a7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967967748 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.967967748
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.1890162020
Short name T1036
Test name
Test status
Simulation time 5684489900 ps
CPU time 69.81 seconds
Started Jun 11 03:07:16 PM PDT 24
Finished Jun 11 03:08:27 PM PDT 24
Peak memory 265428 kb
Host smart-dc41c4d3-02f3-4291-9e8f-2f54b7a20b88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890162020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.1890162020
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3283171543
Short name T904
Test name
Test status
Simulation time 89111317800 ps
CPU time 203.93 seconds
Started Jun 11 03:07:14 PM PDT 24
Finished Jun 11 03:10:39 PM PDT 24
Peak memory 260592 kb
Host smart-1fde57fe-f89b-4948-832e-83fcd2687cec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328
3171543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3283171543
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.4079945534
Short name T409
Test name
Test status
Simulation time 1739206600 ps
CPU time 61.81 seconds
Started Jun 11 03:07:07 PM PDT 24
Finished Jun 11 03:08:09 PM PDT 24
Peak memory 260936 kb
Host smart-287eddb4-9196-4d72-8ddb-f27c9f1ac83b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079945534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.4079945534
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1576091653
Short name T551
Test name
Test status
Simulation time 28850200 ps
CPU time 13.46 seconds
Started Jun 11 03:07:32 PM PDT 24
Finished Jun 11 03:07:47 PM PDT 24
Peak memory 265320 kb
Host smart-e7dac829-ded7-403c-85f5-639c18a8155a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576091653 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1576091653
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.186395903
Short name T109
Test name
Test status
Simulation time 12947696300 ps
CPU time 552.89 seconds
Started Jun 11 03:07:06 PM PDT 24
Finished Jun 11 03:16:20 PM PDT 24
Peak memory 274980 kb
Host smart-6834bb2a-6c52-44e4-90f9-8c610d8d17c1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186395903 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_mp_regions.186395903
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.718408699
Short name T28
Test name
Test status
Simulation time 40626000 ps
CPU time 110.61 seconds
Started Jun 11 03:07:04 PM PDT 24
Finished Jun 11 03:08:56 PM PDT 24
Peak memory 261236 kb
Host smart-811b88bb-49e7-48f3-9762-6a95cd0e1615
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718408699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.718408699
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2683999535
Short name T225
Test name
Test status
Simulation time 41362700 ps
CPU time 149.46 seconds
Started Jun 11 03:06:54 PM PDT 24
Finished Jun 11 03:09:25 PM PDT 24
Peak memory 263424 kb
Host smart-8fe86a47-4a2e-41f6-b14c-376182198a6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683999535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2683999535
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1673978951
Short name T912
Test name
Test status
Simulation time 49906600 ps
CPU time 15.48 seconds
Started Jun 11 03:07:14 PM PDT 24
Finished Jun 11 03:07:31 PM PDT 24
Peak memory 259008 kb
Host smart-ca35a267-1082-430c-bb01-7e4c75a0c47e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673978951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1673978951
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.991404998
Short name T637
Test name
Test status
Simulation time 30793700 ps
CPU time 123.39 seconds
Started Jun 11 03:06:55 PM PDT 24
Finished Jun 11 03:09:00 PM PDT 24
Peak memory 277660 kb
Host smart-ae2e4936-dd48-4213-8438-1aef3466a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991404998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.991404998
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.4050591038
Short name T489
Test name
Test status
Simulation time 85169600 ps
CPU time 33.5 seconds
Started Jun 11 03:07:23 PM PDT 24
Finished Jun 11 03:07:57 PM PDT 24
Peak memory 270512 kb
Host smart-d3d28590-a1ee-4de7-9afa-2fe69d467e9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050591038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.4050591038
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3746691156
Short name T976
Test name
Test status
Simulation time 1021494600 ps
CPU time 117.52 seconds
Started Jun 11 03:07:05 PM PDT 24
Finished Jun 11 03:09:04 PM PDT 24
Peak memory 281272 kb
Host smart-b7727e7a-1f36-4d73-8746-2f6aa57d9c1b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746691156 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3746691156
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.1821088207
Short name T189
Test name
Test status
Simulation time 2394362200 ps
CPU time 156.42 seconds
Started Jun 11 03:07:16 PM PDT 24
Finished Jun 11 03:09:53 PM PDT 24
Peak memory 282968 kb
Host smart-ed6bd4de-ac2f-4bb4-8605-9ee90f785274
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1821088207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1821088207
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.821193824
Short name T583
Test name
Test status
Simulation time 748398100 ps
CPU time 190.87 seconds
Started Jun 11 03:07:07 PM PDT 24
Finished Jun 11 03:10:19 PM PDT 24
Peak memory 282176 kb
Host smart-f2d49cb1-9fbb-437c-ad7f-34414a209fc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821193824 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.821193824
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3088670600
Short name T959
Test name
Test status
Simulation time 17745292800 ps
CPU time 501.87 seconds
Started Jun 11 03:07:06 PM PDT 24
Finished Jun 11 03:15:28 PM PDT 24
Peak memory 314956 kb
Host smart-f00f55c2-62ac-4f86-b37a-2a0a137d916e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088670600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.3088670600
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3483135218
Short name T930
Test name
Test status
Simulation time 4224673900 ps
CPU time 536.39 seconds
Started Jun 11 03:07:14 PM PDT 24
Finished Jun 11 03:16:12 PM PDT 24
Peak memory 317460 kb
Host smart-a6477086-e0fc-43af-a6f7-d04fc4a2b3f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483135218 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.3483135218
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1278519385
Short name T755
Test name
Test status
Simulation time 30751500 ps
CPU time 28.56 seconds
Started Jun 11 03:07:22 PM PDT 24
Finished Jun 11 03:07:52 PM PDT 24
Peak memory 267848 kb
Host smart-7343b7d9-e098-4fe0-bce9-3fe1eac39882
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278519385 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.1278519385
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1826178298
Short name T390
Test name
Test status
Simulation time 466300900 ps
CPU time 67.82 seconds
Started Jun 11 03:07:24 PM PDT 24
Finished Jun 11 03:08:32 PM PDT 24
Peak memory 263316 kb
Host smart-a8f013a2-3111-47cc-8076-bf65860e5bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826178298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1826178298
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2588548400
Short name T938
Test name
Test status
Simulation time 254609400 ps
CPU time 53.04 seconds
Started Jun 11 03:06:45 PM PDT 24
Finished Jun 11 03:07:41 PM PDT 24
Peak memory 271496 kb
Host smart-00200ceb-6f64-4bbb-9c34-d9edfe1ce152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588548400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2588548400
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1588392848
Short name T95
Test name
Test status
Simulation time 4743778100 ps
CPU time 178.26 seconds
Started Jun 11 03:07:05 PM PDT 24
Finished Jun 11 03:10:04 PM PDT 24
Peak memory 260288 kb
Host smart-acd9fadf-85f8-48db-92bb-7d3a5f0969a5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588392848 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.1588392848
Directory /workspace/9.flash_ctrl_wo/latest
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