Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	258426	1		T1	1		T2	2		T3	2
all_values[1]	258426	1		T1	1		T2	2		T3	2
all_values[2]	258426	1		T1	1		T2	2		T3	2
all_values[3]	258426	1		T1	1		T2	2		T3	2
all_values[4]	258426	1		T1	1		T2	2		T3	2
all_values[5]	258426	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	523048	1		T1	6		T2	12		T3	12
auto[1]	1027508	1		T6	16864		T27	5776		T35	12756

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	757809	1		T1	4		T2	6		T3	7
auto[1]	792747	1		T1	2		T2	6		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	258262	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	164	1		T256	3		T257	4		T258	1
all_values[1]	auto[0]	auto[1]	258276	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	150	1		T256	2		T257	1		T258	4
all_values[2]	auto[0]	auto[0]	1569	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	59	1		T256	1		T258	1		T298	2
all_values[2]	auto[1]	auto[0]	256749	1		T6	4216		T27	1444		T35	3189
all_values[2]	auto[1]	auto[1]	49	1		T256	1		T257	3		T298	2
all_values[3]	auto[0]	auto[0]	1568	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	57	1		T256	1		T257	2		T258	1
all_values[3]	auto[1]	auto[0]	77688	1		T6	85		T27	1444		T35	1594
all_values[3]	auto[1]	auto[1]	179113	1		T6	4131		T35	1595		T38	1598
all_values[4]	auto[0]	auto[0]	1093	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	525	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	160920	1		T6	3642		T27	1		T35	1594
all_values[4]	auto[1]	auto[1]	95888	1		T6	574		T27	1443		T35	1595
all_values[5]	auto[0]	auto[0]	1492	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	147	1		T2	1		T21	1		T39	1
all_values[5]	auto[1]	auto[0]	256730	1		T6	4216		T27	1444		T35	3189
all_values[5]	auto[1]	auto[1]	57	1		T258	1		T297	1		T298	5