Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	245322	1		T2	1531		T3	2007		T4	1
auto[FlashEraseBank]	268036	1		T2	1664		T3	1637		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	251813	1		T2	1085		T3	1502		T4	1
auto[FlashOpProgram]	241150	1		T2	2110		T3	2142		T4	1
auto[FlashOpErase]	16395	1		T4	1		T24	56		T34	5
auto[FlashOpInvalid]	4000	1		T69	200		T127	200		T197	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	251813	1		T2	1085		T3	1502		T4	1
op[FlashOpProgram]	241150	1		T2	2110		T3	2142		T4	1
op[FlashOpErase]	16395	1		T4	1		T24	56		T34	5
read_erase_read	582	1		T24	4		T34	2		T42	2
read_prog_read	797	1		T2	10		T3	12		T24	2

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	370458	1		T2	2734		T3	3112		T4	3
auto[FlashPartInfo]	139622	1		T2	440		T3	514		T6	574
auto[FlashPartInfo1]	761	1		T2	2		T3	1		T21	2
auto[FlashPartInfo2]	2517	1		T2	19		T3	17		T21	6

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179271	1		T2	807		T3	1201		T4	1
auto[FlashPartData]	auto[FlashOpProgram]	183401	1		T2	1927		T3	1911		T4	1
auto[FlashPartData]	auto[FlashOpErase]	3866	1		T4	1		T24	30		T15	10
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T69	200		T127	196		T197	196
auto[FlashPartInfo]	auto[FlashOpRead]	70373	1		T2	267		T3	286		T6	574
auto[FlashPartInfo]	auto[FlashOpProgram]	56684	1		T2	173		T3	228		T26	1
auto[FlashPartInfo]	auto[FlashOpErase]	12501	1		T24	26		T34	5		T42	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	64	1		T127	4		T197	4		T198	8
auto[FlashPartInfo1]	auto[FlashOpRead]	589	1		T2	2		T3	1		T21	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T23	32		T115	32		T117	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T136	1		T118	1		T382	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T136	2		T118	2		T382	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1580	1		T2	9		T3	14		T21	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	902	1		T2	10		T3	3		T23	64
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T208	1		T139	1		T140	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T383	2		T384	4		T385	2