Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31691	1		T24	12		T34	4		T56	1
auto[1]	8	1		T316	1		T317	1		T318	2
auto[2]	31	1		T130	2		T143	4		T192	1
auto[3]	54	1		T28	4		T29	1		T319	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7950	1		T24	3		T34	1		T28	1
evic_idx[1]	7950	1		T24	3		T34	1		T56	1
evic_idx[2]	7941	1		T24	3		T34	1		T28	1
evic_idx[3]	7943	1		T24	3		T34	1		T28	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30819	1		T83	120		T61	16		T84	344
evic_op[2]	352	1		T34	4		T56	1		T28	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[2]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[3]]	[evic_op[1]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7699	1		T83	30		T61	4		T84	86
evic_idx[0]	evic_op[1]	auto[2]	2	1		T320	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	4	1		T321	4		-	-		-	-
evic_idx[0]	evic_op[2]	auto[0]	75	1		T34	1		T61	4		T250	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T318	1		T194	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T130	1		T192	1		T193	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T28	1		T319	1		T322	1
evic_idx[1]	evic_op[1]	auto[0]	7702	1		T83	30		T61	4		T84	86
evic_idx[1]	evic_op[1]	auto[2]	2	1		T320	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	4	1		T321	4		-	-		-	-
evic_idx[1]	evic_op[2]	auto[0]	75	1		T34	1		T56	1		T61	4
evic_idx[1]	evic_op[2]	auto[1]	2	1		T318	1		T194	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T28	1		T319	1		T187	1
evic_idx[2]	evic_op[1]	auto[0]	7699	1		T83	30		T61	4		T84	86
evic_idx[2]	evic_op[1]	auto[3]	2	1		T321	2		-	-		-	-
evic_idx[2]	evic_op[2]	auto[0]	72	1		T34	1		T61	4		T250	4
evic_idx[2]	evic_op[2]	auto[1]	3	1		T316	1		T317	1		T193	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T323	1		T324	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T28	1		T29	1		T192	1
evic_idx[3]	evic_op[1]	auto[0]	7701	1		T83	30		T61	4		T84	86
evic_idx[3]	evic_op[1]	auto[2]	1	1		T325	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	3	1		T321	3		-	-		-	-
evic_idx[3]	evic_op[2]	auto[0]	75	1		T34	1		T61	4		T250	4
evic_idx[3]	evic_op[2]	auto[1]	1	1		T193	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T130	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	8	1		T28	1		T40	1		T326	1