Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	11919	1		T304	2383		T305	2509		T306	2561
rd_lvl[2]	38155	1		T6	1530		T77	14947		T304	1066
rd_lvl[3]	12247	1		T6	761		T307	4783		T304	357
rd_lvl[4]	19025	1		T6	136		T307	4562		T77	1
rd_lvl[5]	12117	1		T6	499		T308	2494		T304	268
rd_lvl[6]	14718	1		T6	622		T308	2513		T304	18
rd_lvl[7]	5885	1		T304	230		T305	268		T309	86
rd_lvl[8]	12921	1		T310	2241		T311	2946		T77	1
rd_lvl[9]	7374	1		T310	1107		T311	440		T37	232
rd_lvl[10]	10535	1		T37	72		T312	14		T304	118
rd_lvl[11]	4375	1		T38	637		T36	181		T313	571
rd_lvl[12]	10471	1		T6	6		T38	961		T36	76
rd_lvl[13]	1428	1		T6	6		T36	1		T314	464
rd_lvl[14]	605	1		T36	135		T235	73		T304	99
rd_lvl[15]	2029	1		T35	594		T266	303		T315	209