Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	258426	1		T1	1		T2	2		T3	2
all_pins[1]	258426	1		T1	1		T2	2		T3	2
all_pins[2]	258426	1		T1	1		T2	2		T3	2
all_pins[3]	258426	1		T1	1		T2	2		T3	2
all_pins[4]	258426	1		T1	1		T2	2		T3	2
all_pins[5]	258426	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1274381	1		T1	6		T2	12		T3	12
values[0x1]	276175	1		T6	4157		T27	1443		T35	5191
transitions[0x0=>0x1]	246492	1		T6	3713		T27	1443		T35	3189
transitions[0x1=>0x0]	246472	1		T6	3713		T27	1443		T35	3189

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	258262	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	164	1		T256	3		T257	4		T258	1
all_pins[0]	transitions[0x0=>0x1]	75	1		T256	1		T257	3		T297	1
all_pins[0]	transitions[0x1=>0x0]	61	1		T258	3		T297	7		T299	5
all_pins[1]	values[0x0]	258276	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	150	1		T256	2		T257	1		T258	4
all_pins[1]	transitions[0x0=>0x1]	134	1		T256	1		T258	4		T297	7
all_pins[1]	transitions[0x1=>0x0]	4492	1		T35	1001		T266	224		T315	1461
all_pins[2]	values[0x0]	253918	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	4508	1		T35	1001		T266	224		T315	1461
all_pins[2]	transitions[0x0=>0x1]	30	1		T256	1		T257	2		T298	1
all_pins[2]	transitions[0x1=>0x0]	163866	1		T6	3560		T35	594		T38	1598
all_pins[3]	values[0x0]	90082	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	168344	1		T6	3560		T35	1595		T38	1598
all_pins[3]	transitions[0x0=>0x1]	143288	1		T6	3116		T35	594		T38	1598
all_pins[3]	transitions[0x1=>0x0]	77896	1		T6	153		T27	1443		T35	1594
all_pins[4]	values[0x0]	155474	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	102952	1		T6	597		T27	1443		T35	2595
all_pins[4]	transitions[0x0=>0x1]	102938	1		T6	597		T27	1443		T35	2595
all_pins[4]	transitions[0x1=>0x0]	43	1		T297	1		T298	4		T299	1
all_pins[5]	values[0x0]	258369	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	57	1		T258	1		T297	1		T298	5
all_pins[5]	transitions[0x0=>0x1]	27	1		T258	1		T297	1		T298	3
all_pins[5]	transitions[0x1=>0x0]	114	1		T256	2		T257	3		T258	1