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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.26 95.74 93.89 98.31 92.52 98.27 97.09 98.03


Total test records in report: 1247
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T1069 /workspace/coverage/default/77.flash_ctrl_connect.1744845413 Jun 13 03:27:37 PM PDT 24 Jun 13 03:27:54 PM PDT 24 73595900 ps
T360 /workspace/coverage/default/31.flash_ctrl_sec_info_access.3722297411 Jun 13 03:25:49 PM PDT 24 Jun 13 03:26:40 PM PDT 24 369939500 ps
T1070 /workspace/coverage/default/7.flash_ctrl_smoke.1336183901 Jun 13 03:20:19 PM PDT 24 Jun 13 03:23:07 PM PDT 24 42115900 ps
T1071 /workspace/coverage/default/5.flash_ctrl_mp_regions.2615433768 Jun 13 03:19:33 PM PDT 24 Jun 13 03:24:25 PM PDT 24 12161014900 ps
T241 /workspace/coverage/default/1.flash_ctrl_integrity.1630056452 Jun 13 03:17:39 PM PDT 24 Jun 13 03:30:30 PM PDT 24 15940830000 ps
T1072 /workspace/coverage/default/19.flash_ctrl_wo.2459469524 Jun 13 03:24:14 PM PDT 24 Jun 13 03:27:48 PM PDT 24 2625881900 ps
T1073 /workspace/coverage/default/39.flash_ctrl_sec_info_access.2597943728 Jun 13 03:26:41 PM PDT 24 Jun 13 03:28:07 PM PDT 24 2507161800 ps
T1074 /workspace/coverage/default/31.flash_ctrl_intr_rd.1858151467 Jun 13 03:26:46 PM PDT 24 Jun 13 03:30:10 PM PDT 24 1542929400 ps
T1075 /workspace/coverage/default/11.flash_ctrl_prog_reset.1741268656 Jun 13 03:21:58 PM PDT 24 Jun 13 03:22:12 PM PDT 24 93063300 ps
T1076 /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1793892098 Jun 13 03:24:09 PM PDT 24 Jun 13 03:42:17 PM PDT 24 270248078900 ps
T1077 /workspace/coverage/default/66.flash_ctrl_otp_reset.612857747 Jun 13 03:27:24 PM PDT 24 Jun 13 03:29:36 PM PDT 24 34887800 ps
T1078 /workspace/coverage/default/8.flash_ctrl_intr_rd.2946942526 Jun 13 03:20:56 PM PDT 24 Jun 13 03:25:13 PM PDT 24 12154602600 ps
T1079 /workspace/coverage/default/4.flash_ctrl_fetch_code.2968641107 Jun 13 03:18:58 PM PDT 24 Jun 13 03:19:19 PM PDT 24 246930400 ps
T1080 /workspace/coverage/default/22.flash_ctrl_sec_info_access.2195148127 Jun 13 03:24:49 PM PDT 24 Jun 13 03:25:52 PM PDT 24 2855760400 ps
T1081 /workspace/coverage/default/15.flash_ctrl_otp_reset.1359249060 Jun 13 03:23:09 PM PDT 24 Jun 13 03:25:23 PM PDT 24 555950800 ps
T1082 /workspace/coverage/default/10.flash_ctrl_wo.133811720 Jun 13 03:21:32 PM PDT 24 Jun 13 03:24:53 PM PDT 24 4573614500 ps
T1083 /workspace/coverage/default/4.flash_ctrl_connect.3094184181 Jun 13 03:19:20 PM PDT 24 Jun 13 03:19:37 PM PDT 24 51361700 ps
T1084 /workspace/coverage/default/10.flash_ctrl_re_evict.197031143 Jun 13 03:21:46 PM PDT 24 Jun 13 03:22:20 PM PDT 24 96008400 ps
T1085 /workspace/coverage/default/0.flash_ctrl_intr_wr.4067269591 Jun 13 03:17:21 PM PDT 24 Jun 13 03:18:37 PM PDT 24 2410085800 ps
T1086 /workspace/coverage/default/4.flash_ctrl_intr_wr.2230536981 Jun 13 03:19:16 PM PDT 24 Jun 13 03:20:33 PM PDT 24 8525120800 ps
T1087 /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.187027574 Jun 13 03:23:17 PM PDT 24 Jun 13 03:23:48 PM PDT 24 43837500 ps
T1088 /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.4061417800 Jun 13 03:18:13 PM PDT 24 Jun 13 03:18:29 PM PDT 24 19120600 ps
T1089 /workspace/coverage/default/47.flash_ctrl_disable.483462386 Jun 13 03:27:10 PM PDT 24 Jun 13 03:27:31 PM PDT 24 10796400 ps
T1090 /workspace/coverage/default/8.flash_ctrl_rw_serr.3932369169 Jun 13 03:20:49 PM PDT 24 Jun 13 03:31:43 PM PDT 24 8537867400 ps
T1091 /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2162560151 Jun 13 03:17:46 PM PDT 24 Jun 13 03:18:02 PM PDT 24 15099400 ps
T1092 /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.351705053 Jun 13 03:20:17 PM PDT 24 Jun 13 03:22:26 PM PDT 24 10011554100 ps
T1093 /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3783866386 Jun 13 03:21:27 PM PDT 24 Jun 13 03:21:42 PM PDT 24 24735900 ps
T324 /workspace/coverage/default/18.flash_ctrl_rw.3094639930 Jun 13 03:24:11 PM PDT 24 Jun 13 03:33:43 PM PDT 24 29654401800 ps
T1094 /workspace/coverage/default/32.flash_ctrl_otp_reset.1540631089 Jun 13 03:25:49 PM PDT 24 Jun 13 03:27:40 PM PDT 24 247640700 ps
T1095 /workspace/coverage/default/1.flash_ctrl_invalid_op.2230001299 Jun 13 03:17:39 PM PDT 24 Jun 13 03:18:49 PM PDT 24 2054977800 ps
T1096 /workspace/coverage/default/66.flash_ctrl_connect.3418439170 Jun 13 03:27:27 PM PDT 24 Jun 13 03:27:43 PM PDT 24 24756900 ps
T1097 /workspace/coverage/default/2.flash_ctrl_oversize_error.963061640 Jun 13 03:17:53 PM PDT 24 Jun 13 03:21:11 PM PDT 24 1456760100 ps
T62 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.814595379 Jun 13 03:16:31 PM PDT 24 Jun 13 03:17:01 PM PDT 24 126860900 ps
T1098 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.12738079 Jun 13 03:15:45 PM PDT 24 Jun 13 03:15:59 PM PDT 24 18306300 ps
T63 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3801622482 Jun 13 03:16:02 PM PDT 24 Jun 13 03:16:21 PM PDT 24 679234900 ps
T256 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.543787889 Jun 13 03:16:38 PM PDT 24 Jun 13 03:16:52 PM PDT 24 24474900 ps
T1099 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3991314782 Jun 13 03:16:50 PM PDT 24 Jun 13 03:17:07 PM PDT 24 13022300 ps
T257 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3543633259 Jun 13 03:16:59 PM PDT 24 Jun 13 03:17:12 PM PDT 24 14837300 ps
T64 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.682919016 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:32 PM PDT 24 108059000 ps
T258 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2536206332 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:29 PM PDT 24 23297700 ps
T1100 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1019706092 Jun 13 03:16:31 PM PDT 24 Jun 13 03:16:48 PM PDT 24 14414300 ps
T97 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1575466920 Jun 13 03:16:38 PM PDT 24 Jun 13 03:24:19 PM PDT 24 1739606100 ps
T98 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3372262964 Jun 13 03:15:39 PM PDT 24 Jun 13 03:16:29 PM PDT 24 429328100 ps
T99 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2902427450 Jun 13 03:15:51 PM PDT 24 Jun 13 03:28:38 PM PDT 24 985425800 ps
T202 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1351201725 Jun 13 03:16:40 PM PDT 24 Jun 13 03:16:58 PM PDT 24 371599100 ps
T286 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4157591885 Jun 13 03:15:40 PM PDT 24 Jun 13 03:16:20 PM PDT 24 3185593600 ps
T1101 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2464019803 Jun 13 03:16:26 PM PDT 24 Jun 13 03:16:42 PM PDT 24 30809500 ps
T297 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1446325337 Jun 13 03:16:39 PM PDT 24 Jun 13 03:16:53 PM PDT 24 47060400 ps
T223 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.764344048 Jun 13 03:15:35 PM PDT 24 Jun 13 03:15:49 PM PDT 24 35969400 ps
T253 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3835666545 Jun 13 03:15:52 PM PDT 24 Jun 13 03:17:11 PM PDT 24 2235318900 ps
T298 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.932734416 Jun 13 03:16:55 PM PDT 24 Jun 13 03:17:08 PM PDT 24 14794400 ps
T296 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.63261643 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:12 PM PDT 24 25876900 ps
T301 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1021916191 Jun 13 03:15:39 PM PDT 24 Jun 13 03:15:52 PM PDT 24 132892000 ps
T299 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3742938269 Jun 13 03:17:01 PM PDT 24 Jun 13 03:17:15 PM PDT 24 47713300 ps
T1102 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2189130818 Jun 13 03:15:52 PM PDT 24 Jun 13 03:16:07 PM PDT 24 40403300 ps
T242 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4163601153 Jun 13 03:16:43 PM PDT 24 Jun 13 03:16:58 PM PDT 24 57701400 ps
T300 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2412468859 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:38 PM PDT 24 118797400 ps
T203 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.616601652 Jun 13 03:15:51 PM PDT 24 Jun 13 03:16:13 PM PDT 24 224416000 ps
T1103 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.201442410 Jun 13 03:15:36 PM PDT 24 Jun 13 03:15:53 PM PDT 24 11159600 ps
T1104 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2273459164 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:35 PM PDT 24 675318000 ps
T259 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3555436866 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:24 PM PDT 24 104388700 ps
T302 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.503321719 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:10 PM PDT 24 133882000 ps
T1105 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1128922256 Jun 13 03:16:39 PM PDT 24 Jun 13 03:16:53 PM PDT 24 38757600 ps
T204 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.441577682 Jun 13 03:16:44 PM PDT 24 Jun 13 03:17:03 PM PDT 24 46574200 ps
T1106 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4022820018 Jun 13 03:17:02 PM PDT 24 Jun 13 03:17:17 PM PDT 24 25884700 ps
T1107 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1296451937 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:11 PM PDT 24 42560700 ps
T1108 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2284698311 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:11 PM PDT 24 15783900 ps
T215 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2912407476 Jun 13 03:15:50 PM PDT 24 Jun 13 03:28:16 PM PDT 24 708798700 ps
T252 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2905218796 Jun 13 03:16:02 PM PDT 24 Jun 13 03:23:44 PM PDT 24 1352959800 ps
T1109 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1282339280 Jun 13 03:16:44 PM PDT 24 Jun 13 03:17:03 PM PDT 24 95947900 ps
T1110 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1816957067 Jun 13 03:16:33 PM PDT 24 Jun 13 03:16:51 PM PDT 24 286867000 ps
T216 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.61162517 Jun 13 03:16:33 PM PDT 24 Jun 13 03:16:51 PM PDT 24 89770900 ps
T1111 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3171091232 Jun 13 03:16:19 PM PDT 24 Jun 13 03:16:35 PM PDT 24 13997100 ps
T217 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.372255694 Jun 13 03:16:42 PM PDT 24 Jun 13 03:17:01 PM PDT 24 30179900 ps
T1112 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.161539715 Jun 13 03:16:44 PM PDT 24 Jun 13 03:17:03 PM PDT 24 95832400 ps
T303 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2074081671 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:11 PM PDT 24 30766300 ps
T278 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2559036192 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:32 PM PDT 24 75838700 ps
T1113 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4095639966 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:13 PM PDT 24 75147500 ps
T1114 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1948372049 Jun 13 03:16:37 PM PDT 24 Jun 13 03:16:55 PM PDT 24 132221900 ps
T1115 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3055740575 Jun 13 03:16:31 PM PDT 24 Jun 13 03:16:45 PM PDT 24 46626300 ps
T1116 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.798029479 Jun 13 03:15:36 PM PDT 24 Jun 13 03:16:04 PM PDT 24 55287400 ps
T1117 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.627755109 Jun 13 03:16:50 PM PDT 24 Jun 13 03:17:08 PM PDT 24 48421900 ps
T218 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3544550500 Jun 13 03:16:52 PM PDT 24 Jun 13 03:29:25 PM PDT 24 710158200 ps
T1118 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1420307503 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:11 PM PDT 24 46927300 ps
T219 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2155542327 Jun 13 03:16:23 PM PDT 24 Jun 13 03:29:16 PM PDT 24 1280375900 ps
T1119 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4030613911 Jun 13 03:16:09 PM PDT 24 Jun 13 03:16:45 PM PDT 24 314913800 ps
T1120 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.587964142 Jun 13 03:16:15 PM PDT 24 Jun 13 03:16:29 PM PDT 24 42415900 ps
T220 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3934036377 Jun 13 03:16:08 PM PDT 24 Jun 13 03:16:24 PM PDT 24 67420500 ps
T265 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3542838473 Jun 13 03:16:13 PM PDT 24 Jun 13 03:23:52 PM PDT 24 3153426000 ps
T221 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2509511061 Jun 13 03:15:39 PM PDT 24 Jun 13 03:16:00 PM PDT 24 115717200 ps
T279 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1373620883 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:44 PM PDT 24 182845400 ps
T1121 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1710167675 Jun 13 03:15:34 PM PDT 24 Jun 13 03:15:51 PM PDT 24 37631500 ps
T222 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2508636668 Jun 13 03:15:36 PM PDT 24 Jun 13 03:23:16 PM PDT 24 375955800 ps
T255 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2635393952 Jun 13 03:16:31 PM PDT 24 Jun 13 03:16:51 PM PDT 24 69986300 ps
T280 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3601003161 Jun 13 03:15:39 PM PDT 24 Jun 13 03:15:58 PM PDT 24 83669900 ps
T254 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3142420517 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:20 PM PDT 24 66621400 ps
T1122 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.971561135 Jun 13 03:15:55 PM PDT 24 Jun 13 03:16:25 PM PDT 24 167614400 ps
T1123 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2165742651 Jun 13 03:16:49 PM PDT 24 Jun 13 03:17:03 PM PDT 24 114562400 ps
T281 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3151104150 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:23 PM PDT 24 100230200 ps
T282 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.898673650 Jun 13 03:15:58 PM PDT 24 Jun 13 03:16:29 PM PDT 24 362634600 ps
T260 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2609931751 Jun 13 03:16:49 PM PDT 24 Jun 13 03:17:05 PM PDT 24 66009600 ps
T335 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2973167738 Jun 13 03:16:44 PM PDT 24 Jun 13 03:29:36 PM PDT 24 332388100 ps
T1124 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1578189750 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:21 PM PDT 24 37779900 ps
T1125 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.899832600 Jun 13 03:16:17 PM PDT 24 Jun 13 03:16:34 PM PDT 24 287326100 ps
T1126 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2969124170 Jun 13 03:16:45 PM PDT 24 Jun 13 03:17:02 PM PDT 24 49694800 ps
T1127 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3766954771 Jun 13 03:15:51 PM PDT 24 Jun 13 03:16:08 PM PDT 24 11834800 ps
T1128 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1508462981 Jun 13 03:16:02 PM PDT 24 Jun 13 03:16:16 PM PDT 24 48560500 ps
T261 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.851186565 Jun 13 03:15:46 PM PDT 24 Jun 13 03:16:07 PM PDT 24 179234900 ps
T1129 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4101038816 Jun 13 03:17:01 PM PDT 24 Jun 13 03:17:16 PM PDT 24 55486600 ps
T262 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.430596599 Jun 13 03:16:42 PM PDT 24 Jun 13 03:17:04 PM PDT 24 54318400 ps
T1130 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4187558609 Jun 13 03:16:36 PM PDT 24 Jun 13 03:16:51 PM PDT 24 20148700 ps
T1131 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2311116353 Jun 13 03:16:52 PM PDT 24 Jun 13 03:17:09 PM PDT 24 151556600 ps
T224 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1998499711 Jun 13 03:15:50 PM PDT 24 Jun 13 03:16:05 PM PDT 24 71452400 ps
T1132 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1914570111 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:20 PM PDT 24 277353000 ps
T1133 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1843227037 Jun 13 03:16:44 PM PDT 24 Jun 13 03:16:58 PM PDT 24 18625600 ps
T263 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.277732283 Jun 13 03:16:37 PM PDT 24 Jun 13 03:16:57 PM PDT 24 221402400 ps
T1134 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2827466113 Jun 13 03:17:02 PM PDT 24 Jun 13 03:17:17 PM PDT 24 44529100 ps
T283 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2757849365 Jun 13 03:16:50 PM PDT 24 Jun 13 03:17:09 PM PDT 24 237771500 ps
T284 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1153239487 Jun 13 03:16:46 PM PDT 24 Jun 13 03:17:06 PM PDT 24 198709500 ps
T1135 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.929118107 Jun 13 03:17:02 PM PDT 24 Jun 13 03:17:16 PM PDT 24 81506700 ps
T1136 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.768201266 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:12 PM PDT 24 14455300 ps
T1137 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1149561660 Jun 13 03:17:00 PM PDT 24 Jun 13 03:17:14 PM PDT 24 25048500 ps
T1138 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3464794627 Jun 13 03:16:27 PM PDT 24 Jun 13 03:16:48 PM PDT 24 566392400 ps
T1139 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1905322875 Jun 13 03:16:15 PM PDT 24 Jun 13 03:16:33 PM PDT 24 156058500 ps
T1140 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.971792512 Jun 13 03:16:40 PM PDT 24 Jun 13 03:16:53 PM PDT 24 11364600 ps
T328 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2126495962 Jun 13 03:16:01 PM PDT 24 Jun 13 03:16:20 PM PDT 24 62774700 ps
T1141 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.240608597 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:40 PM PDT 24 96078300 ps
T1142 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3216167048 Jun 13 03:16:27 PM PDT 24 Jun 13 03:16:41 PM PDT 24 24265400 ps
T1143 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2450492346 Jun 13 03:17:02 PM PDT 24 Jun 13 03:17:17 PM PDT 24 19406300 ps
T285 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3224510235 Jun 13 03:16:03 PM PDT 24 Jun 13 03:16:40 PM PDT 24 846968600 ps
T1144 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1452348300 Jun 13 03:16:27 PM PDT 24 Jun 13 03:16:43 PM PDT 24 17830200 ps
T1145 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3992156805 Jun 13 03:16:44 PM PDT 24 Jun 13 03:17:01 PM PDT 24 20054700 ps
T1146 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2252622445 Jun 13 03:15:55 PM PDT 24 Jun 13 03:16:35 PM PDT 24 330887400 ps
T1147 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2877286633 Jun 13 03:15:52 PM PDT 24 Jun 13 03:16:55 PM PDT 24 7162036100 ps
T1148 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3140917540 Jun 13 03:17:04 PM PDT 24 Jun 13 03:17:19 PM PDT 24 54291300 ps
T1149 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.55110864 Jun 13 03:16:54 PM PDT 24 Jun 13 03:17:07 PM PDT 24 25323500 ps
T1150 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3127916794 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:49 PM PDT 24 231307200 ps
T1151 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.571491226 Jun 13 03:15:51 PM PDT 24 Jun 13 03:16:06 PM PDT 24 25073700 ps
T1152 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3651453002 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:28 PM PDT 24 30408800 ps
T1153 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.963268725 Jun 13 03:15:39 PM PDT 24 Jun 13 03:15:53 PM PDT 24 28599900 ps
T1154 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.941791213 Jun 13 03:15:58 PM PDT 24 Jun 13 03:16:53 PM PDT 24 881414600 ps
T1155 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3777953708 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:12 PM PDT 24 17849200 ps
T1156 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2166469890 Jun 13 03:16:45 PM PDT 24 Jun 13 03:17:05 PM PDT 24 484287000 ps
T1157 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2836995120 Jun 13 03:16:38 PM PDT 24 Jun 13 03:16:56 PM PDT 24 173500500 ps
T1158 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.282780988 Jun 13 03:15:39 PM PDT 24 Jun 13 03:15:58 PM PDT 24 924560800 ps
T1159 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.536222323 Jun 13 03:16:43 PM PDT 24 Jun 13 03:16:57 PM PDT 24 16871800 ps
T1160 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.524083246 Jun 13 03:16:05 PM PDT 24 Jun 13 03:16:19 PM PDT 24 15396000 ps
T1161 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3766645246 Jun 13 03:16:33 PM PDT 24 Jun 13 03:16:50 PM PDT 24 44837200 ps
T1162 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3404227804 Jun 13 03:16:38 PM PDT 24 Jun 13 03:16:56 PM PDT 24 118581500 ps
T1163 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.917685198 Jun 13 03:16:31 PM PDT 24 Jun 13 03:16:48 PM PDT 24 34813100 ps
T1164 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1479057795 Jun 13 03:16:10 PM PDT 24 Jun 13 03:16:26 PM PDT 24 303516400 ps
T1165 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1143299707 Jun 13 03:16:03 PM PDT 24 Jun 13 03:16:20 PM PDT 24 177007800 ps
T1166 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1610850157 Jun 13 03:16:43 PM PDT 24 Jun 13 03:16:58 PM PDT 24 14980100 ps
T1167 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3504668367 Jun 13 03:15:53 PM PDT 24 Jun 13 03:16:11 PM PDT 24 43578000 ps
T1168 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.886596102 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:31 PM PDT 24 13703200 ps
T1169 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.374073227 Jun 13 03:15:44 PM PDT 24 Jun 13 03:16:04 PM PDT 24 38204300 ps
T1170 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.7637610 Jun 13 03:15:33 PM PDT 24 Jun 13 03:15:48 PM PDT 24 18368600 ps
T1171 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1605572284 Jun 13 03:16:14 PM PDT 24 Jun 13 03:16:29 PM PDT 24 43866000 ps
T1172 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3149169289 Jun 13 03:16:52 PM PDT 24 Jun 13 03:17:09 PM PDT 24 12577100 ps
T1173 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2003827397 Jun 13 03:16:06 PM PDT 24 Jun 13 03:16:24 PM PDT 24 27857300 ps
T1174 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1885224695 Jun 13 03:16:51 PM PDT 24 Jun 13 03:17:09 PM PDT 24 109468500 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3106345371 Jun 13 03:16:37 PM PDT 24 Jun 13 03:16:55 PM PDT 24 73282100 ps
T1175 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3301383094 Jun 13 03:16:49 PM PDT 24 Jun 13 03:17:02 PM PDT 24 28529900 ps
T1176 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.72064163 Jun 13 03:16:59 PM PDT 24 Jun 13 03:17:13 PM PDT 24 45194500 ps
T1177 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1112756890 Jun 13 03:15:45 PM PDT 24 Jun 13 03:16:28 PM PDT 24 927335600 ps
T1178 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2633233637 Jun 13 03:16:52 PM PDT 24 Jun 13 03:17:11 PM PDT 24 150610400 ps
T1179 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1266205704 Jun 13 03:15:56 PM PDT 24 Jun 13 03:16:10 PM PDT 24 48070800 ps
T1180 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1343886216 Jun 13 03:16:39 PM PDT 24 Jun 13 03:16:55 PM PDT 24 20557900 ps
T1181 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3633995473 Jun 13 03:16:54 PM PDT 24 Jun 13 03:17:30 PM PDT 24 179737400 ps
T1182 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.78673711 Jun 13 03:16:15 PM PDT 24 Jun 13 03:16:33 PM PDT 24 56397100 ps
T1183 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.751035060 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:11 PM PDT 24 14480200 ps
T1184 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.383468604 Jun 13 03:16:07 PM PDT 24 Jun 13 03:16:23 PM PDT 24 272847800 ps
T1185 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1791018894 Jun 13 03:15:52 PM PDT 24 Jun 13 03:16:11 PM PDT 24 213227500 ps
T1186 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.257682485 Jun 13 03:16:31 PM PDT 24 Jun 13 03:16:45 PM PDT 24 20520300 ps
T1187 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.158581411 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:12 PM PDT 24 14309900 ps
T1188 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.226829455 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:10 PM PDT 24 18336600 ps
T1189 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.453917120 Jun 13 03:16:50 PM PDT 24 Jun 13 03:17:05 PM PDT 24 29282300 ps
T1190 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3801483085 Jun 13 03:16:45 PM PDT 24 Jun 13 03:17:04 PM PDT 24 324389100 ps
T1191 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4260030874 Jun 13 03:16:48 PM PDT 24 Jun 13 03:17:05 PM PDT 24 41461000 ps
T1192 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3502349278 Jun 13 03:15:50 PM PDT 24 Jun 13 03:16:04 PM PDT 24 17359800 ps
T334 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3976452264 Jun 13 03:16:14 PM PDT 24 Jun 13 03:31:06 PM PDT 24 652660600 ps
T1193 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3349968583 Jun 13 03:15:46 PM PDT 24 Jun 13 03:17:03 PM PDT 24 4550368400 ps
T1194 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1644680692 Jun 13 03:15:57 PM PDT 24 Jun 13 03:16:45 PM PDT 24 1587980400 ps
T1195 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3727765347 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:24 PM PDT 24 26089900 ps
T225 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.429633959 Jun 13 03:15:53 PM PDT 24 Jun 13 03:16:08 PM PDT 24 54508200 ps
T1196 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1141531270 Jun 13 03:15:38 PM PDT 24 Jun 13 03:15:54 PM PDT 24 22657800 ps
T1197 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3018271355 Jun 13 03:15:54 PM PDT 24 Jun 13 03:16:11 PM PDT 24 30699100 ps
T1198 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2880409568 Jun 13 03:15:54 PM PDT 24 Jun 13 03:16:12 PM PDT 24 107693500 ps
T1199 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2246373992 Jun 13 03:16:39 PM PDT 24 Jun 13 03:16:58 PM PDT 24 204429800 ps
T1200 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4144225900 Jun 13 03:16:00 PM PDT 24 Jun 13 03:23:31 PM PDT 24 480605300 ps
T1201 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1025408288 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:11 PM PDT 24 14567700 ps
T1202 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3225346899 Jun 13 03:15:52 PM PDT 24 Jun 13 03:16:07 PM PDT 24 17975400 ps
T1203 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2131392345 Jun 13 03:16:43 PM PDT 24 Jun 13 03:16:59 PM PDT 24 17054700 ps
T1204 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2927785580 Jun 13 03:16:40 PM PDT 24 Jun 13 03:16:58 PM PDT 24 55710200 ps
T1205 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3949864779 Jun 13 03:16:45 PM PDT 24 Jun 13 03:17:05 PM PDT 24 156081700 ps
T1206 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2787265773 Jun 13 03:16:16 PM PDT 24 Jun 13 03:16:33 PM PDT 24 14467100 ps
T1207 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2654231369 Jun 13 03:16:21 PM PDT 24 Jun 13 03:16:37 PM PDT 24 20117700 ps
T330 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.493375254 Jun 13 03:15:40 PM PDT 24 Jun 13 03:22:11 PM PDT 24 347682400 ps
T226 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1208141626 Jun 13 03:15:58 PM PDT 24 Jun 13 03:16:12 PM PDT 24 15684700 ps
T1208 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2018324820 Jun 13 03:16:55 PM PDT 24 Jun 13 03:17:09 PM PDT 24 55970600 ps
T1209 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.333681603 Jun 13 03:16:49 PM PDT 24 Jun 13 03:17:03 PM PDT 24 17219200 ps
T1210 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.575918310 Jun 13 03:16:05 PM PDT 24 Jun 13 03:16:22 PM PDT 24 21929900 ps
T1211 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.854336373 Jun 13 03:16:27 PM PDT 24 Jun 13 03:16:47 PM PDT 24 187976100 ps
T338 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.661326533 Jun 13 03:16:30 PM PDT 24 Jun 13 03:22:56 PM PDT 24 366230600 ps
T1212 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1936886471 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:21 PM PDT 24 27128400 ps
T227 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3983647154 Jun 13 03:15:56 PM PDT 24 Jun 13 03:16:10 PM PDT 24 20324500 ps
T1213 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2488799159 Jun 13 03:16:43 PM PDT 24 Jun 13 03:16:57 PM PDT 24 25237900 ps
T1214 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2285962467 Jun 13 03:16:52 PM PDT 24 Jun 13 03:17:06 PM PDT 24 18513900 ps
T1215 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2267242422 Jun 13 03:16:17 PM PDT 24 Jun 13 03:16:34 PM PDT 24 18322800 ps
T1216 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.369779098 Jun 13 03:16:44 PM PDT 24 Jun 13 03:16:59 PM PDT 24 16727800 ps
T1217 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1901484695 Jun 13 03:15:35 PM PDT 24 Jun 13 03:15:53 PM PDT 24 41078200 ps
T1218 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3912894297 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:12 PM PDT 24 60653900 ps
T332 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2380591327 Jun 13 03:15:58 PM PDT 24 Jun 13 03:23:34 PM PDT 24 192245100 ps
T1219 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2176282525 Jun 13 03:15:51 PM PDT 24 Jun 13 03:16:05 PM PDT 24 28367800 ps
T331 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3253995823 Jun 13 03:16:03 PM PDT 24 Jun 13 03:28:51 PM PDT 24 790035100 ps
T1220 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.341178653 Jun 13 03:15:52 PM PDT 24 Jun 13 03:16:07 PM PDT 24 23769600 ps
T1221 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3736442331 Jun 13 03:16:42 PM PDT 24 Jun 13 03:17:00 PM PDT 24 14623900 ps
T1222 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.301473415 Jun 13 03:16:03 PM PDT 24 Jun 13 03:16:18 PM PDT 24 28827200 ps
T329 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.725343373 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:42 PM PDT 24 324376000 ps
T337 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.684763022 Jun 13 03:16:40 PM PDT 24 Jun 13 03:29:21 PM PDT 24 1327981300 ps
T1223 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1104817302 Jun 13 03:15:56 PM PDT 24 Jun 13 03:16:13 PM PDT 24 67739200 ps
T1224 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3818729748 Jun 13 03:17:03 PM PDT 24 Jun 13 03:17:17 PM PDT 24 17905900 ps
T1225 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2877012901 Jun 13 03:16:00 PM PDT 24 Jun 13 03:16:21 PM PDT 24 240394400 ps
T1226 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2319020374 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:44 PM PDT 24 126183500 ps
T1227 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.746830190 Jun 13 03:15:37 PM PDT 24 Jun 13 03:16:08 PM PDT 24 70565800 ps
T1228 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.269209321 Jun 13 03:16:05 PM PDT 24 Jun 13 03:16:23 PM PDT 24 230860800 ps
T1229 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2185747907 Jun 13 03:15:34 PM PDT 24 Jun 13 03:15:48 PM PDT 24 33797600 ps
T1230 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1173207756 Jun 13 03:15:43 PM PDT 24 Jun 13 03:16:00 PM PDT 24 132000500 ps
T1231 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1703351571 Jun 13 03:15:44 PM PDT 24 Jun 13 03:16:20 PM PDT 24 194051100 ps
T336 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1690527277 Jun 13 03:16:24 PM PDT 24 Jun 13 03:31:20 PM PDT 24 339670500 ps
T1232 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4267587871 Jun 13 03:16:48 PM PDT 24 Jun 13 03:17:02 PM PDT 24 53886300 ps
T1233 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1361138479 Jun 13 03:15:53 PM PDT 24 Jun 13 03:16:28 PM PDT 24 355967700 ps
T1234 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2269302087 Jun 13 03:16:33 PM PDT 24 Jun 13 03:16:53 PM PDT 24 230617300 ps
T333 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2455036741 Jun 13 03:16:45 PM PDT 24 Jun 13 03:23:14 PM PDT 24 427447900 ps
T1235 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3336627894 Jun 13 03:16:32 PM PDT 24 Jun 13 03:24:15 PM PDT 24 6000469000 ps
T1236 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.773708588 Jun 13 03:16:57 PM PDT 24 Jun 13 03:17:11 PM PDT 24 50174500 ps
T1237 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.715609393 Jun 13 03:16:00 PM PDT 24 Jun 13 03:16:18 PM PDT 24 108235900 ps
T1238 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2026258481 Jun 13 03:15:50 PM PDT 24 Jun 13 03:16:07 PM PDT 24 47798500 ps
T1239 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3479027190 Jun 13 03:16:48 PM PDT 24 Jun 13 03:24:36 PM PDT 24 179017700 ps
T1240 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.958592634 Jun 13 03:16:25 PM PDT 24 Jun 13 03:16:43 PM PDT 24 107327700 ps
T1241 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.484244161 Jun 13 03:16:01 PM PDT 24 Jun 13 03:16:17 PM PDT 24 14881200 ps
T1242 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.845111038 Jun 13 03:16:05 PM PDT 24 Jun 13 03:16:19 PM PDT 24 12425800 ps
T1243 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.594680050 Jun 13 03:16:42 PM PDT 24 Jun 13 03:17:00 PM PDT 24 46182000 ps
T1244 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.241697045 Jun 13 03:15:54 PM PDT 24 Jun 13 03:17:03 PM PDT 24 5088211500 ps
T1245 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2343530539 Jun 13 03:15:50 PM PDT 24 Jun 13 03:16:38 PM PDT 24 191777900 ps
T1246 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3467291178 Jun 13 03:16:56 PM PDT 24 Jun 13 03:17:11 PM PDT 24 15898000 ps
T1247 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3697008576 Jun 13 03:16:04 PM PDT 24 Jun 13 03:16:18 PM PDT 24 50310700 ps

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1620401018
Short name T2
Test name
Test status
Simulation time 3751253800 ps
CPU time 626.33 seconds
Started Jun 13 03:20:33 PM PDT 24
Finished Jun 13 03:31:02 PM PDT 24
Peak memory 313488 kb
Host smart-428739f3-674e-424e-9d2f-5f2e896f9b94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620401018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1620401018
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3914107099
Short name T24
Test name
Test status
Simulation time 8987156000 ps
CPU time 299.93 seconds
Started Jun 13 03:24:16 PM PDT 24
Finished Jun 13 03:29:17 PM PDT 24
Peak memory 274636 kb
Host smart-ae1c0c06-db89-46c1-8efc-e7c75c41887c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914107099 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.3914107099
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1575466920
Short name T97
Test name
Test status
Simulation time 1739606100 ps
CPU time 460.51 seconds
Started Jun 13 03:16:38 PM PDT 24
Finished Jun 13 03:24:19 PM PDT 24
Peak memory 263408 kb
Host smart-2eb5fe23-7b30-4416-9246-80ee34295779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575466920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1575466920
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.4055975739
Short name T14
Test name
Test status
Simulation time 40117652000 ps
CPU time 803.84 seconds
Started Jun 13 03:18:20 PM PDT 24
Finished Jun 13 03:31:45 PM PDT 24
Peak memory 264588 kb
Host smart-eb0cd8c3-9407-4354-97ba-179b8be54b59
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055975739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.4055975739
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2278352561
Short name T10
Test name
Test status
Simulation time 141708000 ps
CPU time 131.83 seconds
Started Jun 13 03:27:41 PM PDT 24
Finished Jun 13 03:29:54 PM PDT 24
Peak memory 260488 kb
Host smart-8e318993-af01-4457-b663-9a2d12f4f0fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278352561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2278352561
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1993919327
Short name T18
Test name
Test status
Simulation time 3956562300 ps
CPU time 4867.11 seconds
Started Jun 13 03:18:05 PM PDT 24
Finished Jun 13 04:39:15 PM PDT 24
Peak memory 286572 kb
Host smart-44279f06-961f-4148-868b-723179e22abb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993919327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1993919327
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.117590293
Short name T6
Test name
Test status
Simulation time 791640600 ps
CPU time 149.72 seconds
Started Jun 13 03:20:31 PM PDT 24
Finished Jun 13 03:23:02 PM PDT 24
Peak memory 294584 kb
Host smart-ac97c9c8-ed3c-4a0c-8f8c-2f08b46c77f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117590293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.117590293
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.1581156532
Short name T143
Test name
Test status
Simulation time 15852071600 ps
CPU time 504.58 seconds
Started Jun 13 03:17:10 PM PDT 24
Finished Jun 13 03:25:36 PM PDT 24
Peak memory 263660 kb
Host smart-f880525b-f83f-4d25-ae54-f5f620fba54d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581156532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.1581156532
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.441577682
Short name T204
Test name
Test status
Simulation time 46574200 ps
CPU time 18.16 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 271672 kb
Host smart-2ddc2a6c-4656-48f2-b7a8-8c1c51314591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441577682 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.441577682
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.2361387181
Short name T70
Test name
Test status
Simulation time 2139523300 ps
CPU time 77.09 seconds
Started Jun 13 03:18:29 PM PDT 24
Finished Jun 13 03:19:47 PM PDT 24
Peak memory 261096 kb
Host smart-106d9f64-7f85-40b1-8884-85316af49b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361387181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2361387181
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2636572599
Short name T12
Test name
Test status
Simulation time 28767300 ps
CPU time 14.53 seconds
Started Jun 13 03:19:28 PM PDT 24
Finished Jun 13 03:19:43 PM PDT 24
Peak memory 266028 kb
Host smart-da5ab85a-d14a-4634-b2bb-f28146ef78b8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636572599 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2636572599
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.1940387394
Short name T28
Test name
Test status
Simulation time 30810000 ps
CPU time 30.92 seconds
Started Jun 13 03:24:59 PM PDT 24
Finished Jun 13 03:25:31 PM PDT 24
Peak memory 270268 kb
Host smart-350dfca2-56d1-42a3-918e-16c47458ed93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940387394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.1940387394
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.118711948
Short name T165
Test name
Test status
Simulation time 39697100 ps
CPU time 110.33 seconds
Started Jun 13 03:17:08 PM PDT 24
Finished Jun 13 03:18:59 PM PDT 24
Peak memory 260280 kb
Host smart-1fe9ef4b-8ea0-4a48-989c-f8d284dde9c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118711948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp
_reset.118711948
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2493343252
Short name T66
Test name
Test status
Simulation time 61745686100 ps
CPU time 1177.41 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:37:27 PM PDT 24
Peak memory 378560 kb
Host smart-fb4b54b4-94df-414c-9157-ecf91dd6ff63
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493343252 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2493343252
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.63261643
Short name T296
Test name
Test status
Simulation time 25876900 ps
CPU time 13.47 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:12 PM PDT 24
Peak memory 260808 kb
Host smart-bd37d683-0f7a-4a68-aa8f-a3d0cf910f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63261643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.63261643
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.2664037753
Short name T164
Test name
Test status
Simulation time 54524400 ps
CPU time 132.06 seconds
Started Jun 13 03:27:29 PM PDT 24
Finished Jun 13 03:29:42 PM PDT 24
Peak memory 261496 kb
Host smart-d6bafce4-c4f2-4a5f-966b-f1913048c08b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664037753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.2664037753
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3474501596
Short name T34
Test name
Test status
Simulation time 1651735300 ps
CPU time 79.54 seconds
Started Jun 13 03:25:27 PM PDT 24
Finished Jun 13 03:26:47 PM PDT 24
Peak memory 263508 kb
Host smart-2d42733d-8094-4a15-9083-78ca2905dfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474501596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3474501596
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.1216628674
Short name T48
Test name
Test status
Simulation time 1689368900 ps
CPU time 22.79 seconds
Started Jun 13 03:18:23 PM PDT 24
Finished Jun 13 03:18:46 PM PDT 24
Peak memory 262916 kb
Host smart-44abbd23-df67-4de7-9c53-a16395054c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216628674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.1216628674
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2669736219
Short name T156
Test name
Test status
Simulation time 38077600 ps
CPU time 110.83 seconds
Started Jun 13 03:26:53 PM PDT 24
Finished Jun 13 03:28:45 PM PDT 24
Peak memory 265188 kb
Host smart-1313f3f3-92d5-4f73-b4f8-a997f764733e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669736219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2669736219
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.1139028114
Short name T149
Test name
Test status
Simulation time 1749597400 ps
CPU time 71.15 seconds
Started Jun 13 03:17:55 PM PDT 24
Finished Jun 13 03:19:08 PM PDT 24
Peak memory 260816 kb
Host smart-79cee7ae-73e4-49aa-8cb6-906e3d8cd162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139028114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.1139028114
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1611322501
Short name T72
Test name
Test status
Simulation time 10011859100 ps
CPU time 333.8 seconds
Started Jun 13 03:18:20 PM PDT 24
Finished Jun 13 03:23:54 PM PDT 24
Peak memory 336636 kb
Host smart-daf1304f-ff8f-4b4c-a0ca-33b668b06aa6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611322501 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1611322501
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.581648148
Short name T20
Test name
Test status
Simulation time 315051500 ps
CPU time 132.1 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:26:25 PM PDT 24
Peak memory 261420 kb
Host smart-c553f692-d114-4fcb-9b2a-01726214bd9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581648148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ot
p_reset.581648148
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.3272541112
Short name T185
Test name
Test status
Simulation time 82308861600 ps
CPU time 714.16 seconds
Started Jun 13 03:17:16 PM PDT 24
Finished Jun 13 03:29:11 PM PDT 24
Peak memory 341392 kb
Host smart-7c91b55f-eac9-4177-9b37-671068d866a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272541112 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.3272541112
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1566003575
Short name T8
Test name
Test status
Simulation time 166543800 ps
CPU time 14.86 seconds
Started Jun 13 03:17:27 PM PDT 24
Finished Jun 13 03:17:43 PM PDT 24
Peak memory 261300 kb
Host smart-52d77e33-12af-4479-b62f-11d339052118
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566003575 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1566003575
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.82549809
Short name T15
Test name
Test status
Simulation time 282896795800 ps
CPU time 3197.67 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 04:11:08 PM PDT 24
Peak memory 265596 kb
Host smart-698a3a2f-0224-4461-a662-683a246fba2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82549809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST
_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_host_ctrl_arb.82549809
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2603362559
Short name T404
Test name
Test status
Simulation time 34444600 ps
CPU time 13.72 seconds
Started Jun 13 03:17:28 PM PDT 24
Finished Jun 13 03:17:42 PM PDT 24
Peak memory 258692 kb
Host smart-0961f1dc-b8f3-4430-b221-3a7afca761a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603362559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
603362559
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2509511061
Short name T221
Test name
Test status
Simulation time 115717200 ps
CPU time 19.62 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:16:00 PM PDT 24
Peak memory 263440 kb
Host smart-920af4db-7796-4ab2-8acf-d7d64464bd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509511061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
509511061
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.3603791120
Short name T152
Test name
Test status
Simulation time 184429300 ps
CPU time 100.77 seconds
Started Jun 13 03:17:12 PM PDT 24
Finished Jun 13 03:18:53 PM PDT 24
Peak memory 282324 kb
Host smart-aab6499b-5b7f-4606-8ea2-cd0547b70998
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603791120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.3603791120
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2155542327
Short name T219
Test name
Test status
Simulation time 1280375900 ps
CPU time 772.25 seconds
Started Jun 13 03:16:23 PM PDT 24
Finished Jun 13 03:29:16 PM PDT 24
Peak memory 263416 kb
Host smart-40ee2bc8-de7d-4547-8bf1-cbff63fe22b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155542327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2155542327
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3520612101
Short name T287
Test name
Test status
Simulation time 4201244800 ps
CPU time 131.14 seconds
Started Jun 13 03:27:06 PM PDT 24
Finished Jun 13 03:29:18 PM PDT 24
Peak memory 262996 kb
Host smart-b3eaabf0-4754-423f-8be0-8c13344333a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520612101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.3520612101
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3535769416
Short name T3
Test name
Test status
Simulation time 23219766900 ps
CPU time 712.33 seconds
Started Jun 13 03:24:15 PM PDT 24
Finished Jun 13 03:36:09 PM PDT 24
Peak memory 314804 kb
Host smart-c4ea1d7a-0548-4d4e-b18f-636fa0ea74fa
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535769416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.3535769416
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3742938269
Short name T299
Test name
Test status
Simulation time 47713300 ps
CPU time 13.37 seconds
Started Jun 13 03:17:01 PM PDT 24
Finished Jun 13 03:17:15 PM PDT 24
Peak memory 260896 kb
Host smart-a6c60e79-3c9d-4bda-9863-2be4c8ed10a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742938269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3742938269
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2788418001
Short name T153
Test name
Test status
Simulation time 15635500 ps
CPU time 13.18 seconds
Started Jun 13 03:18:12 PM PDT 24
Finished Jun 13 03:18:27 PM PDT 24
Peak memory 265372 kb
Host smart-87184202-521b-493c-8f83-d957bbe93586
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788418001 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2788418001
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.764344048
Short name T223
Test name
Test status
Simulation time 35969400 ps
CPU time 13.58 seconds
Started Jun 13 03:15:35 PM PDT 24
Finished Jun 13 03:15:49 PM PDT 24
Peak memory 261744 kb
Host smart-2fd7a9ef-b521-4c3e-8c68-54d5960017d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764344048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.764344048
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2740181921
Short name T136
Test name
Test status
Simulation time 3405770300 ps
CPU time 62.2 seconds
Started Jun 13 03:21:51 PM PDT 24
Finished Jun 13 03:22:54 PM PDT 24
Peak memory 263056 kb
Host smart-13d6c9a5-2464-4505-86ea-fbeaabd365c0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740181921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
740181921
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.87082332
Short name T56
Test name
Test status
Simulation time 3756925600 ps
CPU time 498.47 seconds
Started Jun 13 03:23:40 PM PDT 24
Finished Jun 13 03:31:59 PM PDT 24
Peak memory 314876 kb
Host smart-7a2f3469-4d7d-48bb-ac73-6acd514680e4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87082332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.flash_ctrl_rw.87082332
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.4017108365
Short name T657
Test name
Test status
Simulation time 10021340600 ps
CPU time 80.24 seconds
Started Jun 13 03:17:50 PM PDT 24
Finished Jun 13 03:19:11 PM PDT 24
Peak memory 320560 kb
Host smart-52055494-72b0-4d22-b3d2-714195eb8d83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017108365 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.4017108365
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.940066481
Short name T305
Test name
Test status
Simulation time 12683974400 ps
CPU time 192.92 seconds
Started Jun 13 03:17:22 PM PDT 24
Finished Jun 13 03:20:35 PM PDT 24
Peak memory 293540 kb
Host smart-2a042c07-445f-40f8-a48c-bbe9a12a2b43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940066481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.940066481
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2912407476
Short name T215
Test name
Test status
Simulation time 708798700 ps
CPU time 744.41 seconds
Started Jun 13 03:15:50 PM PDT 24
Finished Jun 13 03:28:16 PM PDT 24
Peak memory 263416 kb
Host smart-67f2cfa6-ae77-4289-a820-b72b1da53938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912407476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2912407476
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.1999385604
Short name T114
Test name
Test status
Simulation time 22458918000 ps
CPU time 419.72 seconds
Started Jun 13 03:17:05 PM PDT 24
Finished Jun 13 03:24:06 PM PDT 24
Peak memory 275220 kb
Host smart-d45a3cdd-3d0d-4ea0-853a-1ee529a0b04d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999385604 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.1999385604
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.616601652
Short name T203
Test name
Test status
Simulation time 224416000 ps
CPU time 20.38 seconds
Started Jun 13 03:15:51 PM PDT 24
Finished Jun 13 03:16:13 PM PDT 24
Peak memory 263412 kb
Host smart-6e721d0b-5889-4e0d-ae8e-716373f49108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616601652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.616601652
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.179454958
Short name T193
Test name
Test status
Simulation time 35364400 ps
CPU time 30.97 seconds
Started Jun 13 03:22:03 PM PDT 24
Finished Jun 13 03:22:35 PM PDT 24
Peak memory 277132 kb
Host smart-06f7243a-cdd4-4419-b28f-2330bb36ceea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179454958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_rw_evict.179454958
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1689117270
Short name T59
Test name
Test status
Simulation time 27923800 ps
CPU time 14.43 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 03:18:05 PM PDT 24
Peak memory 279808 kb
Host smart-ac88417e-6ddb-4b77-91d8-1a3d3dc5a0ab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1689117270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1689117270
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3533332787
Short name T50
Test name
Test status
Simulation time 856800200 ps
CPU time 19.03 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:18:01 PM PDT 24
Peak memory 264368 kb
Host smart-45e92e9b-b1c7-41d1-96ae-e30461d30a60
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533332787 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3533332787
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.410721573
Short name T321
Test name
Test status
Simulation time 172051600 ps
CPU time 35.32 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:18:16 PM PDT 24
Peak memory 275876 kb
Host smart-cee68cf6-8493-4036-8bda-34d54556016c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410721573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_re_evict.410721573
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2127559207
Short name T32
Test name
Test status
Simulation time 51019135700 ps
CPU time 240.58 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:21:41 PM PDT 24
Peak memory 265496 kb
Host smart-438406da-41ef-48cb-9199-c5e2ffeb93aa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212
7559207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2127559207
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.4177663357
Short name T94
Test name
Test status
Simulation time 33615400 ps
CPU time 13.98 seconds
Started Jun 13 03:21:45 PM PDT 24
Finished Jun 13 03:22:00 PM PDT 24
Peak memory 259828 kb
Host smart-376d6f22-a585-4f90-9118-9ecd1757ccb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177663357 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.4177663357
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.14841381
Short name T36
Test name
Test status
Simulation time 575031600 ps
CPU time 121.29 seconds
Started Jun 13 03:23:34 PM PDT 24
Finished Jun 13 03:25:37 PM PDT 24
Peak memory 293836 kb
Host smart-9bc2108f-cb65-4ce3-9951-c6bd6317d67b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14841381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash
_ctrl_intr_rd.14841381
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1810336488
Short name T85
Test name
Test status
Simulation time 30480100 ps
CPU time 20.58 seconds
Started Jun 13 03:17:42 PM PDT 24
Finished Jun 13 03:18:04 PM PDT 24
Peak memory 266016 kb
Host smart-deab8418-99b2-466d-8a6a-84da82677fc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810336488 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1810336488
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3601003161
Short name T280
Test name
Test status
Simulation time 83669900 ps
CPU time 17.56 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:15:58 PM PDT 24
Peak memory 269952 kb
Host smart-0321a12c-f3c3-4bfc-8e66-d26550d0bda0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601003161 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3601003161
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.429633959
Short name T225
Test name
Test status
Simulation time 54508200 ps
CPU time 13.23 seconds
Started Jun 13 03:15:53 PM PDT 24
Finished Jun 13 03:16:08 PM PDT 24
Peak memory 261700 kb
Host smart-584d3ce4-3c39-47b0-843e-25a66343e33b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429633959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.429633959
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.493375254
Short name T330
Test name
Test status
Simulation time 347682400 ps
CPU time 389.78 seconds
Started Jun 13 03:15:40 PM PDT 24
Finished Jun 13 03:22:11 PM PDT 24
Peak memory 263416 kb
Host smart-80920cc2-a304-471d-8988-5733b56dae86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493375254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
tl_intg_err.493375254
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.73192141
Short name T96
Test name
Test status
Simulation time 29508300 ps
CPU time 15.74 seconds
Started Jun 13 03:27:16 PM PDT 24
Finished Jun 13 03:27:33 PM PDT 24
Peak memory 275176 kb
Host smart-4d274a5b-5e63-490d-9830-aff74504bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73192141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.73192141
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3862192670
Short name T179
Test name
Test status
Simulation time 2171471400 ps
CPU time 176.66 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:20:38 PM PDT 24
Peak memory 296832 kb
Host smart-941e2532-c9ce-4e97-b18a-6a5c25390a60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862192670 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3862192670
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3608176014
Short name T95
Test name
Test status
Simulation time 15484700 ps
CPU time 13.78 seconds
Started Jun 13 03:22:14 PM PDT 24
Finished Jun 13 03:22:28 PM PDT 24
Peak memory 258932 kb
Host smart-df206f1b-6467-4696-a2df-63e1e1465a9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608176014 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3608176014
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2450066762
Short name T680
Test name
Test status
Simulation time 895706300 ps
CPU time 2549.25 seconds
Started Jun 13 03:17:09 PM PDT 24
Finished Jun 13 03:59:39 PM PDT 24
Peak memory 263628 kb
Host smart-ea1bc3fd-396e-49a9-bb7a-2b769b36cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450066762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2450066762
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3068639745
Short name T588
Test name
Test status
Simulation time 18656400 ps
CPU time 13.65 seconds
Started Jun 13 03:22:46 PM PDT 24
Finished Jun 13 03:23:00 PM PDT 24
Peak memory 260324 kb
Host smart-c27ca024-5560-43fc-a635-e8e65cd3a31f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068639745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3068639745
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.575833831
Short name T351
Test name
Test status
Simulation time 173771700 ps
CPU time 107.27 seconds
Started Jun 13 03:27:26 PM PDT 24
Finished Jun 13 03:29:14 PM PDT 24
Peak memory 262840 kb
Host smart-f6252b67-3074-49f6-a7e0-412a04a87bd7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575833831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_ot
p_reset.575833831
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2969478657
Short name T1002
Test name
Test status
Simulation time 10019614400 ps
CPU time 76.21 seconds
Started Jun 13 03:17:25 PM PDT 24
Finished Jun 13 03:18:42 PM PDT 24
Peak memory 292192 kb
Host smart-66aca8c1-0a99-49b9-9504-591053e36ace
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969478657 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2969478657
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.2230001299
Short name T1095
Test name
Test status
Simulation time 2054977800 ps
CPU time 69.15 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:18:49 PM PDT 24
Peak memory 264032 kb
Host smart-5812f493-b99a-47a3-b886-e45a5226da56
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230001299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2230001299
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2247129143
Short name T367
Test name
Test status
Simulation time 1604120200 ps
CPU time 62.59 seconds
Started Jun 13 03:17:38 PM PDT 24
Finished Jun 13 03:18:41 PM PDT 24
Peak memory 265200 kb
Host smart-8636eb87-0406-49ce-ac21-2d12459c5023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247129143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2247129143
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.1359249060
Short name T1081
Test name
Test status
Simulation time 555950800 ps
CPU time 133.13 seconds
Started Jun 13 03:23:09 PM PDT 24
Finished Jun 13 03:25:23 PM PDT 24
Peak memory 265700 kb
Host smart-809227e1-f76f-4811-8b21-2c4935098559
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359249060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.1359249060
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1874713391
Short name T364
Test name
Test status
Simulation time 1484728500 ps
CPU time 59.86 seconds
Started Jun 13 03:23:23 PM PDT 24
Finished Jun 13 03:24:24 PM PDT 24
Peak memory 264028 kb
Host smart-895e4eb0-6959-4b5e-a0cb-86fc3f48e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874713391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1874713391
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.740615793
Short name T320
Test name
Test status
Simulation time 323991300 ps
CPU time 32.34 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:24:45 PM PDT 24
Peak memory 275872 kb
Host smart-c93af163-3b53-434b-8d99-70cc862ffdad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740615793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.740615793
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.657520899
Short name T194
Test name
Test status
Simulation time 78941700 ps
CPU time 28.45 seconds
Started Jun 13 03:24:51 PM PDT 24
Finished Jun 13 03:25:22 PM PDT 24
Peak memory 275800 kb
Host smart-969e6eff-ce47-4e2f-8e14-b72dca273939
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657520899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_rw_evict.657520899
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3596222092
Short name T374
Test name
Test status
Simulation time 918925300 ps
CPU time 59.35 seconds
Started Jun 13 03:26:52 PM PDT 24
Finished Jun 13 03:27:52 PM PDT 24
Peak memory 263584 kb
Host smart-68365309-9a7a-4323-b688-15f6591a451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596222092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3596222092
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2412194430
Short name T53
Test name
Test status
Simulation time 1385725200 ps
CPU time 27.97 seconds
Started Jun 13 03:17:34 PM PDT 24
Finished Jun 13 03:18:04 PM PDT 24
Peak memory 262968 kb
Host smart-82f2ba6d-74ec-4583-b8a8-a7ed334fff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412194430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2412194430
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.2727291678
Short name T481
Test name
Test status
Simulation time 31933600 ps
CPU time 28.47 seconds
Started Jun 13 03:24:09 PM PDT 24
Finished Jun 13 03:24:39 PM PDT 24
Peak memory 275864 kb
Host smart-6bd896df-b388-4985-a366-30dac0b13944
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727291678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.2727291678
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3031909896
Short name T201
Test name
Test status
Simulation time 72402000 ps
CPU time 14.17 seconds
Started Jun 13 03:18:13 PM PDT 24
Finished Jun 13 03:18:29 PM PDT 24
Peak memory 265340 kb
Host smart-93b89fc7-07e7-400e-bc9b-3b304096db6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031909896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3031909896
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.3471145307
Short name T35
Test name
Test status
Simulation time 3942131000 ps
CPU time 212.23 seconds
Started Jun 13 03:25:22 PM PDT 24
Finished Jun 13 03:28:56 PM PDT 24
Peak memory 293464 kb
Host smart-0c1da6d0-e3d3-4422-815d-fd04b16554bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471145307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.3471145307
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.1121886679
Short name T46
Test name
Test status
Simulation time 42068100 ps
CPU time 13.82 seconds
Started Jun 13 03:17:26 PM PDT 24
Finished Jun 13 03:17:40 PM PDT 24
Peak memory 261768 kb
Host smart-c39a1667-5c7a-445b-8946-6f0e30d2ca40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121886679 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1121886679
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.4285615471
Short name T342
Test name
Test status
Simulation time 39294600 ps
CPU time 21.56 seconds
Started Jun 13 03:22:04 PM PDT 24
Finished Jun 13 03:22:26 PM PDT 24
Peak memory 265944 kb
Host smart-bbcebf0b-5c02-41f6-8b0e-70147ca09b17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285615471 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.4285615471
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.4134021637
Short name T26
Test name
Test status
Simulation time 19188400 ps
CPU time 22.57 seconds
Started Jun 13 03:19:49 PM PDT 24
Finished Jun 13 03:20:12 PM PDT 24
Peak memory 274156 kb
Host smart-69c68c4e-3e86-43c2-bf30-af5fb7f01f8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134021637 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.4134021637
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.699676644
Short name T57
Test name
Test status
Simulation time 15897868200 ps
CPU time 4689.99 seconds
Started Jun 13 03:17:23 PM PDT 24
Finished Jun 13 04:35:34 PM PDT 24
Peak memory 290904 kb
Host smart-ea434208-b776-4d83-8849-22f133e81433
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699676644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.699676644
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.2912389546
Short name T112
Test name
Test status
Simulation time 716807300 ps
CPU time 17.25 seconds
Started Jun 13 03:17:27 PM PDT 24
Finished Jun 13 03:17:44 PM PDT 24
Peak memory 264608 kb
Host smart-bd7a1470-82a6-42a4-b5ee-d2383067c5a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912389546 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2912389546
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2951188013
Short name T113
Test name
Test status
Simulation time 785649400 ps
CPU time 22.77 seconds
Started Jun 13 03:19:19 PM PDT 24
Finished Jun 13 03:19:42 PM PDT 24
Peak memory 266084 kb
Host smart-6c9cd185-badf-4226-8bd2-3a2fd09665ed
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951188013 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.2951188013
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1021916191
Short name T301
Test name
Test status
Simulation time 132892000 ps
CPU time 13.19 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:15:52 PM PDT 24
Peak memory 260888 kb
Host smart-95ec577a-fe4b-4e61-8391-d4221e16d1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021916191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1
021916191
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.725343373
Short name T329
Test name
Test status
Simulation time 324376000 ps
CPU time 16.42 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:42 PM PDT 24
Peak memory 270988 kb
Host smart-f043288b-1447-4dbe-9201-6f8e1d53f43f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725343373 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.725343373
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1690527277
Short name T336
Test name
Test status
Simulation time 339670500 ps
CPU time 895.95 seconds
Started Jun 13 03:16:24 PM PDT 24
Finished Jun 13 03:31:20 PM PDT 24
Peak memory 263396 kb
Host smart-cbdebf8c-02fc-490a-8920-72e0ec200203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690527277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1690527277
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.684763022
Short name T337
Test name
Test status
Simulation time 1327981300 ps
CPU time 760.18 seconds
Started Jun 13 03:16:40 PM PDT 24
Finished Jun 13 03:29:21 PM PDT 24
Peak memory 263360 kb
Host smart-512b52f6-2737-43d7-8955-635dbf20e60f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684763022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.684763022
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3976452264
Short name T334
Test name
Test status
Simulation time 652660600 ps
CPU time 890.34 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:31:06 PM PDT 24
Peak memory 263364 kb
Host smart-c6c6cc64-fe67-4b77-8385-38a8a449f964
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976452264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.3976452264
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.760879813
Short name T130
Test name
Test status
Simulation time 127059600 ps
CPU time 31.85 seconds
Started Jun 13 03:17:41 PM PDT 24
Finished Jun 13 03:18:15 PM PDT 24
Peak memory 268064 kb
Host smart-3d4f086b-1487-4a98-a3a1-a17481606820
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760879813 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.760879813
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3209728142
Short name T88
Test name
Test status
Simulation time 39422400 ps
CPU time 22.05 seconds
Started Jun 13 03:21:44 PM PDT 24
Finished Jun 13 03:22:07 PM PDT 24
Peak memory 265984 kb
Host smart-bc5a2268-b327-407c-accb-5a37da1d4f47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209728142 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3209728142
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2937546579
Short name T636
Test name
Test status
Simulation time 50128512800 ps
CPU time 966.44 seconds
Started Jun 13 03:22:37 PM PDT 24
Finished Jun 13 03:38:44 PM PDT 24
Peak memory 264668 kb
Host smart-b3b5f020-c34c-49d7-bcb9-137f13f0df8e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937546579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2937546579
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2917094134
Short name T363
Test name
Test status
Simulation time 2009904800 ps
CPU time 78.63 seconds
Started Jun 13 03:22:38 PM PDT 24
Finished Jun 13 03:23:58 PM PDT 24
Peak memory 263984 kb
Host smart-36b4cdad-4dbc-427c-80dc-dbd82657ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917094134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2917094134
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.3094639930
Short name T324
Test name
Test status
Simulation time 29654401800 ps
CPU time 568.98 seconds
Started Jun 13 03:24:11 PM PDT 24
Finished Jun 13 03:33:43 PM PDT 24
Peak memory 310372 kb
Host smart-ebb91d1b-9a67-486a-866d-c83495b2ae2f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094639930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.3094639930
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1403798468
Short name T372
Test name
Test status
Simulation time 4384784800 ps
CPU time 63.14 seconds
Started Jun 13 03:24:32 PM PDT 24
Finished Jun 13 03:25:36 PM PDT 24
Peak memory 263888 kb
Host smart-816b7327-7a63-444d-aac0-af0fad4507db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403798468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1403798468
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.685490436
Short name T377
Test name
Test status
Simulation time 1572444700 ps
CPU time 65.11 seconds
Started Jun 13 03:24:57 PM PDT 24
Finished Jun 13 03:26:03 PM PDT 24
Peak memory 264120 kb
Host smart-f4f74946-2fec-4e18-a03b-a8660665678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685490436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.685490436
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3722297411
Short name T360
Test name
Test status
Simulation time 369939500 ps
CPU time 49.73 seconds
Started Jun 13 03:25:49 PM PDT 24
Finished Jun 13 03:26:40 PM PDT 24
Peak memory 264032 kb
Host smart-cef3b8ca-f338-4ed1-974e-2b374537060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722297411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3722297411
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1111484624
Short name T89
Test name
Test status
Simulation time 24689200 ps
CPU time 21.83 seconds
Started Jun 13 03:25:53 PM PDT 24
Finished Jun 13 03:26:16 PM PDT 24
Peak memory 265976 kb
Host smart-db285de1-d4aa-4564-8bca-1f177497f81f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111484624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1111484624
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2332296690
Short name T86
Test name
Test status
Simulation time 14899800 ps
CPU time 22.18 seconds
Started Jun 13 03:26:57 PM PDT 24
Finished Jun 13 03:27:20 PM PDT 24
Peak memory 274160 kb
Host smart-d64e1b39-655d-4423-8a39-831b2727db04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332296690 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2332296690
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1387176613
Short name T325
Test name
Test status
Simulation time 416082100 ps
CPU time 37.59 seconds
Started Jun 13 03:19:49 PM PDT 24
Finished Jun 13 03:20:27 PM PDT 24
Peak memory 270616 kb
Host smart-b65043b1-b6b2-462f-98e4-e40d2e3dcd0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387176613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1387176613
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.228777258
Short name T180
Test name
Test status
Simulation time 49410900 ps
CPU time 131.17 seconds
Started Jun 13 03:20:42 PM PDT 24
Finished Jun 13 03:22:54 PM PDT 24
Peak memory 265116 kb
Host smart-9d828d35-61da-4005-943e-20a6eaf8426b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228777258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.228777258
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.2015302447
Short name T197
Test name
Test status
Simulation time 6427191400 ps
CPU time 74.5 seconds
Started Jun 13 03:22:16 PM PDT 24
Finished Jun 13 03:23:31 PM PDT 24
Peak memory 260856 kb
Host smart-2c5c690e-816a-4bcd-a12b-c10ea68b4fa1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015302447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2
015302447
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.3662865962
Short name T60
Test name
Test status
Simulation time 14407563200 ps
CPU time 490.12 seconds
Started Jun 13 03:22:58 PM PDT 24
Finished Jun 13 03:31:09 PM PDT 24
Peak memory 310004 kb
Host smart-a2f55fca-fefb-4b4d-830f-7d9bd9058928
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662865962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.3662865962
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.2254347419
Short name T68
Test name
Test status
Simulation time 44273200 ps
CPU time 14.3 seconds
Started Jun 13 03:18:12 PM PDT 24
Finished Jun 13 03:18:28 PM PDT 24
Peak memory 261480 kb
Host smart-4bf4b610-a599-4a3e-904e-1c494e6ff10a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2254347419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2254347419
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.532254619
Short name T160
Test name
Test status
Simulation time 80140320900 ps
CPU time 894 seconds
Started Jun 13 03:20:21 PM PDT 24
Finished Jun 13 03:35:16 PM PDT 24
Peak memory 264580 kb
Host smart-b8bbed1f-7b6d-4cdb-b422-979acfa9415a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532254619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.flash_ctrl_hw_rma_reset.532254619
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1901484695
Short name T1217
Test name
Test status
Simulation time 41078200 ps
CPU time 16.99 seconds
Started Jun 13 03:15:35 PM PDT 24
Finished Jun 13 03:15:53 PM PDT 24
Peak memory 263400 kb
Host smart-3a0ab7bb-54aa-4a04-b219-34058a916cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901484695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1
901484695
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2864287444
Short name T122
Test name
Test status
Simulation time 5406477900 ps
CPU time 2494.87 seconds
Started Jun 13 03:17:15 PM PDT 24
Finished Jun 13 03:58:51 PM PDT 24
Peak memory 263136 kb
Host smart-833ee017-a782-4377-af67-93833ac2d265
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864287444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2864287444
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3667308909
Short name T727
Test name
Test status
Simulation time 398978400 ps
CPU time 988.39 seconds
Started Jun 13 03:17:06 PM PDT 24
Finished Jun 13 03:33:36 PM PDT 24
Peak memory 270708 kb
Host smart-b449db66-514c-4121-8d0c-f544c20af8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667308909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3667308909
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2972934253
Short name T731
Test name
Test status
Simulation time 1450950400 ps
CPU time 119.05 seconds
Started Jun 13 03:17:06 PM PDT 24
Finished Jun 13 03:19:07 PM PDT 24
Peak memory 263012 kb
Host smart-3c3a3f18-4093-4e32-ad9d-a3726fa94538
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2972934253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2972934253
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.460280364
Short name T775
Test name
Test status
Simulation time 607219400 ps
CPU time 138.58 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:19:33 PM PDT 24
Peak memory 282380 kb
Host smart-2064ad77-87d1-42c5-862b-f71296a34efe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
460280364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.460280364
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4060136662
Short name T189
Test name
Test status
Simulation time 654701623800 ps
CPU time 2141.04 seconds
Started Jun 13 03:17:36 PM PDT 24
Finished Jun 13 03:53:18 PM PDT 24
Peak memory 265592 kb
Host smart-ebc3376c-82db-42de-8e68-359a267fba2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060136662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4060136662
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.364250710
Short name T65
Test name
Test status
Simulation time 3225775900 ps
CPU time 900.96 seconds
Started Jun 13 03:22:09 PM PDT 24
Finished Jun 13 03:37:11 PM PDT 24
Peak memory 287648 kb
Host smart-90603347-08e3-4bcb-b50f-da9e5cd475be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364250710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.364250710
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.40677324
Short name T105
Test name
Test status
Simulation time 381560640000 ps
CPU time 2140.74 seconds
Started Jun 13 03:18:58 PM PDT 24
Finished Jun 13 03:54:39 PM PDT 24
Peak memory 264368 kb
Host smart-5f56b58b-1f62-42cf-9530-eb703eb40b84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40677324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST
_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_host_ctrl_arb.40677324
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3372262964
Short name T98
Test name
Test status
Simulation time 429328100 ps
CPU time 49.12 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:16:29 PM PDT 24
Peak memory 261000 kb
Host smart-237692db-ee9c-4d77-9c47-515272f27236
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372262964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.3372262964
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4157591885
Short name T286
Test name
Test status
Simulation time 3185593600 ps
CPU time 39.68 seconds
Started Jun 13 03:15:40 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 260892 kb
Host smart-f8d6b349-d4e4-4ab7-b701-3bf6dc5c7692
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157591885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.4157591885
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.746830190
Short name T1227
Test name
Test status
Simulation time 70565800 ps
CPU time 30.89 seconds
Started Jun 13 03:15:37 PM PDT 24
Finished Jun 13 03:16:08 PM PDT 24
Peak memory 260880 kb
Host smart-5d4c4712-a386-4869-b60d-26bf7828e679
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746830190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_hw_reset.746830190
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3504668367
Short name T1167
Test name
Test status
Simulation time 43578000 ps
CPU time 16.46 seconds
Started Jun 13 03:15:53 PM PDT 24
Finished Jun 13 03:16:11 PM PDT 24
Peak memory 260964 kb
Host smart-eb726258-1193-4c4b-9dc3-3d4fb89d35be
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504668367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3504668367
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.7637610
Short name T1170
Test name
Test status
Simulation time 18368600 ps
CPU time 13.36 seconds
Started Jun 13 03:15:33 PM PDT 24
Finished Jun 13 03:15:48 PM PDT 24
Peak memory 260888 kb
Host smart-7a7b3838-cabd-4f06-abd4-2f4f3e2a2828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7637610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.7637610
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2185747907
Short name T1229
Test name
Test status
Simulation time 33797600 ps
CPU time 13.14 seconds
Started Jun 13 03:15:34 PM PDT 24
Finished Jun 13 03:15:48 PM PDT 24
Peak memory 260812 kb
Host smart-7e7fe9eb-1825-4579-9443-4d7cfd9e5c63
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185747907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.2185747907
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.282780988
Short name T1158
Test name
Test status
Simulation time 924560800 ps
CPU time 18.46 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:15:58 PM PDT 24
Peak memory 262528 kb
Host smart-6fd90457-506f-42fe-aaac-661f6dfa045f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282780988 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.282780988
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.201442410
Short name T1103
Test name
Test status
Simulation time 11159600 ps
CPU time 15.66 seconds
Started Jun 13 03:15:36 PM PDT 24
Finished Jun 13 03:15:53 PM PDT 24
Peak memory 252628 kb
Host smart-33089260-cf41-44a1-8910-2c3266dbe7c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201442410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.201442410
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1710167675
Short name T1121
Test name
Test status
Simulation time 37631500 ps
CPU time 15.81 seconds
Started Jun 13 03:15:34 PM PDT 24
Finished Jun 13 03:15:51 PM PDT 24
Peak memory 252492 kb
Host smart-fa9927fb-b053-4129-b06b-2588537f00d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710167675 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.1710167675
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2508636668
Short name T222
Test name
Test status
Simulation time 375955800 ps
CPU time 459.48 seconds
Started Jun 13 03:15:36 PM PDT 24
Finished Jun 13 03:23:16 PM PDT 24
Peak memory 263416 kb
Host smart-8c712575-1e99-4333-b7e0-2de79db59bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508636668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2508636668
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1112756890
Short name T1177
Test name
Test status
Simulation time 927335600 ps
CPU time 43.22 seconds
Started Jun 13 03:15:45 PM PDT 24
Finished Jun 13 03:16:28 PM PDT 24
Peak memory 260812 kb
Host smart-bde663eb-ec30-4a0a-85a4-3ea3f5e4c483
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112756890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1112756890
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3349968583
Short name T1193
Test name
Test status
Simulation time 4550368400 ps
CPU time 76.36 seconds
Started Jun 13 03:15:46 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 261020 kb
Host smart-faed12e3-a1e9-4da9-90b6-603615537e73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349968583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3349968583
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.798029479
Short name T1116
Test name
Test status
Simulation time 55287400 ps
CPU time 26.52 seconds
Started Jun 13 03:15:36 PM PDT 24
Finished Jun 13 03:16:04 PM PDT 24
Peak memory 261016 kb
Host smart-190d3774-137e-439b-bb68-2548859e2a98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798029479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.798029479
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.374073227
Short name T1169
Test name
Test status
Simulation time 38204300 ps
CPU time 19.36 seconds
Started Jun 13 03:15:44 PM PDT 24
Finished Jun 13 03:16:04 PM PDT 24
Peak memory 277584 kb
Host smart-a9b16106-e8c0-4e82-bd2e-f25fbcd72e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374073227 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.374073227
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1173207756
Short name T1230
Test name
Test status
Simulation time 132000500 ps
CPU time 16.97 seconds
Started Jun 13 03:15:43 PM PDT 24
Finished Jun 13 03:16:00 PM PDT 24
Peak memory 261272 kb
Host smart-0d31f577-fa4a-490c-b077-5a1de0d9ceee
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173207756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1173207756
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.963268725
Short name T1153
Test name
Test status
Simulation time 28599900 ps
CPU time 13.26 seconds
Started Jun 13 03:15:39 PM PDT 24
Finished Jun 13 03:15:53 PM PDT 24
Peak memory 260872 kb
Host smart-b72554fb-631d-4fd6-946b-91baa3b6513e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963268725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.963268725
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1703351571
Short name T1231
Test name
Test status
Simulation time 194051100 ps
CPU time 35.28 seconds
Started Jun 13 03:15:44 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 260940 kb
Host smart-f0c29caf-d3b0-4d4e-82a3-63f312339636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703351571 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1703351571
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.12738079
Short name T1098
Test name
Test status
Simulation time 18306300 ps
CPU time 13.05 seconds
Started Jun 13 03:15:45 PM PDT 24
Finished Jun 13 03:15:59 PM PDT 24
Peak memory 252676 kb
Host smart-0a613db7-917a-4b71-a661-98ce1cda0244
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12738079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.12738079
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1141531270
Short name T1196
Test name
Test status
Simulation time 22657800 ps
CPU time 15.48 seconds
Started Jun 13 03:15:38 PM PDT 24
Finished Jun 13 03:15:54 PM PDT 24
Peak memory 252780 kb
Host smart-4db3e6af-69d4-4487-a3da-c8fcc517497a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141531270 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1141531270
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.958592634
Short name T1240
Test name
Test status
Simulation time 107327700 ps
CPU time 17.47 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:43 PM PDT 24
Peak memory 260952 kb
Host smart-93fe19ce-15b0-4b72-8790-24d1e0f7c5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958592634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.958592634
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2412468859
Short name T300
Test name
Test status
Simulation time 118797400 ps
CPU time 13.32 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:38 PM PDT 24
Peak memory 260824 kb
Host smart-046a58af-d6f7-4ded-9969-5258fa37665e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412468859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2412468859
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1373620883
Short name T279
Test name
Test status
Simulation time 182845400 ps
CPU time 18.59 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:44 PM PDT 24
Peak memory 260956 kb
Host smart-196b63b2-3d5b-45cb-b2fb-33c2f9ba501f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373620883 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1373620883
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3171091232
Short name T1111
Test name
Test status
Simulation time 13997100 ps
CPU time 15.85 seconds
Started Jun 13 03:16:19 PM PDT 24
Finished Jun 13 03:16:35 PM PDT 24
Peak memory 252612 kb
Host smart-e503483e-1c25-45bd-b510-bcad5dcc35aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171091232 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3171091232
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2654231369
Short name T1207
Test name
Test status
Simulation time 20117700 ps
CPU time 16.05 seconds
Started Jun 13 03:16:21 PM PDT 24
Finished Jun 13 03:16:37 PM PDT 24
Peak memory 252604 kb
Host smart-413f3e7c-c181-40d6-b5b6-e767eea7e38f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654231369 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2654231369
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.917685198
Short name T1163
Test name
Test status
Simulation time 34813100 ps
CPU time 15.87 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:16:48 PM PDT 24
Peak memory 263440 kb
Host smart-1b421526-c2c3-4b63-830c-fc7916017327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917685198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.917685198
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.854336373
Short name T1211
Test name
Test status
Simulation time 187976100 ps
CPU time 19.92 seconds
Started Jun 13 03:16:27 PM PDT 24
Finished Jun 13 03:16:47 PM PDT 24
Peak memory 271640 kb
Host smart-5ad32eee-62a3-40dd-9f36-a2b14dbbbcfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854336373 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.854336373
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.240608597
Short name T1141
Test name
Test status
Simulation time 96078300 ps
CPU time 14.35 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:40 PM PDT 24
Peak memory 261188 kb
Host smart-b511aad8-20e6-4b54-850d-e5459900333c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240608597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_csr_rw.240608597
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3216167048
Short name T1142
Test name
Test status
Simulation time 24265400 ps
CPU time 13.32 seconds
Started Jun 13 03:16:27 PM PDT 24
Finished Jun 13 03:16:41 PM PDT 24
Peak memory 260888 kb
Host smart-ead549c1-8d55-4386-b6ca-642534cb044b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216167048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
3216167048
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2319020374
Short name T1226
Test name
Test status
Simulation time 126183500 ps
CPU time 17.9 seconds
Started Jun 13 03:16:25 PM PDT 24
Finished Jun 13 03:16:44 PM PDT 24
Peak memory 263400 kb
Host smart-f852621d-8c09-4896-93a6-3f48890701dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319020374 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2319020374
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2464019803
Short name T1101
Test name
Test status
Simulation time 30809500 ps
CPU time 15.63 seconds
Started Jun 13 03:16:26 PM PDT 24
Finished Jun 13 03:16:42 PM PDT 24
Peak memory 252740 kb
Host smart-00cd7005-1788-4fba-858f-36c356ab1b5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464019803 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2464019803
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1452348300
Short name T1144
Test name
Test status
Simulation time 17830200 ps
CPU time 15.61 seconds
Started Jun 13 03:16:27 PM PDT 24
Finished Jun 13 03:16:43 PM PDT 24
Peak memory 252612 kb
Host smart-dd08e442-87e4-4d0c-b5c5-ab14a7c6a2fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452348300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1452348300
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3464794627
Short name T1138
Test name
Test status
Simulation time 566392400 ps
CPU time 20.71 seconds
Started Jun 13 03:16:27 PM PDT 24
Finished Jun 13 03:16:48 PM PDT 24
Peak memory 263436 kb
Host smart-2e97f45b-16e0-4a5c-a08a-2fa337cdecb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464794627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
3464794627
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.61162517
Short name T216
Test name
Test status
Simulation time 89770900 ps
CPU time 16.25 seconds
Started Jun 13 03:16:33 PM PDT 24
Finished Jun 13 03:16:51 PM PDT 24
Peak memory 271644 kb
Host smart-7545c267-faa0-410b-bcb7-c0d3eb74a92b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61162517 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.61162517
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1816957067
Short name T1110
Test name
Test status
Simulation time 286867000 ps
CPU time 16.57 seconds
Started Jun 13 03:16:33 PM PDT 24
Finished Jun 13 03:16:51 PM PDT 24
Peak memory 263436 kb
Host smart-0b84e3c1-26a2-477c-a647-2ef87614d792
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816957067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1816957067
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3055740575
Short name T1115
Test name
Test status
Simulation time 46626300 ps
CPU time 13.38 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:16:45 PM PDT 24
Peak memory 260744 kb
Host smart-f9dd2c8d-335b-4dc3-a7d0-4fe7e1042faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055740575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3055740575
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.814595379
Short name T62
Test name
Test status
Simulation time 126860900 ps
CPU time 28.98 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:17:01 PM PDT 24
Peak memory 261012 kb
Host smart-779d6198-b07a-4b6b-b36b-82a9c88239e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814595379 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.814595379
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1019706092
Short name T1100
Test name
Test status
Simulation time 14414300 ps
CPU time 15.86 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:16:48 PM PDT 24
Peak memory 252732 kb
Host smart-9975d87c-acd8-4bbb-a685-452c4084a0ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019706092 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1019706092
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3766645246
Short name T1161
Test name
Test status
Simulation time 44837200 ps
CPU time 15.69 seconds
Started Jun 13 03:16:33 PM PDT 24
Finished Jun 13 03:16:50 PM PDT 24
Peak memory 252612 kb
Host smart-552ce86e-33fa-4199-9d08-79746b1d6e1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766645246 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.3766645246
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2269302087
Short name T1234
Test name
Test status
Simulation time 230617300 ps
CPU time 19.26 seconds
Started Jun 13 03:16:33 PM PDT 24
Finished Jun 13 03:16:53 PM PDT 24
Peak memory 263440 kb
Host smart-ca9db13e-5da2-4cac-ba1a-3bf1192e6ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269302087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2269302087
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3336627894
Short name T1235
Test name
Test status
Simulation time 6000469000 ps
CPU time 462.15 seconds
Started Jun 13 03:16:32 PM PDT 24
Finished Jun 13 03:24:15 PM PDT 24
Peak memory 263420 kb
Host smart-5a748687-7411-45b6-bc65-47f288b6518c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336627894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3336627894
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2927785580
Short name T1204
Test name
Test status
Simulation time 55710200 ps
CPU time 17.56 seconds
Started Jun 13 03:16:40 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 271612 kb
Host smart-0abaada7-5005-4df2-a981-548483a3abfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927785580 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2927785580
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2836995120
Short name T1157
Test name
Test status
Simulation time 173500500 ps
CPU time 17.12 seconds
Started Jun 13 03:16:38 PM PDT 24
Finished Jun 13 03:16:56 PM PDT 24
Peak memory 263372 kb
Host smart-5865acb6-ff8f-4d41-9348-a49869b45fd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836995120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.2836995120
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.543787889
Short name T256
Test name
Test status
Simulation time 24474900 ps
CPU time 13.58 seconds
Started Jun 13 03:16:38 PM PDT 24
Finished Jun 13 03:16:52 PM PDT 24
Peak memory 260892 kb
Host smart-910fe2af-1535-48e5-bac9-07df398e56ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543787889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.543787889
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1948372049
Short name T1114
Test name
Test status
Simulation time 132221900 ps
CPU time 17.62 seconds
Started Jun 13 03:16:37 PM PDT 24
Finished Jun 13 03:16:55 PM PDT 24
Peak memory 261108 kb
Host smart-5fec5615-3e03-4f13-97b3-34222363d930
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948372049 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1948372049
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.257682485
Short name T1186
Test name
Test status
Simulation time 20520300 ps
CPU time 13 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:16:45 PM PDT 24
Peak memory 252624 kb
Host smart-86459146-707e-4ab9-94fb-c6b3a1cc4518
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257682485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.257682485
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1343886216
Short name T1180
Test name
Test status
Simulation time 20557900 ps
CPU time 15.46 seconds
Started Jun 13 03:16:39 PM PDT 24
Finished Jun 13 03:16:55 PM PDT 24
Peak memory 252740 kb
Host smart-28ad6ffc-a490-494a-b3f3-5cfac18268e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343886216 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1343886216
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2635393952
Short name T255
Test name
Test status
Simulation time 69986300 ps
CPU time 18.28 seconds
Started Jun 13 03:16:31 PM PDT 24
Finished Jun 13 03:16:51 PM PDT 24
Peak memory 263436 kb
Host smart-9c358bc2-a7d4-4278-8a34-d7a7aefe57bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635393952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2635393952
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.661326533
Short name T338
Test name
Test status
Simulation time 366230600 ps
CPU time 385.42 seconds
Started Jun 13 03:16:30 PM PDT 24
Finished Jun 13 03:22:56 PM PDT 24
Peak memory 263420 kb
Host smart-038f322e-7217-4211-b821-e4baae0f95c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661326533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_tl_intg_err.661326533
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1351201725
Short name T202
Test name
Test status
Simulation time 371599100 ps
CPU time 16.96 seconds
Started Jun 13 03:16:40 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 278120 kb
Host smart-93efb10f-3d00-437b-bf59-b9ff38147b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351201725 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1351201725
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3404227804
Short name T1162
Test name
Test status
Simulation time 118581500 ps
CPU time 17.17 seconds
Started Jun 13 03:16:38 PM PDT 24
Finished Jun 13 03:16:56 PM PDT 24
Peak memory 263404 kb
Host smart-b4596463-f498-44bd-8ef6-4e6b71c24cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404227804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3404227804
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1446325337
Short name T297
Test name
Test status
Simulation time 47060400 ps
CPU time 13.32 seconds
Started Jun 13 03:16:39 PM PDT 24
Finished Jun 13 03:16:53 PM PDT 24
Peak memory 260892 kb
Host smart-7d0ce9ae-9341-4d22-bd5d-6f903c635030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446325337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1446325337
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2246373992
Short name T1199
Test name
Test status
Simulation time 204429800 ps
CPU time 18.61 seconds
Started Jun 13 03:16:39 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 263344 kb
Host smart-e063faf1-0e55-47ad-99df-7572c820b982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246373992 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2246373992
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1128922256
Short name T1105
Test name
Test status
Simulation time 38757600 ps
CPU time 13.19 seconds
Started Jun 13 03:16:39 PM PDT 24
Finished Jun 13 03:16:53 PM PDT 24
Peak memory 252680 kb
Host smart-8691cc98-0169-4cc1-8614-9525211d05d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128922256 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1128922256
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4187558609
Short name T1130
Test name
Test status
Simulation time 20148700 ps
CPU time 15.5 seconds
Started Jun 13 03:16:36 PM PDT 24
Finished Jun 13 03:16:51 PM PDT 24
Peak memory 252692 kb
Host smart-61527fe2-9073-4c27-b6ce-f916afe31ce7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187558609 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.4187558609
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3106345371
Short name T264
Test name
Test status
Simulation time 73282100 ps
CPU time 16.57 seconds
Started Jun 13 03:16:37 PM PDT 24
Finished Jun 13 03:16:55 PM PDT 24
Peak memory 263444 kb
Host smart-fe378ca6-0165-443e-bc6e-36a6f9dcc5b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106345371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3106345371
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.161539715
Short name T1112
Test name
Test status
Simulation time 95832400 ps
CPU time 17.27 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 263436 kb
Host smart-72149205-70fc-4067-bb82-dfbff502ce88
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161539715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.161539715
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.536222323
Short name T1159
Test name
Test status
Simulation time 16871800 ps
CPU time 13.38 seconds
Started Jun 13 03:16:43 PM PDT 24
Finished Jun 13 03:16:57 PM PDT 24
Peak memory 260752 kb
Host smart-094e84c4-0053-4566-9f21-5513ea0a0b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536222323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.536222323
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2166469890
Short name T1156
Test name
Test status
Simulation time 484287000 ps
CPU time 18.5 seconds
Started Jun 13 03:16:45 PM PDT 24
Finished Jun 13 03:17:05 PM PDT 24
Peak memory 263372 kb
Host smart-e53d477a-ba57-4297-aa96-cdc45c550ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166469890 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2166469890
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.971792512
Short name T1140
Test name
Test status
Simulation time 11364600 ps
CPU time 13.11 seconds
Started Jun 13 03:16:40 PM PDT 24
Finished Jun 13 03:16:53 PM PDT 24
Peak memory 252696 kb
Host smart-38762bc9-b7fe-4c9c-b358-d0c4df73fb2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971792512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.971792512
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2488799159
Short name T1213
Test name
Test status
Simulation time 25237900 ps
CPU time 13.21 seconds
Started Jun 13 03:16:43 PM PDT 24
Finished Jun 13 03:16:57 PM PDT 24
Peak memory 252608 kb
Host smart-c1d03962-30d4-43c3-baf2-24d6426c107e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488799159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.2488799159
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.277732283
Short name T263
Test name
Test status
Simulation time 221402400 ps
CPU time 19.87 seconds
Started Jun 13 03:16:37 PM PDT 24
Finished Jun 13 03:16:57 PM PDT 24
Peak memory 263436 kb
Host smart-5c647a36-0818-4680-8e60-515cff5b080f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277732283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.277732283
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.372255694
Short name T217
Test name
Test status
Simulation time 30179900 ps
CPU time 18.04 seconds
Started Jun 13 03:16:42 PM PDT 24
Finished Jun 13 03:17:01 PM PDT 24
Peak memory 271644 kb
Host smart-64f76697-1bbe-4619-b225-3724130b44ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372255694 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.372255694
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4163601153
Short name T242
Test name
Test status
Simulation time 57701400 ps
CPU time 13.99 seconds
Started Jun 13 03:16:43 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 263400 kb
Host smart-dcd85012-91db-4fa1-805d-b7438b1319aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163601153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.4163601153
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.369779098
Short name T1216
Test name
Test status
Simulation time 16727800 ps
CPU time 13.58 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:16:59 PM PDT 24
Peak memory 260764 kb
Host smart-8638fa10-6738-46e0-9342-668be9bda8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369779098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.369779098
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3801483085
Short name T1190
Test name
Test status
Simulation time 324389100 ps
CPU time 18.34 seconds
Started Jun 13 03:16:45 PM PDT 24
Finished Jun 13 03:17:04 PM PDT 24
Peak memory 263344 kb
Host smart-ec1ab0b5-40d3-4918-9543-c2f40ff627a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801483085 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3801483085
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3736442331
Short name T1221
Test name
Test status
Simulation time 14623900 ps
CPU time 16.21 seconds
Started Jun 13 03:16:42 PM PDT 24
Finished Jun 13 03:17:00 PM PDT 24
Peak memory 252484 kb
Host smart-8ea4ebc4-ef73-4c2c-adb7-b8a7874f20ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736442331 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3736442331
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1843227037
Short name T1133
Test name
Test status
Simulation time 18625600 ps
CPU time 13.16 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 252624 kb
Host smart-ebafe17c-6673-4263-87e7-22a054e0cacf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843227037 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.1843227037
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.430596599
Short name T262
Test name
Test status
Simulation time 54318400 ps
CPU time 20.55 seconds
Started Jun 13 03:16:42 PM PDT 24
Finished Jun 13 03:17:04 PM PDT 24
Peak memory 263436 kb
Host smart-f79afede-5cc6-4e15-adc9-7c240bc98abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430596599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.430596599
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2455036741
Short name T333
Test name
Test status
Simulation time 427447900 ps
CPU time 388.15 seconds
Started Jun 13 03:16:45 PM PDT 24
Finished Jun 13 03:23:14 PM PDT 24
Peak memory 263400 kb
Host smart-183de7c4-0c92-43b5-a303-bcb33a7d7b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455036741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.2455036741
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1153239487
Short name T284
Test name
Test status
Simulation time 198709500 ps
CPU time 19.39 seconds
Started Jun 13 03:16:46 PM PDT 24
Finished Jun 13 03:17:06 PM PDT 24
Peak memory 271656 kb
Host smart-dea3aa98-aa18-4445-bc69-5981179a03cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153239487 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1153239487
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.594680050
Short name T1243
Test name
Test status
Simulation time 46182000 ps
CPU time 17.38 seconds
Started Jun 13 03:16:42 PM PDT 24
Finished Jun 13 03:17:00 PM PDT 24
Peak memory 261216 kb
Host smart-19fd1008-bab9-438b-a43f-dde462c7397c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594680050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.594680050
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1610850157
Short name T1166
Test name
Test status
Simulation time 14980100 ps
CPU time 13.38 seconds
Started Jun 13 03:16:43 PM PDT 24
Finished Jun 13 03:16:58 PM PDT 24
Peak memory 260760 kb
Host smart-61d80374-a0ed-4ceb-affb-82bbc553083f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610850157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
1610850157
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1282339280
Short name T1109
Test name
Test status
Simulation time 95947900 ps
CPU time 17.91 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 262176 kb
Host smart-34707d56-9146-486a-959d-5f70cf3800c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282339280 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1282339280
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2131392345
Short name T1203
Test name
Test status
Simulation time 17054700 ps
CPU time 15.51 seconds
Started Jun 13 03:16:43 PM PDT 24
Finished Jun 13 03:16:59 PM PDT 24
Peak memory 252676 kb
Host smart-8a541590-afdf-481d-be40-d7b92eb1149f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131392345 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2131392345
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3992156805
Short name T1145
Test name
Test status
Simulation time 20054700 ps
CPU time 15.85 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:17:01 PM PDT 24
Peak memory 252592 kb
Host smart-2d1df23b-1f69-4513-8bf9-21f36abf1130
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992156805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.3992156805
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3949864779
Short name T1205
Test name
Test status
Simulation time 156081700 ps
CPU time 19.06 seconds
Started Jun 13 03:16:45 PM PDT 24
Finished Jun 13 03:17:05 PM PDT 24
Peak memory 262784 kb
Host smart-d7b10b4d-b6a8-4c1d-b557-95beea66dc74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949864779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
3949864779
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2973167738
Short name T335
Test name
Test status
Simulation time 332388100 ps
CPU time 770.4 seconds
Started Jun 13 03:16:44 PM PDT 24
Finished Jun 13 03:29:36 PM PDT 24
Peak memory 263412 kb
Host smart-28ccb87a-3702-496e-8c78-2342dcb343a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973167738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.2973167738
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2311116353
Short name T1131
Test name
Test status
Simulation time 151556600 ps
CPU time 16.1 seconds
Started Jun 13 03:16:52 PM PDT 24
Finished Jun 13 03:17:09 PM PDT 24
Peak memory 270340 kb
Host smart-7859cf70-9b59-4037-b8bc-9d849d65e424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311116353 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2311116353
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.627755109
Short name T1117
Test name
Test status
Simulation time 48421900 ps
CPU time 17.12 seconds
Started Jun 13 03:16:50 PM PDT 24
Finished Jun 13 03:17:08 PM PDT 24
Peak memory 260760 kb
Host smart-b2400655-9835-4f6c-858a-3d1c234c4193
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627755109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.flash_ctrl_csr_rw.627755109
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.453917120
Short name T1189
Test name
Test status
Simulation time 29282300 ps
CPU time 13.31 seconds
Started Jun 13 03:16:50 PM PDT 24
Finished Jun 13 03:17:05 PM PDT 24
Peak memory 260628 kb
Host smart-c72ee6ea-9d5a-4a86-8763-ab86e258bead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453917120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.453917120
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3633995473
Short name T1181
Test name
Test status
Simulation time 179737400 ps
CPU time 35.4 seconds
Started Jun 13 03:16:54 PM PDT 24
Finished Jun 13 03:17:30 PM PDT 24
Peak memory 263356 kb
Host smart-cf75c889-464c-4ed1-ba64-01f74ba65632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633995473 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3633995473
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4260030874
Short name T1191
Test name
Test status
Simulation time 41461000 ps
CPU time 15.99 seconds
Started Jun 13 03:16:48 PM PDT 24
Finished Jun 13 03:17:05 PM PDT 24
Peak memory 252736 kb
Host smart-89a4111d-8afb-40aa-a53d-b4e0ea941df6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260030874 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.4260030874
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3149169289
Short name T1172
Test name
Test status
Simulation time 12577100 ps
CPU time 15.96 seconds
Started Jun 13 03:16:52 PM PDT 24
Finished Jun 13 03:17:09 PM PDT 24
Peak memory 252688 kb
Host smart-4732ae50-9bc1-4307-90ae-15ed6d78aa6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149169289 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3149169289
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2969124170
Short name T1126
Test name
Test status
Simulation time 49694800 ps
CPU time 15.91 seconds
Started Jun 13 03:16:45 PM PDT 24
Finished Jun 13 03:17:02 PM PDT 24
Peak memory 262692 kb
Host smart-f623e694-1e97-4de9-b02a-c0e0269035ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969124170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2969124170
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3544550500
Short name T218
Test name
Test status
Simulation time 710158200 ps
CPU time 752.21 seconds
Started Jun 13 03:16:52 PM PDT 24
Finished Jun 13 03:29:25 PM PDT 24
Peak memory 263408 kb
Host smart-25422750-df0c-4852-9d8d-6ac98eda3621
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544550500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3544550500
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2757849365
Short name T283
Test name
Test status
Simulation time 237771500 ps
CPU time 17.71 seconds
Started Jun 13 03:16:50 PM PDT 24
Finished Jun 13 03:17:09 PM PDT 24
Peak memory 271616 kb
Host smart-62568caf-c352-49a0-868d-c3eae622f8de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757849365 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2757849365
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1885224695
Short name T1174
Test name
Test status
Simulation time 109468500 ps
CPU time 17.6 seconds
Started Jun 13 03:16:51 PM PDT 24
Finished Jun 13 03:17:09 PM PDT 24
Peak memory 263404 kb
Host smart-02150f37-ac9c-4976-8069-2e352737c072
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885224695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1885224695
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.333681603
Short name T1209
Test name
Test status
Simulation time 17219200 ps
CPU time 13.29 seconds
Started Jun 13 03:16:49 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 260760 kb
Host smart-b6f298a9-7c08-4c42-884c-eb15363ed59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333681603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.333681603
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2633233637
Short name T1178
Test name
Test status
Simulation time 150610400 ps
CPU time 18.47 seconds
Started Jun 13 03:16:52 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 263352 kb
Host smart-55a70951-2b9b-4d07-a265-bf0e7d7e1dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633233637 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2633233637
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3991314782
Short name T1099
Test name
Test status
Simulation time 13022300 ps
CPU time 15.71 seconds
Started Jun 13 03:16:50 PM PDT 24
Finished Jun 13 03:17:07 PM PDT 24
Peak memory 252592 kb
Host smart-fa53e774-f52a-4136-8b05-b1e83dc87182
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991314782 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3991314782
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2285962467
Short name T1214
Test name
Test status
Simulation time 18513900 ps
CPU time 13.36 seconds
Started Jun 13 03:16:52 PM PDT 24
Finished Jun 13 03:17:06 PM PDT 24
Peak memory 252604 kb
Host smart-6fb702f2-2d2f-4a05-a6d7-da024097ad5f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285962467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2285962467
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2609931751
Short name T260
Test name
Test status
Simulation time 66009600 ps
CPU time 16.05 seconds
Started Jun 13 03:16:49 PM PDT 24
Finished Jun 13 03:17:05 PM PDT 24
Peak memory 263396 kb
Host smart-eb3afbbf-62b5-46ef-b0b2-b27055769559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609931751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
2609931751
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3479027190
Short name T1239
Test name
Test status
Simulation time 179017700 ps
CPU time 467.01 seconds
Started Jun 13 03:16:48 PM PDT 24
Finished Jun 13 03:24:36 PM PDT 24
Peak memory 263364 kb
Host smart-44f6de75-4b16-48d8-a396-9f576d009d38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479027190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3479027190
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2877286633
Short name T1147
Test name
Test status
Simulation time 7162036100 ps
CPU time 61.3 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:16:55 PM PDT 24
Peak memory 260876 kb
Host smart-7b68e327-579f-483b-b26b-f28fe325d59d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877286633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2877286633
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3835666545
Short name T253
Test name
Test status
Simulation time 2235318900 ps
CPU time 77.42 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260876 kb
Host smart-489bddf5-2a00-44ee-b726-1844febea465
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835666545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.3835666545
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2343530539
Short name T1245
Test name
Test status
Simulation time 191777900 ps
CPU time 46.02 seconds
Started Jun 13 03:15:50 PM PDT 24
Finished Jun 13 03:16:38 PM PDT 24
Peak memory 261036 kb
Host smart-a21a818b-d150-4b75-acda-3a87ea318a1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343530539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.2343530539
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2880409568
Short name T1198
Test name
Test status
Simulation time 107693500 ps
CPU time 16.95 seconds
Started Jun 13 03:15:54 PM PDT 24
Finished Jun 13 03:16:12 PM PDT 24
Peak memory 270200 kb
Host smart-4ac2487a-e365-48ed-b188-a46ef5aa6106
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880409568 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2880409568
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1791018894
Short name T1185
Test name
Test status
Simulation time 213227500 ps
CPU time 17.97 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:16:11 PM PDT 24
Peak memory 263412 kb
Host smart-66189af2-3505-407a-a28a-f80718a9508c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791018894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.1791018894
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.341178653
Short name T1220
Test name
Test status
Simulation time 23769600 ps
CPU time 13.13 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:16:07 PM PDT 24
Peak memory 260832 kb
Host smart-bbf14dce-1d8e-4a75-a2f7-8dbbf881f758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341178653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.341178653
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1998499711
Short name T224
Test name
Test status
Simulation time 71452400 ps
CPU time 13.53 seconds
Started Jun 13 03:15:50 PM PDT 24
Finished Jun 13 03:16:05 PM PDT 24
Peak memory 262296 kb
Host smart-dbac3e07-36c5-47a7-9e82-ba64088cc27e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998499711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1998499711
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.571491226
Short name T1151
Test name
Test status
Simulation time 25073700 ps
CPU time 13.47 seconds
Started Jun 13 03:15:51 PM PDT 24
Finished Jun 13 03:16:06 PM PDT 24
Peak memory 260872 kb
Host smart-f51f4b5b-4f02-48d1-b6d9-7fb1e54b0da6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571491226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.571491226
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1361138479
Short name T1233
Test name
Test status
Simulation time 355967700 ps
CPU time 34.17 seconds
Started Jun 13 03:15:53 PM PDT 24
Finished Jun 13 03:16:28 PM PDT 24
Peak memory 263396 kb
Host smart-89b80584-5f59-42e3-927c-d6cb5cc9fdf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361138479 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1361138479
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3766954771
Short name T1127
Test name
Test status
Simulation time 11834800 ps
CPU time 15.62 seconds
Started Jun 13 03:15:51 PM PDT 24
Finished Jun 13 03:16:08 PM PDT 24
Peak memory 252692 kb
Host smart-7e9cdbe6-0551-498b-9890-3d4d4b9c20a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766954771 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3766954771
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2026258481
Short name T1238
Test name
Test status
Simulation time 47798500 ps
CPU time 15.72 seconds
Started Jun 13 03:15:50 PM PDT 24
Finished Jun 13 03:16:07 PM PDT 24
Peak memory 252688 kb
Host smart-57a1db3d-0462-427a-ab7d-2e569214b2a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026258481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2026258481
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.851186565
Short name T261
Test name
Test status
Simulation time 179234900 ps
CPU time 19.72 seconds
Started Jun 13 03:15:46 PM PDT 24
Finished Jun 13 03:16:07 PM PDT 24
Peak memory 263388 kb
Host smart-59486f07-905d-4fb7-9898-4c2cf86964b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851186565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.851186565
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2902427450
Short name T99
Test name
Test status
Simulation time 985425800 ps
CPU time 765.05 seconds
Started Jun 13 03:15:51 PM PDT 24
Finished Jun 13 03:28:38 PM PDT 24
Peak memory 263412 kb
Host smart-333c1b27-7a76-404f-907f-c56fd1a54628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902427450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2902427450
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4267587871
Short name T1232
Test name
Test status
Simulation time 53886300 ps
CPU time 13.68 seconds
Started Jun 13 03:16:48 PM PDT 24
Finished Jun 13 03:17:02 PM PDT 24
Peak memory 260892 kb
Host smart-a5ace0d7-6053-447d-9201-a9e8df1571bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267587871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
4267587871
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2165742651
Short name T1123
Test name
Test status
Simulation time 114562400 ps
CPU time 13.29 seconds
Started Jun 13 03:16:49 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 260820 kb
Host smart-8a57aa03-013c-41f9-bcc6-2c7decde1d4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165742651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2165742651
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3301383094
Short name T1175
Test name
Test status
Simulation time 28529900 ps
CPU time 13.32 seconds
Started Jun 13 03:16:49 PM PDT 24
Finished Jun 13 03:17:02 PM PDT 24
Peak memory 260816 kb
Host smart-6b46817a-de6d-4ec9-a117-26f526072753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301383094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3301383094
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1420307503
Short name T1118
Test name
Test status
Simulation time 46927300 ps
CPU time 13.79 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260884 kb
Host smart-136c5c80-31f2-44c1-b6ba-f550bf0e2b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420307503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1420307503
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2284698311
Short name T1108
Test name
Test status
Simulation time 15783900 ps
CPU time 13.75 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260812 kb
Host smart-6fa85be8-064e-4815-9783-9873b7466de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284698311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2284698311
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2074081671
Short name T303
Test name
Test status
Simulation time 30766300 ps
CPU time 13.34 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260772 kb
Host smart-a7fa6a71-6d77-4da1-b31e-b4f46f6b39fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074081671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2074081671
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.932734416
Short name T298
Test name
Test status
Simulation time 14794400 ps
CPU time 13.3 seconds
Started Jun 13 03:16:55 PM PDT 24
Finished Jun 13 03:17:08 PM PDT 24
Peak memory 260828 kb
Host smart-83372032-5489-4461-8561-5dce021c36fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932734416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.932734416
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.72064163
Short name T1176
Test name
Test status
Simulation time 45194500 ps
CPU time 13.3 seconds
Started Jun 13 03:16:59 PM PDT 24
Finished Jun 13 03:17:13 PM PDT 24
Peak memory 260768 kb
Host smart-e785163b-4036-4aec-87d5-ff9f99912543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72064163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.72064163
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3912894297
Short name T1218
Test name
Test status
Simulation time 60653900 ps
CPU time 13.3 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:12 PM PDT 24
Peak memory 260748 kb
Host smart-d554da6b-b807-4483-b508-94992a0c2da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912894297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
3912894297
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.941791213
Short name T1154
Test name
Test status
Simulation time 881414600 ps
CPU time 54.03 seconds
Started Jun 13 03:15:58 PM PDT 24
Finished Jun 13 03:16:53 PM PDT 24
Peak memory 260880 kb
Host smart-86817873-7d8a-4c87-b52c-32f93fad2a6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941791213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.941791213
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2252622445
Short name T1146
Test name
Test status
Simulation time 330887400 ps
CPU time 39.88 seconds
Started Jun 13 03:15:55 PM PDT 24
Finished Jun 13 03:16:35 PM PDT 24
Peak memory 260952 kb
Host smart-4db4493a-4d0f-4eb6-9706-00fe54dc4efb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252622445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.2252622445
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3555436866
Short name T259
Test name
Test status
Simulation time 104388700 ps
CPU time 25.86 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:24 PM PDT 24
Peak memory 260884 kb
Host smart-8c24456f-d445-4c1d-9030-206a1b7cb037
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555436866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3555436866
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2877012901
Short name T1225
Test name
Test status
Simulation time 240394400 ps
CPU time 20 seconds
Started Jun 13 03:16:00 PM PDT 24
Finished Jun 13 03:16:21 PM PDT 24
Peak memory 271624 kb
Host smart-68d30a84-d117-452f-9f66-679a30eefcb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877012901 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.2877012901
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1104817302
Short name T1223
Test name
Test status
Simulation time 67739200 ps
CPU time 16.46 seconds
Started Jun 13 03:15:56 PM PDT 24
Finished Jun 13 03:16:13 PM PDT 24
Peak memory 263312 kb
Host smart-71f5c13e-cd32-4b82-81c0-59bc2d725c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104817302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1104817302
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2176282525
Short name T1219
Test name
Test status
Simulation time 28367800 ps
CPU time 13.22 seconds
Started Jun 13 03:15:51 PM PDT 24
Finished Jun 13 03:16:05 PM PDT 24
Peak memory 260872 kb
Host smart-edae7edc-1824-44c1-84d6-107623b67551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176282525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
176282525
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3983647154
Short name T227
Test name
Test status
Simulation time 20324500 ps
CPU time 13.56 seconds
Started Jun 13 03:15:56 PM PDT 24
Finished Jun 13 03:16:10 PM PDT 24
Peak memory 262424 kb
Host smart-969932d8-47dd-42ea-a098-3640e953ea14
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983647154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3983647154
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3225346899
Short name T1202
Test name
Test status
Simulation time 17975400 ps
CPU time 13.44 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:16:07 PM PDT 24
Peak memory 260868 kb
Host smart-a433ebc9-245c-4bcb-ac5d-d54fe46124c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225346899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.3225346899
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.971561135
Short name T1122
Test name
Test status
Simulation time 167614400 ps
CPU time 29.55 seconds
Started Jun 13 03:15:55 PM PDT 24
Finished Jun 13 03:16:25 PM PDT 24
Peak memory 261004 kb
Host smart-10c1fd1b-3c12-47be-b337-7da6325c806a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971561135 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.971561135
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3502349278
Short name T1192
Test name
Test status
Simulation time 17359800 ps
CPU time 13.2 seconds
Started Jun 13 03:15:50 PM PDT 24
Finished Jun 13 03:16:04 PM PDT 24
Peak memory 252692 kb
Host smart-5d02ea36-69dd-4f58-acd0-693c5034657c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502349278 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3502349278
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2189130818
Short name T1102
Test name
Test status
Simulation time 40403300 ps
CPU time 13.12 seconds
Started Jun 13 03:15:52 PM PDT 24
Finished Jun 13 03:16:07 PM PDT 24
Peak memory 252576 kb
Host smart-e3bf9c12-fb85-4610-a3c6-0801485e1f0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189130818 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2189130818
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3543633259
Short name T257
Test name
Test status
Simulation time 14837300 ps
CPU time 13.25 seconds
Started Jun 13 03:16:59 PM PDT 24
Finished Jun 13 03:17:12 PM PDT 24
Peak memory 260620 kb
Host smart-265561d3-c4d9-48bd-acf5-8f17cadbd1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543633259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3543633259
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3467291178
Short name T1246
Test name
Test status
Simulation time 15898000 ps
CPU time 13.5 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260820 kb
Host smart-f3b076c3-48b4-4a28-ada0-caa794c2dc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467291178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3467291178
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.55110864
Short name T1149
Test name
Test status
Simulation time 25323500 ps
CPU time 13.39 seconds
Started Jun 13 03:16:54 PM PDT 24
Finished Jun 13 03:17:07 PM PDT 24
Peak memory 260712 kb
Host smart-96adc6a3-e49d-46bd-9d21-dcb0f1c880c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55110864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.55110864
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.503321719
Short name T302
Test name
Test status
Simulation time 133882000 ps
CPU time 13.84 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:10 PM PDT 24
Peak memory 260752 kb
Host smart-e1d49c0b-c5ea-4750-845c-2c2c913e26d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503321719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.503321719
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.773708588
Short name T1236
Test name
Test status
Simulation time 50174500 ps
CPU time 13.37 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260820 kb
Host smart-6e46ae22-36e7-4c74-b3bf-48a77948036d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773708588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.773708588
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.751035060
Short name T1183
Test name
Test status
Simulation time 14480200 ps
CPU time 13.2 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260748 kb
Host smart-668708aa-d3f9-4a74-92ee-e9079892f090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751035060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.751035060
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.226829455
Short name T1188
Test name
Test status
Simulation time 18336600 ps
CPU time 13.38 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:10 PM PDT 24
Peak memory 260804 kb
Host smart-2b9645cf-354b-47c8-984b-4e4accf88f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226829455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.226829455
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2018324820
Short name T1208
Test name
Test status
Simulation time 55970600 ps
CPU time 13.32 seconds
Started Jun 13 03:16:55 PM PDT 24
Finished Jun 13 03:17:09 PM PDT 24
Peak memory 260836 kb
Host smart-3321c1e2-9290-441c-aa81-b881c3d9b36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018324820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2018324820
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3777953708
Short name T1155
Test name
Test status
Simulation time 17849200 ps
CPU time 13.38 seconds
Started Jun 13 03:16:57 PM PDT 24
Finished Jun 13 03:17:12 PM PDT 24
Peak memory 260748 kb
Host smart-c60483d5-1b27-4350-a708-2abe95224ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777953708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
3777953708
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1296451937
Short name T1107
Test name
Test status
Simulation time 42560700 ps
CPU time 13.31 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260828 kb
Host smart-01e65294-d1fe-478d-af5b-ee7b0f78c5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296451937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1296451937
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.241697045
Short name T1244
Test name
Test status
Simulation time 5088211500 ps
CPU time 67.76 seconds
Started Jun 13 03:15:54 PM PDT 24
Finished Jun 13 03:17:03 PM PDT 24
Peak memory 260868 kb
Host smart-5999f001-49c9-40c7-9690-c008faa67514
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241697045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.241697045
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1644680692
Short name T1194
Test name
Test status
Simulation time 1587980400 ps
CPU time 46.82 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:45 PM PDT 24
Peak memory 260884 kb
Host smart-c6015bd7-1b21-4b45-b5fa-8e3fae5c37d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644680692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.1644680692
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3651453002
Short name T1152
Test name
Test status
Simulation time 30408800 ps
CPU time 30.6 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:28 PM PDT 24
Peak memory 260892 kb
Host smart-1ee7d048-3e8d-4951-af05-cb0c83b8b122
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651453002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3651453002
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3727765347
Short name T1195
Test name
Test status
Simulation time 26089900 ps
CPU time 18.65 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:24 PM PDT 24
Peak memory 276968 kb
Host smart-370063a0-1e98-49c4-98e1-40839a875d77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727765347 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3727765347
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4095639966
Short name T1113
Test name
Test status
Simulation time 75147500 ps
CPU time 14.23 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:13 PM PDT 24
Peak memory 260876 kb
Host smart-1b4c8def-c099-4670-af86-f2f9f87f85df
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095639966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.4095639966
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1266205704
Short name T1179
Test name
Test status
Simulation time 48070800 ps
CPU time 13.29 seconds
Started Jun 13 03:15:56 PM PDT 24
Finished Jun 13 03:16:10 PM PDT 24
Peak memory 260884 kb
Host smart-4c9409c7-f8c8-408d-818d-41654a68d3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266205704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
266205704
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1208141626
Short name T226
Test name
Test status
Simulation time 15684700 ps
CPU time 13.58 seconds
Started Jun 13 03:15:58 PM PDT 24
Finished Jun 13 03:16:12 PM PDT 24
Peak memory 261868 kb
Host smart-4014ff66-ef41-487a-a2bf-fc15bf7ead4b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208141626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1208141626
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.768201266
Short name T1136
Test name
Test status
Simulation time 14455300 ps
CPU time 13.43 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:12 PM PDT 24
Peak memory 260864 kb
Host smart-b66d079b-168a-446c-83d8-8bc73e77301a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768201266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.768201266
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.898673650
Short name T282
Test name
Test status
Simulation time 362634600 ps
CPU time 30.3 seconds
Started Jun 13 03:15:58 PM PDT 24
Finished Jun 13 03:16:29 PM PDT 24
Peak memory 262916 kb
Host smart-b5d058d6-9af9-41e3-bb7c-8ed0e9373b5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898673650 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.898673650
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3018271355
Short name T1197
Test name
Test status
Simulation time 30699100 ps
CPU time 16.13 seconds
Started Jun 13 03:15:54 PM PDT 24
Finished Jun 13 03:16:11 PM PDT 24
Peak memory 252628 kb
Host smart-6e6f9e71-6f3f-4dee-bb7e-12919e012f64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018271355 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3018271355
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.158581411
Short name T1187
Test name
Test status
Simulation time 14309900 ps
CPU time 15.52 seconds
Started Jun 13 03:15:57 PM PDT 24
Finished Jun 13 03:16:12 PM PDT 24
Peak memory 252736 kb
Host smart-a6bb703c-076c-4c7d-a59c-9390883ffd16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158581411 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.158581411
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.715609393
Short name T1237
Test name
Test status
Simulation time 108235900 ps
CPU time 17.13 seconds
Started Jun 13 03:16:00 PM PDT 24
Finished Jun 13 03:16:18 PM PDT 24
Peak memory 263376 kb
Host smart-15aac8a2-e471-4600-8ab2-35566c1d9493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715609393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.715609393
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2380591327
Short name T332
Test name
Test status
Simulation time 192245100 ps
CPU time 455.01 seconds
Started Jun 13 03:15:58 PM PDT 24
Finished Jun 13 03:23:34 PM PDT 24
Peak memory 263412 kb
Host smart-bd2f85e0-26de-4f72-83a2-5179bce7045a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380591327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2380591327
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1025408288
Short name T1201
Test name
Test status
Simulation time 14567700 ps
CPU time 13.62 seconds
Started Jun 13 03:16:56 PM PDT 24
Finished Jun 13 03:17:11 PM PDT 24
Peak memory 260708 kb
Host smart-d4e0e9ba-933e-43b7-8ae6-c7d898fc4ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025408288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1025408288
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.929118107
Short name T1135
Test name
Test status
Simulation time 81506700 ps
CPU time 13.39 seconds
Started Jun 13 03:17:02 PM PDT 24
Finished Jun 13 03:17:16 PM PDT 24
Peak memory 260724 kb
Host smart-a7656172-6756-4e70-8c99-e14c85d67b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929118107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.929118107
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3818729748
Short name T1224
Test name
Test status
Simulation time 17905900 ps
CPU time 13.5 seconds
Started Jun 13 03:17:03 PM PDT 24
Finished Jun 13 03:17:17 PM PDT 24
Peak memory 260828 kb
Host smart-74572740-87a6-48a7-b9cf-1143b2978c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818729748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3818729748
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2450492346
Short name T1143
Test name
Test status
Simulation time 19406300 ps
CPU time 13.48 seconds
Started Jun 13 03:17:02 PM PDT 24
Finished Jun 13 03:17:17 PM PDT 24
Peak memory 260820 kb
Host smart-f1fa2730-8fc6-4689-9811-3c2ee4227ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450492346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
2450492346
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4022820018
Short name T1106
Test name
Test status
Simulation time 25884700 ps
CPU time 13.35 seconds
Started Jun 13 03:17:02 PM PDT 24
Finished Jun 13 03:17:17 PM PDT 24
Peak memory 260812 kb
Host smart-caa2c2ef-1c2c-45d7-90ff-a06f1fd86e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022820018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
4022820018
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4101038816
Short name T1129
Test name
Test status
Simulation time 55486600 ps
CPU time 13.32 seconds
Started Jun 13 03:17:01 PM PDT 24
Finished Jun 13 03:17:16 PM PDT 24
Peak memory 260760 kb
Host smart-e0a71318-296b-498a-a082-277f1c0f3979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101038816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
4101038816
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1149561660
Short name T1137
Test name
Test status
Simulation time 25048500 ps
CPU time 13.41 seconds
Started Jun 13 03:17:00 PM PDT 24
Finished Jun 13 03:17:14 PM PDT 24
Peak memory 260828 kb
Host smart-3cdaa856-687d-46a7-bc66-54cea2d71f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149561660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
1149561660
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2827466113
Short name T1134
Test name
Test status
Simulation time 44529100 ps
CPU time 13.48 seconds
Started Jun 13 03:17:02 PM PDT 24
Finished Jun 13 03:17:17 PM PDT 24
Peak memory 260776 kb
Host smart-e1d81152-788e-4927-a409-fd23609e97d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827466113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2827466113
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3140917540
Short name T1148
Test name
Test status
Simulation time 54291300 ps
CPU time 13.58 seconds
Started Jun 13 03:17:04 PM PDT 24
Finished Jun 13 03:17:19 PM PDT 24
Peak memory 260832 kb
Host smart-e40b7cd5-0fd5-4404-ab9a-5223eb9d6b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140917540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3140917540
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.269209321
Short name T1228
Test name
Test status
Simulation time 230860800 ps
CPU time 17.85 seconds
Started Jun 13 03:16:05 PM PDT 24
Finished Jun 13 03:16:23 PM PDT 24
Peak memory 269956 kb
Host smart-888cd52e-c50e-401c-840b-7b01204692e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269209321 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.269209321
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1578189750
Short name T1124
Test name
Test status
Simulation time 37779900 ps
CPU time 16.25 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:21 PM PDT 24
Peak memory 260808 kb
Host smart-92f93705-b4cd-4bdb-99d6-7c79a0e2872b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578189750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1578189750
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.524083246
Short name T1160
Test name
Test status
Simulation time 15396000 ps
CPU time 13.12 seconds
Started Jun 13 03:16:05 PM PDT 24
Finished Jun 13 03:16:19 PM PDT 24
Peak memory 260740 kb
Host smart-ed043008-25c7-40bb-9455-ff3b41a944ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524083246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.524083246
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3224510235
Short name T285
Test name
Test status
Simulation time 846968600 ps
CPU time 36.12 seconds
Started Jun 13 03:16:03 PM PDT 24
Finished Jun 13 03:16:40 PM PDT 24
Peak memory 263420 kb
Host smart-0b6b14a5-d9dc-425c-ad40-bbb7dfb7f309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224510235 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3224510235
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.301473415
Short name T1222
Test name
Test status
Simulation time 28827200 ps
CPU time 13.61 seconds
Started Jun 13 03:16:03 PM PDT 24
Finished Jun 13 03:16:18 PM PDT 24
Peak memory 252684 kb
Host smart-8c1ec208-c906-408b-84ea-86129d2b6b62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301473415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.301473415
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1936886471
Short name T1212
Test name
Test status
Simulation time 27128400 ps
CPU time 15.69 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:21 PM PDT 24
Peak memory 252664 kb
Host smart-1aee3e37-8c12-4baa-9711-97e53649ac03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936886471 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1936886471
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2126495962
Short name T328
Test name
Test status
Simulation time 62774700 ps
CPU time 18.72 seconds
Started Jun 13 03:16:01 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 263436 kb
Host smart-33f1ba09-acfd-4aef-b646-55458e794634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126495962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
126495962
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4144225900
Short name T1200
Test name
Test status
Simulation time 480605300 ps
CPU time 450.37 seconds
Started Jun 13 03:16:00 PM PDT 24
Finished Jun 13 03:23:31 PM PDT 24
Peak memory 263412 kb
Host smart-7c10eb2e-c7df-439b-977b-7a8448e4e9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144225900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.4144225900
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2003827397
Short name T1173
Test name
Test status
Simulation time 27857300 ps
CPU time 17.38 seconds
Started Jun 13 03:16:06 PM PDT 24
Finished Jun 13 03:16:24 PM PDT 24
Peak memory 271648 kb
Host smart-03ae995e-8857-452f-a23e-735117e56040
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003827397 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.2003827397
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3151104150
Short name T281
Test name
Test status
Simulation time 100230200 ps
CPU time 17.68 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:23 PM PDT 24
Peak memory 263384 kb
Host smart-cb555426-a932-4696-ad33-336b1cb85093
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151104150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3151104150
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3697008576
Short name T1247
Test name
Test status
Simulation time 50310700 ps
CPU time 13.36 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:18 PM PDT 24
Peak memory 260628 kb
Host smart-d0afaa6a-5169-4b7b-be9a-078e47f13eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697008576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
697008576
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3801622482
Short name T63
Test name
Test status
Simulation time 679234900 ps
CPU time 18.17 seconds
Started Jun 13 03:16:02 PM PDT 24
Finished Jun 13 03:16:21 PM PDT 24
Peak memory 260780 kb
Host smart-59b2e5c4-c0e8-4d7b-9bf4-a4c7a7693b37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801622482 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3801622482
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1143299707
Short name T1165
Test name
Test status
Simulation time 177007800 ps
CPU time 16.15 seconds
Started Jun 13 03:16:03 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 252620 kb
Host smart-395c06c0-de37-4f41-908a-7237daf2be62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143299707 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1143299707
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.845111038
Short name T1242
Test name
Test status
Simulation time 12425800 ps
CPU time 13.4 seconds
Started Jun 13 03:16:05 PM PDT 24
Finished Jun 13 03:16:19 PM PDT 24
Peak memory 252636 kb
Host smart-b1fc1bbf-5e7d-40cb-bc4f-0552b668d412
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845111038 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.845111038
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3142420517
Short name T254
Test name
Test status
Simulation time 66621400 ps
CPU time 15.31 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 263432 kb
Host smart-8d290b17-507f-43bf-91b5-ce761cca9209
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142420517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3
142420517
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3253995823
Short name T331
Test name
Test status
Simulation time 790035100 ps
CPU time 767.88 seconds
Started Jun 13 03:16:03 PM PDT 24
Finished Jun 13 03:28:51 PM PDT 24
Peak memory 263432 kb
Host smart-af9bd4f1-2c33-4272-a056-f89d52f10468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253995823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3253995823
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1479057795
Short name T1164
Test name
Test status
Simulation time 303516400 ps
CPU time 15.69 seconds
Started Jun 13 03:16:10 PM PDT 24
Finished Jun 13 03:16:26 PM PDT 24
Peak memory 270384 kb
Host smart-2e38baf9-81a2-4019-9f63-4c5488c1937b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479057795 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1479057795
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.383468604
Short name T1184
Test name
Test status
Simulation time 272847800 ps
CPU time 15.16 seconds
Started Jun 13 03:16:07 PM PDT 24
Finished Jun 13 03:16:23 PM PDT 24
Peak memory 260876 kb
Host smart-db235522-c52d-4720-86b9-17e59c52697f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383468604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.383468604
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1508462981
Short name T1128
Test name
Test status
Simulation time 48560500 ps
CPU time 13.32 seconds
Started Jun 13 03:16:02 PM PDT 24
Finished Jun 13 03:16:16 PM PDT 24
Peak memory 260764 kb
Host smart-2f04b499-c6d1-43d9-8743-edc9d9028a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508462981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1
508462981
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4030613911
Short name T1119
Test name
Test status
Simulation time 314913800 ps
CPU time 35.16 seconds
Started Jun 13 03:16:09 PM PDT 24
Finished Jun 13 03:16:45 PM PDT 24
Peak memory 262240 kb
Host smart-1dda6b9a-ecc5-43fe-9077-f1ad3cdb0e27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030613911 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.4030613911
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.484244161
Short name T1241
Test name
Test status
Simulation time 14881200 ps
CPU time 15.6 seconds
Started Jun 13 03:16:01 PM PDT 24
Finished Jun 13 03:16:17 PM PDT 24
Peak memory 252444 kb
Host smart-f6623f6b-630c-4656-b428-d84417fb9139
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484244161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.484244161
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.575918310
Short name T1210
Test name
Test status
Simulation time 21929900 ps
CPU time 15.86 seconds
Started Jun 13 03:16:05 PM PDT 24
Finished Jun 13 03:16:22 PM PDT 24
Peak memory 252756 kb
Host smart-edaacd66-e95b-410b-910e-833b82f9249c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575918310 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.575918310
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1914570111
Short name T1132
Test name
Test status
Simulation time 277353000 ps
CPU time 15.88 seconds
Started Jun 13 03:16:04 PM PDT 24
Finished Jun 13 03:16:20 PM PDT 24
Peak memory 263432 kb
Host smart-43e4af99-e920-4917-a8bb-53e6e5302a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914570111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
914570111
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2905218796
Short name T252
Test name
Test status
Simulation time 1352959800 ps
CPU time 461.57 seconds
Started Jun 13 03:16:02 PM PDT 24
Finished Jun 13 03:23:44 PM PDT 24
Peak memory 263408 kb
Host smart-d265428d-1c2d-41aa-aaf6-17dd1f40eb50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905218796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2905218796
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.682919016
Short name T64
Test name
Test status
Simulation time 108059000 ps
CPU time 17.21 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:32 PM PDT 24
Peak memory 263420 kb
Host smart-ce2dfb9b-e4bd-4357-a6fa-17920bfb1561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682919016 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.682919016
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2559036192
Short name T278
Test name
Test status
Simulation time 75838700 ps
CPU time 17.68 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:32 PM PDT 24
Peak memory 263416 kb
Host smart-ae379a2d-ec75-4794-9ec2-18b5164cc7d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559036192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2559036192
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.587964142
Short name T1120
Test name
Test status
Simulation time 42415900 ps
CPU time 13.44 seconds
Started Jun 13 03:16:15 PM PDT 24
Finished Jun 13 03:16:29 PM PDT 24
Peak memory 260888 kb
Host smart-bedd0fd7-435b-4168-b6db-4f965b1bd83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587964142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.587964142
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3127916794
Short name T1150
Test name
Test status
Simulation time 231307200 ps
CPU time 34.64 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:49 PM PDT 24
Peak memory 263148 kb
Host smart-2059c88d-b0ae-42d1-9bfb-117b9c956d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127916794 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3127916794
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1605572284
Short name T1171
Test name
Test status
Simulation time 43866000 ps
CPU time 13.23 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:29 PM PDT 24
Peak memory 252696 kb
Host smart-5855570b-936e-42f9-9bfb-69075971ef02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605572284 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1605572284
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.886596102
Short name T1168
Test name
Test status
Simulation time 13703200 ps
CPU time 15.7 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:31 PM PDT 24
Peak memory 252628 kb
Host smart-3e858845-5ebb-43b6-8f65-99e54bfbf4b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886596102 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.886596102
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3934036377
Short name T220
Test name
Test status
Simulation time 67420500 ps
CPU time 15.84 seconds
Started Jun 13 03:16:08 PM PDT 24
Finished Jun 13 03:16:24 PM PDT 24
Peak memory 263428 kb
Host smart-fc3f5b50-2b3e-461c-9e63-fa7c5fe6b41c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934036377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
934036377
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.78673711
Short name T1182
Test name
Test status
Simulation time 56397100 ps
CPU time 17.16 seconds
Started Jun 13 03:16:15 PM PDT 24
Finished Jun 13 03:16:33 PM PDT 24
Peak memory 263404 kb
Host smart-816c79f7-f2ad-4aa7-9aa8-76b8c2baceab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78673711 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.78673711
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.899832600
Short name T1125
Test name
Test status
Simulation time 287326100 ps
CPU time 16.31 seconds
Started Jun 13 03:16:17 PM PDT 24
Finished Jun 13 03:16:34 PM PDT 24
Peak memory 260936 kb
Host smart-58a5b6cf-ec94-406f-94a6-7720e0a568f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899832600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.899832600
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2536206332
Short name T258
Test name
Test status
Simulation time 23297700 ps
CPU time 13.2 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:29 PM PDT 24
Peak memory 260832 kb
Host smart-ccad8700-ca84-4f4b-ad2d-c11432bf7989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536206332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
536206332
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2273459164
Short name T1104
Test name
Test status
Simulation time 675318000 ps
CPU time 21.14 seconds
Started Jun 13 03:16:14 PM PDT 24
Finished Jun 13 03:16:35 PM PDT 24
Peak memory 263320 kb
Host smart-1537b982-7b39-4bad-aacf-b512c2f7ea2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273459164 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2273459164
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2267242422
Short name T1215
Test name
Test status
Simulation time 18322800 ps
CPU time 16.33 seconds
Started Jun 13 03:16:17 PM PDT 24
Finished Jun 13 03:16:34 PM PDT 24
Peak memory 252620 kb
Host smart-c0af7008-426f-4d34-b0a4-893942bdd0a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267242422 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2267242422
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2787265773
Short name T1206
Test name
Test status
Simulation time 14467100 ps
CPU time 16.32 seconds
Started Jun 13 03:16:16 PM PDT 24
Finished Jun 13 03:16:33 PM PDT 24
Peak memory 252712 kb
Host smart-6dc727c5-6408-4360-ad62-fc7aab14663d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787265773 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2787265773
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1905322875
Short name T1139
Test name
Test status
Simulation time 156058500 ps
CPU time 16.8 seconds
Started Jun 13 03:16:15 PM PDT 24
Finished Jun 13 03:16:33 PM PDT 24
Peak memory 263444 kb
Host smart-1121e588-8190-4b1f-aaac-ac4966402666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905322875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
905322875
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3542838473
Short name T265
Test name
Test status
Simulation time 3153426000 ps
CPU time 459.11 seconds
Started Jun 13 03:16:13 PM PDT 24
Finished Jun 13 03:23:52 PM PDT 24
Peak memory 263416 kb
Host smart-efc51279-7007-4cc9-ab6c-63fcd9b3c9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542838473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3542838473
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3562986767
Short name T339
Test name
Test status
Simulation time 131193300 ps
CPU time 13.76 seconds
Started Jun 13 03:17:29 PM PDT 24
Finished Jun 13 03:17:44 PM PDT 24
Peak memory 262012 kb
Host smart-7f6e96e0-bd84-4693-b734-ba33a7c8e17e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562986767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3562986767
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2477069714
Short name T591
Test name
Test status
Simulation time 19537100 ps
CPU time 13.57 seconds
Started Jun 13 03:17:26 PM PDT 24
Finished Jun 13 03:17:40 PM PDT 24
Peak memory 275200 kb
Host smart-f6b473b1-53da-416c-b0d5-7b05c539e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477069714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2477069714
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3386357802
Short name T349
Test name
Test status
Simulation time 33174500 ps
CPU time 21.56 seconds
Started Jun 13 03:17:20 PM PDT 24
Finished Jun 13 03:17:43 PM PDT 24
Peak memory 274124 kb
Host smart-5d4229b2-4698-44b6-a151-7a4f588d3fb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386357802 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3386357802
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3061708092
Short name T812
Test name
Test status
Simulation time 2160259000 ps
CPU time 24.22 seconds
Started Jun 13 03:17:06 PM PDT 24
Finished Jun 13 03:17:31 PM PDT 24
Peak memory 262896 kb
Host smart-d462647d-5177-436e-8a54-d7f21aed1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061708092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3061708092
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.989310
Short name T886
Test name
Test status
Simulation time 1142616700 ps
CPU time 35.92 seconds
Started Jun 13 03:17:32 PM PDT 24
Finished Jun 13 03:18:08 PM PDT 24
Peak memory 263424 kb
Host smart-b794ec49-6067-4fd5-a461-3b6513d42f43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_fs_sup.989310
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.1189412062
Short name T115
Test name
Test status
Simulation time 109980999100 ps
CPU time 2687.83 seconds
Started Jun 13 03:17:08 PM PDT 24
Finished Jun 13 04:01:57 PM PDT 24
Peak memory 264060 kb
Host smart-230ad79a-44eb-4cd6-a2a0-9f2666358672
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189412062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.1189412062
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2507876122
Short name T726
Test name
Test status
Simulation time 241592582600 ps
CPU time 2593.7 seconds
Started Jun 13 03:17:05 PM PDT 24
Finished Jun 13 04:00:19 PM PDT 24
Peak memory 264304 kb
Host smart-8cf11838-098e-4e57-a7cb-5e83ede9c426
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507876122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2507876122
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.75949497
Short name T992
Test name
Test status
Simulation time 59084200 ps
CPU time 102.58 seconds
Started Jun 13 03:17:04 PM PDT 24
Finished Jun 13 03:18:47 PM PDT 24
Peak memory 265656 kb
Host smart-d6ce0880-f4db-4371-b815-69ed72c63569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75949497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.75949497
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1203223590
Short name T327
Test name
Test status
Simulation time 25733000 ps
CPU time 13.5 seconds
Started Jun 13 03:17:28 PM PDT 24
Finished Jun 13 03:17:42 PM PDT 24
Peak memory 259880 kb
Host smart-6b9db541-55a5-468f-b6a4-7b66e2f1e555
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203223590 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1203223590
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.356818809
Short name T816
Test name
Test status
Simulation time 209106438000 ps
CPU time 2145.08 seconds
Started Jun 13 03:17:09 PM PDT 24
Finished Jun 13 03:52:55 PM PDT 24
Peak memory 265356 kb
Host smart-0e762ba8-5a1e-46a1-b0ce-fcce4712bd0f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356818809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.356818809
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.2971600859
Short name T102
Test name
Test status
Simulation time 350231276100 ps
CPU time 872.19 seconds
Started Jun 13 03:17:10 PM PDT 24
Finished Jun 13 03:31:43 PM PDT 24
Peak memory 265492 kb
Host smart-67cc4066-950b-4f04-baa3-c057af6883fc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971600859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.2971600859
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2239173598
Short name T442
Test name
Test status
Simulation time 7290998400 ps
CPU time 137.83 seconds
Started Jun 13 03:17:07 PM PDT 24
Finished Jun 13 03:19:26 PM PDT 24
Peak memory 263396 kb
Host smart-196f73ad-98ef-48d9-8cf4-64497c884531
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239173598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2239173598
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.868066809
Short name T240
Test name
Test status
Simulation time 15219124300 ps
CPU time 639.47 seconds
Started Jun 13 03:17:12 PM PDT 24
Finished Jun 13 03:27:52 PM PDT 24
Peak memory 335160 kb
Host smart-f17d1595-a786-4b1a-9a7a-f22f4ec0f74d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868066809 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_integrity.868066809
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2513625444
Short name T570
Test name
Test status
Simulation time 29889215900 ps
CPU time 139.05 seconds
Started Jun 13 03:17:17 PM PDT 24
Finished Jun 13 03:19:37 PM PDT 24
Peak memory 292996 kb
Host smart-f1031c5b-c170-4f5b-b443-39a1ad1b636f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513625444 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2513625444
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.4067269591
Short name T1085
Test name
Test status
Simulation time 2410085800 ps
CPU time 74.43 seconds
Started Jun 13 03:17:21 PM PDT 24
Finished Jun 13 03:18:37 PM PDT 24
Peak memory 265536 kb
Host smart-40eb9188-740a-401c-bb11-dd3969e77b8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067269591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.4067269591
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1824559561
Short name T951
Test name
Test status
Simulation time 174292307700 ps
CPU time 284.38 seconds
Started Jun 13 03:17:21 PM PDT 24
Finished Jun 13 03:22:07 PM PDT 24
Peak memory 260340 kb
Host smart-914242b8-efb6-4d7a-8c83-c225455b0400
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182
4559561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1824559561
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1320960579
Short name T199
Test name
Test status
Simulation time 1021337000 ps
CPU time 92.48 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:18:48 PM PDT 24
Peak memory 260836 kb
Host smart-bb7ed767-3907-4224-aab3-7fdbc3f75490
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320960579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1320960579
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2922962019
Short name T819
Test name
Test status
Simulation time 15487300 ps
CPU time 13.38 seconds
Started Jun 13 03:17:30 PM PDT 24
Finished Jun 13 03:17:44 PM PDT 24
Peak memory 260288 kb
Host smart-c46295af-cddb-4557-8350-69ba1f0b47a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922962019 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2922962019
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.926078121
Short name T79
Test name
Test status
Simulation time 3433121800 ps
CPU time 71.16 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:18:26 PM PDT 24
Peak memory 260892 kb
Host smart-203d9e4f-c8d5-49f2-8f76-3e13143d86ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926078121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.926078121
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.2461973053
Short name T693
Test name
Test status
Simulation time 1903124900 ps
CPU time 155.09 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:19:50 PM PDT 24
Peak memory 290908 kb
Host smart-a69ddade-231b-4663-9cf8-eb52ac6ac983
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461973053 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.2461973053
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3751875904
Short name T207
Test name
Test status
Simulation time 45388200 ps
CPU time 13.78 seconds
Started Jun 13 03:17:28 PM PDT 24
Finished Jun 13 03:17:42 PM PDT 24
Peak memory 261984 kb
Host smart-c6e772ab-4f46-4892-bf12-eacba7e8cf52
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3751875904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3751875904
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.741179818
Short name T618
Test name
Test status
Simulation time 58917200 ps
CPU time 110.26 seconds
Started Jun 13 03:17:07 PM PDT 24
Finished Jun 13 03:18:58 PM PDT 24
Peak memory 263588 kb
Host smart-eb811dad-6554-47d4-861f-6c5b2cd63d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741179818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.741179818
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2033058813
Short name T386
Test name
Test status
Simulation time 15858500 ps
CPU time 13.8 seconds
Started Jun 13 03:17:28 PM PDT 24
Finished Jun 13 03:17:43 PM PDT 24
Peak memory 266024 kb
Host smart-b13712cc-8973-404c-8add-dc34faaad639
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033058813 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2033058813
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.4148584579
Short name T569
Test name
Test status
Simulation time 37345800 ps
CPU time 13.57 seconds
Started Jun 13 03:17:20 PM PDT 24
Finished Jun 13 03:17:34 PM PDT 24
Peak memory 259436 kb
Host smart-104b505e-ec84-4494-82f6-ee7220fc7d65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148584579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.4148584579
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3740803064
Short name T745
Test name
Test status
Simulation time 876460400 ps
CPU time 1865.73 seconds
Started Jun 13 03:17:02 PM PDT 24
Finished Jun 13 03:48:10 PM PDT 24
Peak memory 291188 kb
Host smart-73919f29-716f-49e8-8a1c-d30ff0ee6c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740803064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3740803064
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1760839183
Short name T1009
Test name
Test status
Simulation time 219052400 ps
CPU time 31.72 seconds
Started Jun 13 03:17:27 PM PDT 24
Finished Jun 13 03:17:59 PM PDT 24
Peak memory 276144 kb
Host smart-e224b543-395d-4e32-ac7b-803d06fc1f6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760839183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1760839183
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3903233441
Short name T484
Test name
Test status
Simulation time 156646700 ps
CPU time 48.07 seconds
Started Jun 13 03:17:28 PM PDT 24
Finished Jun 13 03:18:17 PM PDT 24
Peak memory 275772 kb
Host smart-6d3bf5fc-41f5-48f4-a6f3-ff4c01f6cdcb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903233441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3903233441
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2819175517
Short name T792
Test name
Test status
Simulation time 184588500 ps
CPU time 35.25 seconds
Started Jun 13 03:17:19 PM PDT 24
Finished Jun 13 03:17:54 PM PDT 24
Peak memory 277164 kb
Host smart-45e7bc9b-5f2a-49b2-8150-127105d302c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819175517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2819175517
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.2645329017
Short name T557
Test name
Test status
Simulation time 25289300 ps
CPU time 14.53 seconds
Started Jun 13 03:17:16 PM PDT 24
Finished Jun 13 03:17:31 PM PDT 24
Peak memory 258848 kb
Host smart-cdb3f2cc-a427-4bc7-a292-0006d2c15f03
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2645329017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.2645329017
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.2335279935
Short name T877
Test name
Test status
Simulation time 35552200 ps
CPU time 22.58 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:17:37 PM PDT 24
Peak memory 265668 kb
Host smart-ed2265ab-16bb-46f7-80d8-b3644f3607de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335279935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.2335279935
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2165491360
Short name T170
Test name
Test status
Simulation time 93489078600 ps
CPU time 1554.52 seconds
Started Jun 13 03:17:27 PM PDT 24
Finished Jun 13 03:43:23 PM PDT 24
Peak memory 552680 kb
Host smart-e6ddc238-b2f7-44f8-a71d-ff383ec301f8
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165491360 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2165491360
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.24000239
Short name T455
Test name
Test status
Simulation time 623752300 ps
CPU time 109.33 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:19:04 PM PDT 24
Peak memory 290500 kb
Host smart-cadc8a7b-e446-469f-8617-50875081d9e8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000239 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.flash_ctrl_ro.24000239
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3020220593
Short name T577
Test name
Test status
Simulation time 1089943000 ps
CPU time 138.51 seconds
Started Jun 13 03:17:16 PM PDT 24
Finished Jun 13 03:19:35 PM PDT 24
Peak memory 282344 kb
Host smart-a6cd5e26-00da-4af4-b807-04e887d23530
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020220593 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3020220593
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1808955743
Short name T971
Test name
Test status
Simulation time 13771370100 ps
CPU time 564.48 seconds
Started Jun 13 03:17:16 PM PDT 24
Finished Jun 13 03:26:41 PM PDT 24
Peak memory 315044 kb
Host smart-0239fa57-bdb9-42cc-8e55-42c4fad036c8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808955743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1808955743
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3970450108
Short name T794
Test name
Test status
Simulation time 28197200 ps
CPU time 31.13 seconds
Started Jun 13 03:17:19 PM PDT 24
Finished Jun 13 03:17:51 PM PDT 24
Peak memory 275720 kb
Host smart-c328e4c6-ed7c-44fb-b4a2-0927f5ba37bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970450108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3970450108
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.2616411114
Short name T508
Test name
Test status
Simulation time 148323300 ps
CPU time 31.27 seconds
Started Jun 13 03:17:21 PM PDT 24
Finished Jun 13 03:17:53 PM PDT 24
Peak memory 275384 kb
Host smart-ebb556bb-43aa-4a03-86f1-a45dc53f2900
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616411114 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.2616411114
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3275238867
Short name T341
Test name
Test status
Simulation time 1693784300 ps
CPU time 67.94 seconds
Started Jun 13 03:17:21 PM PDT 24
Finished Jun 13 03:18:29 PM PDT 24
Peak memory 264116 kb
Host smart-de25940e-f097-4d9f-bd60-0ae578e126e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275238867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3275238867
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.3209765129
Short name T111
Test name
Test status
Simulation time 1231415500 ps
CPU time 68.16 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:18:23 PM PDT 24
Peak memory 265880 kb
Host smart-a5c593a2-c971-44b4-a1ed-67c1f38e0447
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209765129 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.3209765129
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.69809238
Short name T446
Test name
Test status
Simulation time 2125131300 ps
CPU time 59.72 seconds
Started Jun 13 03:17:14 PM PDT 24
Finished Jun 13 03:18:15 PM PDT 24
Peak memory 266000 kb
Host smart-dae2a5ef-2d5e-4390-90bd-cf2ef40f9342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69809238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_counter.69809238
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3291480633
Short name T487
Test name
Test status
Simulation time 77529800 ps
CPU time 123.91 seconds
Started Jun 13 03:17:03 PM PDT 24
Finished Jun 13 03:19:08 PM PDT 24
Peak memory 276472 kb
Host smart-bcc9e1ea-5ebf-4941-b6fb-31942f1b84a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291480633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3291480633
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1795676699
Short name T498
Test name
Test status
Simulation time 16909800 ps
CPU time 26.68 seconds
Started Jun 13 03:17:00 PM PDT 24
Finished Jun 13 03:17:28 PM PDT 24
Peak memory 260076 kb
Host smart-9c0b0b27-af90-41e7-8851-a4b1e5a169bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795676699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1795676699
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.897592413
Short name T506
Test name
Test status
Simulation time 855461500 ps
CPU time 1055.31 seconds
Started Jun 13 03:17:25 PM PDT 24
Finished Jun 13 03:35:01 PM PDT 24
Peak memory 285644 kb
Host smart-df755f29-fc8c-48c4-b9a0-cd5155d0261a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897592413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress
_all.897592413
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.2284649437
Short name T855
Test name
Test status
Simulation time 70786000 ps
CPU time 27.21 seconds
Started Jun 13 03:17:00 PM PDT 24
Finished Jun 13 03:17:28 PM PDT 24
Peak memory 262560 kb
Host smart-19deecd4-e80f-4260-a79a-bc3d7d3e1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284649437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2284649437
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.1761293322
Short name T518
Test name
Test status
Simulation time 8527038500 ps
CPU time 182.06 seconds
Started Jun 13 03:17:13 PM PDT 24
Finished Jun 13 03:20:16 PM PDT 24
Peak memory 265556 kb
Host smart-c96338ea-fc31-46db-954d-2879d7f83b3a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761293322 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.1761293322
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2875532826
Short name T668
Test name
Test status
Simulation time 269273100 ps
CPU time 15 seconds
Started Jun 13 03:17:11 PM PDT 24
Finished Jun 13 03:17:27 PM PDT 24
Peak memory 265732 kb
Host smart-12456d92-7348-4bcd-a472-1ddc0463c8fd
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2875532826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2875532826
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.2948771073
Short name T9
Test name
Test status
Simulation time 22372600 ps
CPU time 13.53 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:17:56 PM PDT 24
Peak memory 265904 kb
Host smart-6e5c2895-dd77-4686-be2a-c4ae355a2c11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948771073 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.2948771073
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.809396532
Short name T747
Test name
Test status
Simulation time 54652600 ps
CPU time 13.61 seconds
Started Jun 13 03:17:50 PM PDT 24
Finished Jun 13 03:18:05 PM PDT 24
Peak memory 258740 kb
Host smart-2b986dd3-8a6e-4766-ad7e-75fb8dbf63c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809396532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.809396532
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.3910575501
Short name T927
Test name
Test status
Simulation time 35859800 ps
CPU time 13.69 seconds
Started Jun 13 03:17:44 PM PDT 24
Finished Jun 13 03:17:59 PM PDT 24
Peak memory 262028 kb
Host smart-fd4736af-f195-4ff5-a004-7215a632b71d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910575501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.3910575501
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.1337019568
Short name T650
Test name
Test status
Simulation time 14828700 ps
CPU time 16.1 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:17:58 PM PDT 24
Peak memory 275216 kb
Host smart-8d2ac796-9409-4756-88ad-cb5de9816043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337019568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1337019568
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.143244370
Short name T846
Test name
Test status
Simulation time 292366000 ps
CPU time 104.43 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:19:26 PM PDT 24
Peak memory 282244 kb
Host smart-27d0a6a1-7377-4d67-92c3-2021a542d4d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143244370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_derr_detect.143244370
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.1190341520
Short name T145
Test name
Test status
Simulation time 3084964800 ps
CPU time 292.44 seconds
Started Jun 13 03:17:37 PM PDT 24
Finished Jun 13 03:22:30 PM PDT 24
Peak memory 263816 kb
Host smart-d84e13c9-556c-4bda-92ba-befb7a51a526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190341520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.1190341520
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.3362139745
Short name T699
Test name
Test status
Simulation time 18432338600 ps
CPU time 2407.33 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 03:57:43 PM PDT 24
Peak memory 264900 kb
Host smart-ad1e3c5a-a46b-4208-8029-a61d05c9b7c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362139745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.3362139745
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1194742931
Short name T1044
Test name
Test status
Simulation time 1109778300 ps
CPU time 2906.7 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 04:06:02 PM PDT 24
Peak memory 265068 kb
Host smart-93491ed4-33f5-4016-80f4-c5d9f3350a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194742931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1194742931
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.1599720799
Short name T838
Test name
Test status
Simulation time 757991200 ps
CPU time 763.43 seconds
Started Jun 13 03:17:37 PM PDT 24
Finished Jun 13 03:30:21 PM PDT 24
Peak memory 273856 kb
Host smart-d067e6bb-6947-4117-a2d8-b63aea5b17d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599720799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1599720799
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2968785875
Short name T317
Test name
Test status
Simulation time 4668015500 ps
CPU time 46.21 seconds
Started Jun 13 03:17:41 PM PDT 24
Finished Jun 13 03:18:30 PM PDT 24
Peak memory 263396 kb
Host smart-6273174c-833e-4ab6-b5f6-9e6b01cec4e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968785875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2968785875
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.3873820738
Short name T23
Test name
Test status
Simulation time 93763975500 ps
CPU time 2668.76 seconds
Started Jun 13 03:17:31 PM PDT 24
Finished Jun 13 04:02:01 PM PDT 24
Peak memory 263368 kb
Host smart-c08feced-bc52-4fe9-970d-f69f6bdbdb75
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873820738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.3873820738
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2241277517
Short name T229
Test name
Test status
Simulation time 51074600 ps
CPU time 38.03 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:18:19 PM PDT 24
Peak memory 262960 kb
Host smart-99e1efc5-9913-4a74-b375-9b6613daf878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2241277517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2241277517
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2870904313
Short name T724
Test name
Test status
Simulation time 51378000 ps
CPU time 13.33 seconds
Started Jun 13 03:17:43 PM PDT 24
Finished Jun 13 03:17:58 PM PDT 24
Peak memory 265332 kb
Host smart-bbae61d8-4f14-439b-8490-4fd415fd5336
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870904313 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2870904313
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1597392295
Short name T104
Test name
Test status
Simulation time 746173456300 ps
CPU time 2065.83 seconds
Started Jun 13 03:17:31 PM PDT 24
Finished Jun 13 03:51:58 PM PDT 24
Peak memory 265660 kb
Host smart-4c47cd59-4131-48f1-9f76-5cb4b8e4ed54
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597392295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1597392295
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3264381436
Short name T781
Test name
Test status
Simulation time 80145466500 ps
CPU time 879.68 seconds
Started Jun 13 03:17:31 PM PDT 24
Finished Jun 13 03:32:12 PM PDT 24
Peak memory 264348 kb
Host smart-8ec9811d-6604-4783-a3ca-32fc7215f028
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264381436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.3264381436
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1883458360
Short name T291
Test name
Test status
Simulation time 6136548400 ps
CPU time 233.72 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:21:34 PM PDT 24
Peak memory 261692 kb
Host smart-5cf498c9-d563-423c-a99f-ef0d21aab6cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883458360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1883458360
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1630056452
Short name T241
Test name
Test status
Simulation time 15940830000 ps
CPU time 769.61 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:30:30 PM PDT 24
Peak memory 337352 kb
Host smart-ce6e7b37-a7c2-42ea-bf5a-33fcacd6e5b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630056452 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1630056452
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2908626126
Short name T37
Test name
Test status
Simulation time 2321935500 ps
CPU time 134.27 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:19:57 PM PDT 24
Peak memory 294584 kb
Host smart-53c0bc76-405c-46cd-94a0-c7d9825a2d0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908626126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2908626126
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.66217687
Short name T380
Test name
Test status
Simulation time 11546145300 ps
CPU time 143.73 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:20:06 PM PDT 24
Peak memory 293464 kb
Host smart-3df4cc57-03ff-46c1-9bff-468a903b33ad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66217687 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.66217687
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.4231671298
Short name T711
Test name
Test status
Simulation time 7566363100 ps
CPU time 64.8 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:18:46 PM PDT 24
Peak memory 260940 kb
Host smart-d9fefa0f-545b-467d-adec-789a91d3423e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231671298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.4231671298
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2162560151
Short name T1091
Test name
Test status
Simulation time 15099400 ps
CPU time 13.26 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:18:02 PM PDT 24
Peak memory 260340 kb
Host smart-27fc5363-9018-48d9-bb3b-2c1145dc03b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162560151 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2162560151
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.4131139072
Short name T78
Test name
Test status
Simulation time 2214810400 ps
CPU time 73.9 seconds
Started Jun 13 03:17:35 PM PDT 24
Finished Jun 13 03:18:50 PM PDT 24
Peak memory 261108 kb
Host smart-1738e44c-5368-4307-8681-9c40d33a4112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131139072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.4131139072
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2719391139
Short name T137
Test name
Test status
Simulation time 7984826200 ps
CPU time 603.53 seconds
Started Jun 13 03:17:35 PM PDT 24
Finished Jun 13 03:27:40 PM PDT 24
Peak memory 275040 kb
Host smart-bd070ec5-c252-47e5-af1b-b3310eef9087
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719391139 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2719391139
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.1900687270
Short name T883
Test name
Test status
Simulation time 42151500 ps
CPU time 109.01 seconds
Started Jun 13 03:17:38 PM PDT 24
Finished Jun 13 03:19:28 PM PDT 24
Peak memory 260648 kb
Host smart-c8adb9c9-80fc-460f-bca0-fa2003bc8aec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900687270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.1900687270
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2858756411
Short name T186
Test name
Test status
Simulation time 53608500 ps
CPU time 64.97 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 03:18:39 PM PDT 24
Peak memory 263600 kb
Host smart-9fac148a-be68-4388-913d-c8dbb343afda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858756411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2858756411
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3347141063
Short name T206
Test name
Test status
Simulation time 23721500 ps
CPU time 14.13 seconds
Started Jun 13 03:17:45 PM PDT 24
Finished Jun 13 03:18:02 PM PDT 24
Peak memory 266020 kb
Host smart-0e062e72-5199-42e8-b2fd-69ffccb9f671
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347141063 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3347141063
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.3518158766
Short name T777
Test name
Test status
Simulation time 104903800 ps
CPU time 13.4 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:17:54 PM PDT 24
Peak memory 265660 kb
Host smart-40441a0e-8696-47ae-8c41-5082a1236c42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518158766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.3518158766
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1986402658
Short name T849
Test name
Test status
Simulation time 482837400 ps
CPU time 443.14 seconds
Started Jun 13 03:17:34 PM PDT 24
Finished Jun 13 03:24:59 PM PDT 24
Peak memory 282268 kb
Host smart-650bb795-1cfe-4906-8b3e-14266ef0d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986402658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1986402658
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2036964959
Short name T592
Test name
Test status
Simulation time 3178722100 ps
CPU time 147.95 seconds
Started Jun 13 03:17:32 PM PDT 24
Finished Jun 13 03:20:01 PM PDT 24
Peak memory 263052 kb
Host smart-ca77bf5f-90c9-4139-b4a8-a44bffd711c9
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2036964959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2036964959
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.762832781
Short name T5
Test name
Test status
Simulation time 64883700 ps
CPU time 29.29 seconds
Started Jun 13 03:17:38 PM PDT 24
Finished Jun 13 03:18:08 PM PDT 24
Peak memory 275376 kb
Host smart-7742c477-3dc9-4b6d-adb8-e16e6f142b6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762832781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rd_intg.762832781
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.137751636
Short name T663
Test name
Test status
Simulation time 33411000 ps
CPU time 22.57 seconds
Started Jun 13 03:17:34 PM PDT 24
Finished Jun 13 03:17:58 PM PDT 24
Peak memory 265952 kb
Host smart-f876da7d-4195-47be-9f4d-44b906e069de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137751636 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.137751636
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.486524778
Short name T787
Test name
Test status
Simulation time 85434100 ps
CPU time 20.6 seconds
Started Jun 13 03:17:37 PM PDT 24
Finished Jun 13 03:17:58 PM PDT 24
Peak memory 265428 kb
Host smart-f187abe9-9200-4b92-8c9c-7fa6e12e556d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486524778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.486524778
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3221649235
Short name T409
Test name
Test status
Simulation time 2149121200 ps
CPU time 121.94 seconds
Started Jun 13 03:17:35 PM PDT 24
Finished Jun 13 03:19:38 PM PDT 24
Peak memory 290480 kb
Host smart-7cb39481-d1ca-4b98-bcbe-322fc3a854b9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221649235 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.3221649235
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.4090101758
Short name T238
Test name
Test status
Simulation time 558385000 ps
CPU time 141.63 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:20:04 PM PDT 24
Peak memory 282416 kb
Host smart-cbf27265-a7ad-4fa0-a2d5-2adaad02fed5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4090101758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.4090101758
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1769478255
Short name T675
Test name
Test status
Simulation time 3480908600 ps
CPU time 162.93 seconds
Started Jun 13 03:17:38 PM PDT 24
Finished Jun 13 03:20:22 PM PDT 24
Peak memory 282320 kb
Host smart-3e6c75ae-fbbb-4c81-94be-107d2b104481
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769478255 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1769478255
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2858984483
Short name T860
Test name
Test status
Simulation time 3936650300 ps
CPU time 648.71 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 03:28:22 PM PDT 24
Peak memory 314656 kb
Host smart-63717645-5bae-40b7-bfaa-af192a9b6016
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858984483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2858984483
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1761968535
Short name T192
Test name
Test status
Simulation time 56129400 ps
CPU time 31.24 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:18:13 PM PDT 24
Peak memory 275880 kb
Host smart-f0655785-a208-4c1c-9219-959168343d0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761968535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1761968535
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2716288197
Short name T108
Test name
Test status
Simulation time 1080146500 ps
CPU time 4947.81 seconds
Started Jun 13 03:17:42 PM PDT 24
Finished Jun 13 04:40:12 PM PDT 24
Peak memory 285672 kb
Host smart-c4aa02b4-f09b-4821-997b-c043011efc70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716288197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2716288197
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3790058193
Short name T1026
Test name
Test status
Simulation time 926589300 ps
CPU time 58.1 seconds
Started Jun 13 03:17:35 PM PDT 24
Finished Jun 13 03:18:34 PM PDT 24
Peak memory 265712 kb
Host smart-6e89646a-f17f-4592-b8c8-de994ebbf0f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790058193 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3790058193
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.618825215
Short name T836
Test name
Test status
Simulation time 3518178700 ps
CPU time 90.3 seconds
Started Jun 13 03:17:35 PM PDT 24
Finished Jun 13 03:19:07 PM PDT 24
Peak memory 275404 kb
Host smart-038e1dbb-a9f9-4255-a451-81d0e6e1d622
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618825215 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_counter.618825215
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.866674920
Short name T483
Test name
Test status
Simulation time 27806500 ps
CPU time 146.55 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 03:20:02 PM PDT 24
Peak memory 280400 kb
Host smart-a86a98ab-ad06-4620-87b5-eedc19a59eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866674920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.866674920
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2854472403
Short name T811
Test name
Test status
Simulation time 22822300 ps
CPU time 25.95 seconds
Started Jun 13 03:17:34 PM PDT 24
Finished Jun 13 03:18:01 PM PDT 24
Peak memory 260144 kb
Host smart-c7cb6245-7af2-42e8-b17f-c2798669c2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854472403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2854472403
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.2932892170
Short name T109
Test name
Test status
Simulation time 154758600 ps
CPU time 357.74 seconds
Started Jun 13 03:17:40 PM PDT 24
Finished Jun 13 03:23:39 PM PDT 24
Peak memory 290296 kb
Host smart-2ce8bca6-bbf0-4bf4-8d36-a14ab005e362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932892170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.2932892170
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2122039955
Short name T888
Test name
Test status
Simulation time 80209300 ps
CPU time 23.61 seconds
Started Jun 13 03:17:33 PM PDT 24
Finished Jun 13 03:17:57 PM PDT 24
Peak memory 260088 kb
Host smart-4c48c72d-cc9e-4ff2-83ab-8b3835d166de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122039955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2122039955
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.2929160467
Short name T823
Test name
Test status
Simulation time 2186308200 ps
CPU time 180.25 seconds
Started Jun 13 03:17:32 PM PDT 24
Finished Jun 13 03:20:33 PM PDT 24
Peak memory 265280 kb
Host smart-4f563a40-2e60-40d6-b021-6ecb89c3f407
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929160467 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.2929160467
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.3593703141
Short name T25
Test name
Test status
Simulation time 44434200 ps
CPU time 15.46 seconds
Started Jun 13 03:17:39 PM PDT 24
Finished Jun 13 03:17:55 PM PDT 24
Peak memory 261236 kb
Host smart-ebfdbe5c-cc42-4a57-b1cc-75fe6b411719
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593703141 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.3593703141
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3348346942
Short name T505
Test name
Test status
Simulation time 99825900 ps
CPU time 14.31 seconds
Started Jun 13 03:21:51 PM PDT 24
Finished Jun 13 03:22:06 PM PDT 24
Peak memory 265656 kb
Host smart-c2ecc597-a685-4f9a-8bc7-8ba19563d796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348346942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3348346942
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.403627812
Short name T461
Test name
Test status
Simulation time 22296300 ps
CPU time 16.3 seconds
Started Jun 13 03:21:47 PM PDT 24
Finished Jun 13 03:22:04 PM PDT 24
Peak memory 275220 kb
Host smart-a511feef-16ef-46d6-8407-70e157eb1a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403627812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.403627812
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1550375933
Short name T921
Test name
Test status
Simulation time 10020226400 ps
CPU time 89.96 seconds
Started Jun 13 03:21:46 PM PDT 24
Finished Jun 13 03:23:17 PM PDT 24
Peak memory 332572 kb
Host smart-c80d77ef-fc7c-494a-9dbf-9897d7178c7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550375933 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1550375933
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3426052269
Short name T646
Test name
Test status
Simulation time 100156248300 ps
CPU time 941.69 seconds
Started Jun 13 03:21:33 PM PDT 24
Finished Jun 13 03:37:17 PM PDT 24
Peak memory 264400 kb
Host smart-38e15097-2abe-4824-8216-468e08b15620
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426052269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3426052269
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1934408714
Short name T84
Test name
Test status
Simulation time 2370583700 ps
CPU time 82.97 seconds
Started Jun 13 03:21:32 PM PDT 24
Finished Jun 13 03:22:57 PM PDT 24
Peak memory 261108 kb
Host smart-7b1d4aa2-bb96-4918-b173-111e242082db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934408714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1934408714
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.3154479958
Short name T1039
Test name
Test status
Simulation time 3093547000 ps
CPU time 146.77 seconds
Started Jun 13 03:21:39 PM PDT 24
Finished Jun 13 03:24:07 PM PDT 24
Peak memory 285312 kb
Host smart-e8bb3b31-adbb-4442-b3ec-88eeb30030cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154479958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.3154479958
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2162082722
Short name T410
Test name
Test status
Simulation time 11544331700 ps
CPU time 143.07 seconds
Started Jun 13 03:21:43 PM PDT 24
Finished Jun 13 03:24:07 PM PDT 24
Peak memory 293532 kb
Host smart-b4aef4db-ffb9-4861-a200-c3df858b29bc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162082722 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.2162082722
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.3830460311
Short name T382
Test name
Test status
Simulation time 1706361700 ps
CPU time 61.59 seconds
Started Jun 13 03:21:31 PM PDT 24
Finished Jun 13 03:22:34 PM PDT 24
Peak memory 260968 kb
Host smart-ce8b4c6d-3dc9-4ace-93fe-bbd9328002b4
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830460311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3
830460311
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1046677572
Short name T773
Test name
Test status
Simulation time 45633800 ps
CPU time 13.41 seconds
Started Jun 13 03:21:47 PM PDT 24
Finished Jun 13 03:22:02 PM PDT 24
Peak memory 260320 kb
Host smart-b9fd24e7-44c3-49ca-adcb-2f6eb037d24f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046677572 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1046677572
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1784320463
Short name T890
Test name
Test status
Simulation time 3743618400 ps
CPU time 172.9 seconds
Started Jun 13 03:21:32 PM PDT 24
Finished Jun 13 03:24:27 PM PDT 24
Peak memory 265564 kb
Host smart-d505f9b8-f065-4490-b5db-0e0dbe2431de
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784320463 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1784320463
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.4207441811
Short name T489
Test name
Test status
Simulation time 151838600 ps
CPU time 135.37 seconds
Started Jun 13 03:21:34 PM PDT 24
Finished Jun 13 03:23:51 PM PDT 24
Peak memory 261460 kb
Host smart-eb9b4c3d-8e71-45bd-8adb-dbac37b05ad6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207441811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.4207441811
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.1609010730
Short name T928
Test name
Test status
Simulation time 116475400 ps
CPU time 69.01 seconds
Started Jun 13 03:21:33 PM PDT 24
Finished Jun 13 03:22:44 PM PDT 24
Peak memory 263568 kb
Host smart-21b8b700-976a-4c49-ace8-91c1a593f262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609010730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.1609010730
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.1253428903
Short name T840
Test name
Test status
Simulation time 2296488900 ps
CPU time 187.31 seconds
Started Jun 13 03:21:43 PM PDT 24
Finished Jun 13 03:24:51 PM PDT 24
Peak memory 260656 kb
Host smart-57871f8b-cb72-4a59-bfd4-575645eb16e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253428903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.1253428903
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.709971780
Short name T703
Test name
Test status
Simulation time 752122900 ps
CPU time 875.63 seconds
Started Jun 13 03:21:33 PM PDT 24
Finished Jun 13 03:36:11 PM PDT 24
Peak memory 284200 kb
Host smart-af1d987c-fd7e-4784-b68c-230945b7aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709971780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.709971780
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.197031143
Short name T1084
Test name
Test status
Simulation time 96008400 ps
CPU time 32.73 seconds
Started Jun 13 03:21:46 PM PDT 24
Finished Jun 13 03:22:20 PM PDT 24
Peak memory 274072 kb
Host smart-7cd073ee-dcbf-4d1f-897f-3ade0a58fba0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197031143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_re_evict.197031143
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.1992412376
Short name T690
Test name
Test status
Simulation time 3250058200 ps
CPU time 125.94 seconds
Started Jun 13 03:21:40 PM PDT 24
Finished Jun 13 03:23:47 PM PDT 24
Peak memory 282328 kb
Host smart-fdca7966-dd41-4f10-b795-16fcfb3401eb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992412376 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.1992412376
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.2538967350
Short name T765
Test name
Test status
Simulation time 3852180400 ps
CPU time 715.38 seconds
Started Jun 13 03:21:40 PM PDT 24
Finished Jun 13 03:33:36 PM PDT 24
Peak memory 315056 kb
Host smart-56d6a179-745e-4918-ae3d-ace2c72e5799
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538967350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.2538967350
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.561750774
Short name T814
Test name
Test status
Simulation time 28732200 ps
CPU time 31.11 seconds
Started Jun 13 03:21:47 PM PDT 24
Finished Jun 13 03:22:20 PM PDT 24
Peak memory 274092 kb
Host smart-741706aa-8ab0-44ef-860f-850966f2f79e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561750774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_rw_evict.561750774
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2569041989
Short name T579
Test name
Test status
Simulation time 28970300 ps
CPU time 27.84 seconds
Started Jun 13 03:21:45 PM PDT 24
Finished Jun 13 03:22:13 PM PDT 24
Peak memory 268136 kb
Host smart-b63d9f3b-1c5d-4fe3-9baa-5efdc6e03b5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569041989 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2569041989
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3740138174
Short name T820
Test name
Test status
Simulation time 1470183600 ps
CPU time 64.41 seconds
Started Jun 13 03:21:47 PM PDT 24
Finished Jun 13 03:22:53 PM PDT 24
Peak memory 264960 kb
Host smart-dbaffc87-d27b-4827-bcd4-4dcdc2ad9887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740138174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3740138174
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.4026817179
Short name T600
Test name
Test status
Simulation time 89822900 ps
CPU time 52.99 seconds
Started Jun 13 03:21:33 PM PDT 24
Finished Jun 13 03:22:28 PM PDT 24
Peak memory 271548 kb
Host smart-0b900239-d0c9-4424-81e3-916d7e29e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026817179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.4026817179
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.133811720
Short name T1082
Test name
Test status
Simulation time 4573614500 ps
CPU time 199.72 seconds
Started Jun 13 03:21:32 PM PDT 24
Finished Jun 13 03:24:53 PM PDT 24
Peak memory 259756 kb
Host smart-c23b9eaa-a993-4185-b598-f548a113b5af
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133811720 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.133811720
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3302282328
Short name T423
Test name
Test status
Simulation time 142941000 ps
CPU time 13.85 seconds
Started Jun 13 03:22:09 PM PDT 24
Finished Jun 13 03:22:24 PM PDT 24
Peak memory 265640 kb
Host smart-bc6c48b8-e6c8-4a04-9a82-f9e896097dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302282328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3302282328
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.1146062343
Short name T389
Test name
Test status
Simulation time 174655000 ps
CPU time 13.5 seconds
Started Jun 13 03:22:04 PM PDT 24
Finished Jun 13 03:22:18 PM PDT 24
Peak memory 275276 kb
Host smart-82e4af94-83f5-4dbd-92e9-764d147371f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146062343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1146062343
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.853868129
Short name T270
Test name
Test status
Simulation time 10032437100 ps
CPU time 62.11 seconds
Started Jun 13 03:22:10 PM PDT 24
Finished Jun 13 03:23:13 PM PDT 24
Peak memory 287940 kb
Host smart-cc9ae100-dd3f-4072-87c5-66ca5ee5412d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853868129 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.853868129
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1519437896
Short name T897
Test name
Test status
Simulation time 760411576600 ps
CPU time 998.87 seconds
Started Jun 13 03:21:49 PM PDT 24
Finished Jun 13 03:38:29 PM PDT 24
Peak memory 265184 kb
Host smart-593856a2-e7ff-49e7-be75-b785e613425e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519437896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.1519437896
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.1859220869
Short name T232
Test name
Test status
Simulation time 39997644400 ps
CPU time 149.01 seconds
Started Jun 13 03:21:53 PM PDT 24
Finished Jun 13 03:24:23 PM PDT 24
Peak memory 263520 kb
Host smart-2384f7d6-39f4-4d15-aa89-2f868698683a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859220869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.1859220869
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.2356559343
Short name T306
Test name
Test status
Simulation time 762717600 ps
CPU time 175.66 seconds
Started Jun 13 03:21:56 PM PDT 24
Finished Jun 13 03:24:52 PM PDT 24
Peak memory 294012 kb
Host smart-f45b3873-bf88-46e3-a05e-307ad36718cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356559343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.2356559343
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.241058339
Short name T587
Test name
Test status
Simulation time 30934250400 ps
CPU time 286.26 seconds
Started Jun 13 03:21:59 PM PDT 24
Finished Jun 13 03:26:45 PM PDT 24
Peak memory 285264 kb
Host smart-e2a1ce6b-613a-4a70-8559-c4701a9477eb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241058339 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.241058339
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1583337479
Short name T274
Test name
Test status
Simulation time 86131700 ps
CPU time 13.53 seconds
Started Jun 13 03:22:09 PM PDT 24
Finished Jun 13 03:22:24 PM PDT 24
Peak memory 265272 kb
Host smart-52e507ec-b030-416e-9d7c-25421a57db14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583337479 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1583337479
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3931929327
Short name T208
Test name
Test status
Simulation time 2668508100 ps
CPU time 123.4 seconds
Started Jun 13 03:21:52 PM PDT 24
Finished Jun 13 03:23:56 PM PDT 24
Peak memory 265620 kb
Host smart-8ec7dcc1-511f-479a-8ad5-5ce700aae16e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931929327 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3931929327
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3558841477
Short name T1053
Test name
Test status
Simulation time 208107500 ps
CPU time 130.26 seconds
Started Jun 13 03:21:52 PM PDT 24
Finished Jun 13 03:24:03 PM PDT 24
Peak memory 261396 kb
Host smart-4b0b1201-eb81-40af-9eab-d445d8e4ffda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558841477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3558841477
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2076420541
Short name T578
Test name
Test status
Simulation time 182424500 ps
CPU time 442.93 seconds
Started Jun 13 03:21:52 PM PDT 24
Finished Jun 13 03:29:16 PM PDT 24
Peak memory 263352 kb
Host smart-3886b813-9cb8-47f0-bb35-87a9edfd7872
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076420541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2076420541
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.1741268656
Short name T1075
Test name
Test status
Simulation time 93063300 ps
CPU time 13.81 seconds
Started Jun 13 03:21:58 PM PDT 24
Finished Jun 13 03:22:12 PM PDT 24
Peak memory 259208 kb
Host smart-f6390f59-d4ea-4682-89c1-785676918cb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741268656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.1741268656
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.2558379865
Short name T672
Test name
Test status
Simulation time 626152600 ps
CPU time 555.82 seconds
Started Jun 13 03:21:50 PM PDT 24
Finished Jun 13 03:31:07 PM PDT 24
Peak memory 283236 kb
Host smart-923db247-4223-4c78-88a9-66898f794eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558379865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.2558379865
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3841156058
Short name T414
Test name
Test status
Simulation time 124397900 ps
CPU time 34.51 seconds
Started Jun 13 03:22:05 PM PDT 24
Finished Jun 13 03:22:41 PM PDT 24
Peak memory 275856 kb
Host smart-7d367fde-4674-4f57-a19c-bbab642ee238
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841156058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3841156058
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.1509369249
Short name T839
Test name
Test status
Simulation time 943271400 ps
CPU time 103.23 seconds
Started Jun 13 03:21:56 PM PDT 24
Finished Jun 13 03:23:40 PM PDT 24
Peak memory 281268 kb
Host smart-2ee14799-6f7c-44ac-abcf-bffd02108ac1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509369249 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.1509369249
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.1467907141
Short name T449
Test name
Test status
Simulation time 13939921800 ps
CPU time 548.69 seconds
Started Jun 13 03:21:57 PM PDT 24
Finished Jun 13 03:31:06 PM PDT 24
Peak memory 309768 kb
Host smart-8fc5cb94-3539-4273-9504-439b7a226e2f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467907141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.1467907141
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1141270154
Short name T547
Test name
Test status
Simulation time 80034600 ps
CPU time 28.95 seconds
Started Jun 13 03:22:10 PM PDT 24
Finished Jun 13 03:22:40 PM PDT 24
Peak memory 276128 kb
Host smart-9ed7e49e-ff54-4edf-8a4f-97f9837586a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141270154 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1141270154
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3631443265
Short name T378
Test name
Test status
Simulation time 2168107400 ps
CPU time 78.9 seconds
Started Jun 13 03:22:04 PM PDT 24
Finished Jun 13 03:23:23 PM PDT 24
Peak memory 264464 kb
Host smart-f885edf5-c821-4d73-a3bb-bb9764ed4850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631443265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3631443265
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.405552824
Short name T818
Test name
Test status
Simulation time 146190500 ps
CPU time 168.26 seconds
Started Jun 13 03:21:54 PM PDT 24
Finished Jun 13 03:24:42 PM PDT 24
Peak memory 277600 kb
Host smart-1d6e0df2-dd13-4900-8378-7b29bc1f8e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405552824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.405552824
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.2174471814
Short name T624
Test name
Test status
Simulation time 2106464700 ps
CPU time 182.79 seconds
Started Jun 13 03:21:55 PM PDT 24
Finished Jun 13 03:24:58 PM PDT 24
Peak memory 260332 kb
Host smart-1ec5cb0a-1063-4f83-96c4-55d80613767b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174471814 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.2174471814
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.4000937364
Short name T573
Test name
Test status
Simulation time 176221900 ps
CPU time 13.75 seconds
Started Jun 13 03:22:36 PM PDT 24
Finished Jun 13 03:22:51 PM PDT 24
Peak memory 258644 kb
Host smart-9aca17ee-b49e-4716-ba32-4cfa4302b3e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000937364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
4000937364
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.513872335
Short name T415
Test name
Test status
Simulation time 15994700 ps
CPU time 13.26 seconds
Started Jun 13 03:22:21 PM PDT 24
Finished Jun 13 03:22:34 PM PDT 24
Peak memory 284552 kb
Host smart-a5bb23cb-9997-4f1d-a67d-b6540e808699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513872335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.513872335
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.3408014332
Short name T43
Test name
Test status
Simulation time 23665700 ps
CPU time 20.7 seconds
Started Jun 13 03:22:22 PM PDT 24
Finished Jun 13 03:22:43 PM PDT 24
Peak memory 265820 kb
Host smart-15b5e32c-20d7-46f5-b8ef-89da0a394823
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408014332 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.3408014332
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3709204493
Short name T177
Test name
Test status
Simulation time 10019566000 ps
CPU time 78.87 seconds
Started Jun 13 03:22:28 PM PDT 24
Finished Jun 13 03:23:47 PM PDT 24
Peak memory 306956 kb
Host smart-f06b498f-2fba-44ae-b5b4-35d1af33a49e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709204493 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3709204493
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1402652477
Short name T147
Test name
Test status
Simulation time 25890200 ps
CPU time 13.57 seconds
Started Jun 13 03:22:26 PM PDT 24
Finished Jun 13 03:22:40 PM PDT 24
Peak memory 265800 kb
Host smart-f965d84f-1187-49bf-9544-9cb132a72dc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402652477 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1402652477
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3982914542
Short name T174
Test name
Test status
Simulation time 200194131000 ps
CPU time 929.57 seconds
Started Jun 13 03:22:16 PM PDT 24
Finished Jun 13 03:37:46 PM PDT 24
Peak memory 264616 kb
Host smart-cc091b7e-7736-4311-a863-d7da00504332
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982914542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3982914542
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.3021327487
Short name T872
Test name
Test status
Simulation time 11723656000 ps
CPU time 203.3 seconds
Started Jun 13 03:22:10 PM PDT 24
Finished Jun 13 03:25:34 PM PDT 24
Peak memory 261348 kb
Host smart-f574393f-8a69-49d7-bab3-a9d92cb13cf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021327487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.3021327487
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.1733643541
Short name T904
Test name
Test status
Simulation time 2379216500 ps
CPU time 118.12 seconds
Started Jun 13 03:22:19 PM PDT 24
Finished Jun 13 03:24:17 PM PDT 24
Peak memory 298088 kb
Host smart-843e445c-f564-485f-8e5a-18e3acc0e1b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733643541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.1733643541
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.1990447265
Short name T905
Test name
Test status
Simulation time 23226792700 ps
CPU time 140.52 seconds
Started Jun 13 03:22:17 PM PDT 24
Finished Jun 13 03:24:38 PM PDT 24
Peak memory 294600 kb
Host smart-62f25dc1-41c1-4f06-bc3c-9b01c65423e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990447265 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.1990447265
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1547171742
Short name T801
Test name
Test status
Simulation time 26413500 ps
CPU time 13.6 seconds
Started Jun 13 03:22:22 PM PDT 24
Finished Jun 13 03:22:37 PM PDT 24
Peak memory 265284 kb
Host smart-7b197324-3814-41a7-93a0-e45e2263e0ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547171742 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1547171742
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.169186095
Short name T209
Test name
Test status
Simulation time 13055493800 ps
CPU time 139.28 seconds
Started Jun 13 03:22:17 PM PDT 24
Finished Jun 13 03:24:37 PM PDT 24
Peak memory 263096 kb
Host smart-8a2d8fbb-0ae1-497d-befe-7c5771e893ad
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169186095 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_mp_regions.169186095
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1333450222
Short name T983
Test name
Test status
Simulation time 47783600 ps
CPU time 131.56 seconds
Started Jun 13 03:22:10 PM PDT 24
Finished Jun 13 03:24:22 PM PDT 24
Peak memory 264252 kb
Host smart-86c77319-3749-4e42-bf29-280f24721ca1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333450222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1333450222
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1889279913
Short name T828
Test name
Test status
Simulation time 2841962800 ps
CPU time 330.7 seconds
Started Jun 13 03:22:10 PM PDT 24
Finished Jun 13 03:27:41 PM PDT 24
Peak memory 263424 kb
Host smart-21db02be-6e0f-4f5c-87a9-bd73bbdab2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889279913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1889279913
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3793873647
Short name T572
Test name
Test status
Simulation time 3510146700 ps
CPU time 138.85 seconds
Started Jun 13 03:22:17 PM PDT 24
Finished Jun 13 03:24:37 PM PDT 24
Peak memory 259900 kb
Host smart-262e4516-cff7-4837-bcf6-5f2be4c7b060
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793873647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3793873647
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.4240943361
Short name T348
Test name
Test status
Simulation time 124413000 ps
CPU time 38.1 seconds
Started Jun 13 03:22:21 PM PDT 24
Finished Jun 13 03:23:00 PM PDT 24
Peak memory 277164 kb
Host smart-a853f9a6-b643-4c92-854d-f6035f8a91b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240943361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.4240943361
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2067533523
Short name T629
Test name
Test status
Simulation time 1080678000 ps
CPU time 132.01 seconds
Started Jun 13 03:22:17 PM PDT 24
Finished Jun 13 03:24:30 PM PDT 24
Peak memory 282228 kb
Host smart-b91b4c91-1d34-405b-87fb-aa466b1d6255
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067533523 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.2067533523
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2053574348
Short name T871
Test name
Test status
Simulation time 15756721800 ps
CPU time 573.33 seconds
Started Jun 13 03:22:20 PM PDT 24
Finished Jun 13 03:31:54 PM PDT 24
Peak memory 314852 kb
Host smart-6da33936-562e-40a8-a24a-6842b71355e7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053574348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.2053574348
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.1695984575
Short name T30
Test name
Test status
Simulation time 32510300 ps
CPU time 30.97 seconds
Started Jun 13 03:22:16 PM PDT 24
Finished Jun 13 03:22:47 PM PDT 24
Peak memory 275844 kb
Host smart-5fd98f5b-4930-4378-9f7d-dd176a360d16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695984575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.1695984575
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1301987771
Short name T830
Test name
Test status
Simulation time 49157800 ps
CPU time 30.58 seconds
Started Jun 13 03:22:15 PM PDT 24
Finished Jun 13 03:22:46 PM PDT 24
Peak memory 267952 kb
Host smart-80583633-91df-46db-a949-d1136b81f296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301987771 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1301987771
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1487909161
Short name T769
Test name
Test status
Simulation time 744381800 ps
CPU time 77.75 seconds
Started Jun 13 03:22:22 PM PDT 24
Finished Jun 13 03:23:40 PM PDT 24
Peak memory 263908 kb
Host smart-712ecdc6-6820-4ecd-bf0a-71fba64fe823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487909161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1487909161
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.644106666
Short name T719
Test name
Test status
Simulation time 21571100 ps
CPU time 119.13 seconds
Started Jun 13 03:22:14 PM PDT 24
Finished Jun 13 03:24:13 PM PDT 24
Peak memory 277592 kb
Host smart-3407a0a6-7e6f-40b9-b5c8-25a111f3a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644106666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.644106666
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2845195736
Short name T899
Test name
Test status
Simulation time 6600146200 ps
CPU time 135.63 seconds
Started Jun 13 03:22:15 PM PDT 24
Finished Jun 13 03:24:31 PM PDT 24
Peak memory 260304 kb
Host smart-d931148c-7b5d-474d-a906-176f38d60104
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845195736 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.2845195736
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2162299832
Short name T82
Test name
Test status
Simulation time 79708900 ps
CPU time 13.85 seconds
Started Jun 13 03:22:45 PM PDT 24
Finished Jun 13 03:23:00 PM PDT 24
Peak memory 258748 kb
Host smart-6941d53a-bb88-4776-9f4e-2d43d0d3fb0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162299832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2162299832
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.1062778119
Short name T491
Test name
Test status
Simulation time 13880300 ps
CPU time 15.8 seconds
Started Jun 13 03:22:45 PM PDT 24
Finished Jun 13 03:23:01 PM PDT 24
Peak memory 275288 kb
Host smart-6712520a-0546-4c04-bc88-b8ba14a7697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062778119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1062778119
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3693241204
Short name T54
Test name
Test status
Simulation time 19463200 ps
CPU time 21.39 seconds
Started Jun 13 03:22:38 PM PDT 24
Finished Jun 13 03:23:00 PM PDT 24
Peak memory 274132 kb
Host smart-9f4987ff-ec4b-4bf9-93a5-5f2bd2249e69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693241204 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3693241204
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.168535298
Short name T162
Test name
Test status
Simulation time 10012038600 ps
CPU time 125.71 seconds
Started Jun 13 03:22:43 PM PDT 24
Finished Jun 13 03:24:49 PM PDT 24
Peak memory 330576 kb
Host smart-fb883f84-1a4e-4370-9ef6-90def807595e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168535298 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.168535298
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3777131930
Short name T445
Test name
Test status
Simulation time 15177600 ps
CPU time 13.36 seconds
Started Jun 13 03:22:44 PM PDT 24
Finished Jun 13 03:22:58 PM PDT 24
Peak memory 265276 kb
Host smart-c2eb5fda-2fcf-40a7-b753-57641f6d616e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777131930 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3777131930
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2725310885
Short name T796
Test name
Test status
Simulation time 8624957400 ps
CPU time 110.24 seconds
Started Jun 13 03:22:36 PM PDT 24
Finished Jun 13 03:24:27 PM PDT 24
Peak memory 261196 kb
Host smart-00397beb-8000-4d6c-90b4-c73c170aee04
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725310885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.2725310885
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.1322235451
Short name T701
Test name
Test status
Simulation time 505619700 ps
CPU time 120.26 seconds
Started Jun 13 03:22:33 PM PDT 24
Finished Jun 13 03:24:35 PM PDT 24
Peak memory 294448 kb
Host smart-1ca8d8c3-b9d5-40a7-b22d-d59d2ccb31fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322235451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.1322235451
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2433748093
Short name T313
Test name
Test status
Simulation time 195573434100 ps
CPU time 370.39 seconds
Started Jun 13 03:22:37 PM PDT 24
Finished Jun 13 03:28:48 PM PDT 24
Peak memory 292464 kb
Host smart-43118b8e-70da-4c4c-90d3-d83d199ea72c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433748093 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2433748093
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.734263039
Short name T990
Test name
Test status
Simulation time 1630490500 ps
CPU time 59.67 seconds
Started Jun 13 03:22:34 PM PDT 24
Finished Jun 13 03:23:35 PM PDT 24
Peak memory 260912 kb
Host smart-c45d5313-a69a-4c24-b29a-1fdfe5a0530d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734263039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.734263039
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.710470674
Short name T138
Test name
Test status
Simulation time 26157913800 ps
CPU time 505.8 seconds
Started Jun 13 03:22:32 PM PDT 24
Finished Jun 13 03:30:58 PM PDT 24
Peak memory 275028 kb
Host smart-77b64a3d-b090-4a0a-b009-f326ff020f3a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710470674 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.710470674
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2458116978
Short name T158
Test name
Test status
Simulation time 133176900 ps
CPU time 128.52 seconds
Started Jun 13 03:22:27 PM PDT 24
Finished Jun 13 03:24:37 PM PDT 24
Peak memory 265192 kb
Host smart-31cc33ad-5e8e-44c4-bdba-4274cab3c7bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458116978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2458116978
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.1332047621
Short name T698
Test name
Test status
Simulation time 96522900 ps
CPU time 444.13 seconds
Started Jun 13 03:22:36 PM PDT 24
Finished Jun 13 03:30:01 PM PDT 24
Peak memory 263536 kb
Host smart-3aadad6e-6e5b-41ab-9e4f-187541661458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332047621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.1332047621
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.1234941048
Short name T784
Test name
Test status
Simulation time 32459200 ps
CPU time 13.55 seconds
Started Jun 13 03:22:39 PM PDT 24
Finished Jun 13 03:22:53 PM PDT 24
Peak memory 259028 kb
Host smart-98a51d30-7293-4409-b4d5-4cd0afd61724
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234941048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.1234941048
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.2382825837
Short name T141
Test name
Test status
Simulation time 502398100 ps
CPU time 868.86 seconds
Started Jun 13 03:22:30 PM PDT 24
Finished Jun 13 03:36:59 PM PDT 24
Peak memory 286028 kb
Host smart-cc1c3570-b6d1-4d48-9165-7601e7c2c6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382825837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2382825837
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3665294817
Short name T895
Test name
Test status
Simulation time 284985500 ps
CPU time 35.45 seconds
Started Jun 13 03:22:39 PM PDT 24
Finished Jun 13 03:23:15 PM PDT 24
Peak memory 270684 kb
Host smart-f6ff754f-7560-4391-bbb4-f8025c5e34e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665294817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3665294817
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.2211049230
Short name T844
Test name
Test status
Simulation time 2111618200 ps
CPU time 99.3 seconds
Started Jun 13 03:22:33 PM PDT 24
Finished Jun 13 03:24:14 PM PDT 24
Peak memory 289728 kb
Host smart-1c600898-612f-4a23-a016-6c81190d5e7b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211049230 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.2211049230
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3299171985
Short name T444
Test name
Test status
Simulation time 4171939900 ps
CPU time 638.66 seconds
Started Jun 13 03:22:34 PM PDT 24
Finished Jun 13 03:33:14 PM PDT 24
Peak memory 310200 kb
Host smart-d1fd5858-f25f-48b0-93f0-bb9d3bfd8c38
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299171985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.3299171985
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.4100371805
Short name T29
Test name
Test status
Simulation time 30318700 ps
CPU time 30.35 seconds
Started Jun 13 03:22:39 PM PDT 24
Finished Jun 13 03:23:10 PM PDT 24
Peak memory 275760 kb
Host smart-23698e7a-a26e-4bbc-a2d2-5a84f6d465e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100371805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.4100371805
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.368713289
Short name T326
Test name
Test status
Simulation time 31718400 ps
CPU time 31.63 seconds
Started Jun 13 03:22:37 PM PDT 24
Finished Jun 13 03:23:09 PM PDT 24
Peak memory 267932 kb
Host smart-f99e75cb-b275-4580-a658-7bec2de5661d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368713289 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.368713289
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.810568776
Short name T979
Test name
Test status
Simulation time 59693500 ps
CPU time 96.78 seconds
Started Jun 13 03:22:34 PM PDT 24
Finished Jun 13 03:24:12 PM PDT 24
Peak memory 277120 kb
Host smart-fa289fb3-bc6c-45f0-9b90-78d63a8243be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810568776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.810568776
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.24239440
Short name T234
Test name
Test status
Simulation time 7223473100 ps
CPU time 209.91 seconds
Started Jun 13 03:22:33 PM PDT 24
Finished Jun 13 03:26:03 PM PDT 24
Peak memory 265660 kb
Host smart-560a56fb-e391-454b-af71-6d8c2734ccd5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24239440 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_wo.24239440
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.2449748583
Short name T432
Test name
Test status
Simulation time 182732100 ps
CPU time 13.8 seconds
Started Jun 13 03:23:07 PM PDT 24
Finished Jun 13 03:23:22 PM PDT 24
Peak memory 258624 kb
Host smart-73b26ed3-5742-474d-8a62-6f1dc12809e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449748583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
2449748583
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.318806558
Short name T780
Test name
Test status
Simulation time 16179600 ps
CPU time 15.58 seconds
Started Jun 13 03:23:04 PM PDT 24
Finished Jun 13 03:23:20 PM PDT 24
Peak memory 284652 kb
Host smart-75069132-5898-40ce-8188-93cb01546f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318806558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.318806558
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3327280816
Short name T972
Test name
Test status
Simulation time 53012400 ps
CPU time 21.77 seconds
Started Jun 13 03:23:04 PM PDT 24
Finished Jun 13 03:23:26 PM PDT 24
Peak memory 265328 kb
Host smart-f83a5e90-ceed-4a29-aeaa-adda76baac97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327280816 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3327280816
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.801760889
Short name T943
Test name
Test status
Simulation time 10012578200 ps
CPU time 110.08 seconds
Started Jun 13 03:23:01 PM PDT 24
Finished Jun 13 03:24:52 PM PDT 24
Peak memory 305644 kb
Host smart-133d1423-635a-437c-b23d-b3c06526e5b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801760889 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.801760889
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2375404113
Short name T874
Test name
Test status
Simulation time 15616800 ps
CPU time 13.69 seconds
Started Jun 13 03:23:00 PM PDT 24
Finished Jun 13 03:23:15 PM PDT 24
Peak memory 265828 kb
Host smart-0896eb53-a093-4a11-8a17-69f1a3782389
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375404113 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2375404113
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2113207650
Short name T146
Test name
Test status
Simulation time 170183110000 ps
CPU time 1021.66 seconds
Started Jun 13 03:22:50 PM PDT 24
Finished Jun 13 03:39:52 PM PDT 24
Peak memory 264876 kb
Host smart-d51ba7bd-a973-48f4-804d-50505bce8aa2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113207650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2113207650
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.3652546053
Short name T884
Test name
Test status
Simulation time 1423249600 ps
CPU time 73.36 seconds
Started Jun 13 03:22:50 PM PDT 24
Finished Jun 13 03:24:04 PM PDT 24
Peak memory 263416 kb
Host smart-3e96132b-8f63-47e4-9788-8333cb3d6c06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652546053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.3652546053
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1142415135
Short name T381
Test name
Test status
Simulation time 12376913400 ps
CPU time 223.35 seconds
Started Jun 13 03:22:58 PM PDT 24
Finished Jun 13 03:26:41 PM PDT 24
Peak memory 291520 kb
Host smart-1a46ad98-182d-4888-8cf2-090ee1f6a881
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142415135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1142415135
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1916769470
Short name T786
Test name
Test status
Simulation time 58198838900 ps
CPU time 359.03 seconds
Started Jun 13 03:22:57 PM PDT 24
Finished Jun 13 03:28:56 PM PDT 24
Peak memory 285248 kb
Host smart-b9830e85-f52f-44dd-9471-806dc6b4503b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916769470 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1916769470
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1193205213
Short name T602
Test name
Test status
Simulation time 976768200 ps
CPU time 78.95 seconds
Started Jun 13 03:22:50 PM PDT 24
Finished Jun 13 03:24:10 PM PDT 24
Peak memory 263584 kb
Host smart-2de7439e-d1a3-40cb-863d-aa37a8413c98
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193205213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
193205213
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.1918151001
Short name T873
Test name
Test status
Simulation time 23469100 ps
CPU time 13.71 seconds
Started Jun 13 03:23:02 PM PDT 24
Finished Jun 13 03:23:16 PM PDT 24
Peak memory 265364 kb
Host smart-65406ed6-7ab7-4180-a62e-70e66facd338
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918151001 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.1918151001
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.3427365898
Short name T116
Test name
Test status
Simulation time 22501961000 ps
CPU time 738.72 seconds
Started Jun 13 03:22:52 PM PDT 24
Finished Jun 13 03:35:11 PM PDT 24
Peak memory 274496 kb
Host smart-4fe2dbee-e9f9-4a07-a704-b504e1f2d8e0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427365898 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.3427365898
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3889147873
Short name T611
Test name
Test status
Simulation time 37377700 ps
CPU time 132.66 seconds
Started Jun 13 03:22:51 PM PDT 24
Finished Jun 13 03:25:04 PM PDT 24
Peak memory 260764 kb
Host smart-878816a8-dc8b-4776-a59d-dd6d3c5c61b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889147873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3889147873
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.2314697984
Short name T720
Test name
Test status
Simulation time 828368600 ps
CPU time 502.47 seconds
Started Jun 13 03:22:50 PM PDT 24
Finished Jun 13 03:31:14 PM PDT 24
Peak memory 263448 kb
Host smart-a3a12537-a42a-4451-a0fe-d95712ffa6cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314697984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2314697984
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.876252778
Short name T551
Test name
Test status
Simulation time 55069700 ps
CPU time 13.9 seconds
Started Jun 13 03:22:54 PM PDT 24
Finished Jun 13 03:23:09 PM PDT 24
Peak memory 265752 kb
Host smart-fe595821-e243-4542-a00b-7bfce3408b07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876252778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.876252778
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.2278196876
Short name T139
Test name
Test status
Simulation time 570268000 ps
CPU time 1235.55 seconds
Started Jun 13 03:22:46 PM PDT 24
Finished Jun 13 03:43:22 PM PDT 24
Peak memory 289848 kb
Host smart-d432b171-d190-46a9-8ea4-3bea2ad31c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278196876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.2278196876
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3933281086
Short name T837
Test name
Test status
Simulation time 202866500 ps
CPU time 34.86 seconds
Started Jun 13 03:22:55 PM PDT 24
Finished Jun 13 03:23:31 PM PDT 24
Peak memory 277168 kb
Host smart-1f126e7a-0d0a-4b08-9e9b-67c1b0c9dec6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933281086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3933281086
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.666714041
Short name T918
Test name
Test status
Simulation time 1991803700 ps
CPU time 117.35 seconds
Started Jun 13 03:22:56 PM PDT 24
Finished Jun 13 03:24:54 PM PDT 24
Peak memory 282284 kb
Host smart-eb5833f7-0c02-4b1f-9a63-b32412ac855f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666714041 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.flash_ctrl_ro.666714041
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1492341528
Short name T730
Test name
Test status
Simulation time 44863400 ps
CPU time 30.79 seconds
Started Jun 13 03:22:55 PM PDT 24
Finished Jun 13 03:23:26 PM PDT 24
Peak memory 275856 kb
Host smart-96e4f0ab-ed65-416f-952f-c03f944c52fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492341528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1492341528
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.1723766320
Short name T467
Test name
Test status
Simulation time 26815000 ps
CPU time 28.5 seconds
Started Jun 13 03:22:57 PM PDT 24
Finished Jun 13 03:23:26 PM PDT 24
Peak memory 267960 kb
Host smart-53713ba8-60c6-4168-bb3e-b5fa3c059e96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723766320 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.1723766320
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3014557690
Short name T182
Test name
Test status
Simulation time 10100311300 ps
CPU time 70.67 seconds
Started Jun 13 03:23:03 PM PDT 24
Finished Jun 13 03:24:14 PM PDT 24
Peak memory 263452 kb
Host smart-df639cfa-b2c0-4e55-8fa1-2d4a7d3a073c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014557690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3014557690
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.2591591092
Short name T527
Test name
Test status
Simulation time 27962100 ps
CPU time 98.99 seconds
Started Jun 13 03:22:44 PM PDT 24
Finished Jun 13 03:24:24 PM PDT 24
Peak memory 277256 kb
Host smart-8f3212ad-9206-4dcc-949c-7a4ec3edcdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591591092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2591591092
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1777920452
Short name T625
Test name
Test status
Simulation time 6042178200 ps
CPU time 215.01 seconds
Started Jun 13 03:22:57 PM PDT 24
Finished Jun 13 03:26:33 PM PDT 24
Peak memory 265740 kb
Host smart-2179607b-cacb-4851-81ff-cfd2cf9959e8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777920452 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.1777920452
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3874722031
Short name T584
Test name
Test status
Simulation time 71833400 ps
CPU time 13.58 seconds
Started Jun 13 03:23:24 PM PDT 24
Finished Jun 13 03:23:39 PM PDT 24
Peak memory 265744 kb
Host smart-aba1ce1f-73ad-42fb-a2a2-1b16027fcc5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874722031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3874722031
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.4290199360
Short name T425
Test name
Test status
Simulation time 51521900 ps
CPU time 13.28 seconds
Started Jun 13 03:23:22 PM PDT 24
Finished Jun 13 03:23:37 PM PDT 24
Peak memory 275192 kb
Host smart-9bc37e4a-f8b2-4681-abf9-e7593dfd79b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290199360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.4290199360
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.1484799070
Short name T568
Test name
Test status
Simulation time 17881400 ps
CPU time 21.96 seconds
Started Jun 13 03:23:20 PM PDT 24
Finished Jun 13 03:23:43 PM PDT 24
Peak memory 274128 kb
Host smart-ea29821f-6b46-4dc5-a9f3-e810e7569eb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484799070 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.1484799070
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3739516604
Short name T1017
Test name
Test status
Simulation time 10013828100 ps
CPU time 87.31 seconds
Started Jun 13 03:23:22 PM PDT 24
Finished Jun 13 03:24:51 PM PDT 24
Peak memory 281072 kb
Host smart-1b06d64d-3a23-4581-aa0b-df7b776fda3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739516604 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3739516604
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2929690280
Short name T268
Test name
Test status
Simulation time 15143400 ps
CPU time 13.47 seconds
Started Jun 13 03:23:22 PM PDT 24
Finished Jun 13 03:23:37 PM PDT 24
Peak memory 258928 kb
Host smart-e963cffb-c71e-4bec-a740-999605d08d92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929690280 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2929690280
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.1542498770
Short name T1006
Test name
Test status
Simulation time 40123258000 ps
CPU time 856.25 seconds
Started Jun 13 03:23:06 PM PDT 24
Finished Jun 13 03:37:23 PM PDT 24
Peak memory 264812 kb
Host smart-ffb7e252-0b25-4c2b-918c-de943e4945c4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542498770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.1542498770
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2976082193
Short name T546
Test name
Test status
Simulation time 2911711900 ps
CPU time 92.52 seconds
Started Jun 13 03:23:10 PM PDT 24
Finished Jun 13 03:24:44 PM PDT 24
Peak memory 263512 kb
Host smart-1f66e251-98ac-4cbf-afc1-1d8a9e55bebe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976082193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2976082193
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.3596767846
Short name T1018
Test name
Test status
Simulation time 2144287900 ps
CPU time 172.92 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:26:10 PM PDT 24
Peak memory 294596 kb
Host smart-c59275d5-54ba-48c3-ab6b-10aea39a483b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596767846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.3596767846
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.1844153151
Short name T77
Test name
Test status
Simulation time 13086226200 ps
CPU time 340.99 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:28:57 PM PDT 24
Peak memory 293444 kb
Host smart-a461c233-7455-437a-a391-61513d609faf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844153151 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.1844153151
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1067532616
Short name T385
Test name
Test status
Simulation time 3270527200 ps
CPU time 65.71 seconds
Started Jun 13 03:23:14 PM PDT 24
Finished Jun 13 03:24:20 PM PDT 24
Peak memory 263532 kb
Host smart-e7b82662-1d1b-4c61-a8db-42a984855f58
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067532616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
067532616
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3564105221
Short name T534
Test name
Test status
Simulation time 15768100 ps
CPU time 13.73 seconds
Started Jun 13 03:23:22 PM PDT 24
Finished Jun 13 03:23:38 PM PDT 24
Peak memory 265888 kb
Host smart-f89ebc9b-70cc-4dd2-8975-6ce9e4165fa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564105221 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3564105221
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3880265464
Short name T892
Test name
Test status
Simulation time 10911838700 ps
CPU time 256.24 seconds
Started Jun 13 03:23:17 PM PDT 24
Finished Jun 13 03:27:34 PM PDT 24
Peak memory 274656 kb
Host smart-98d3ba66-f5a3-4787-baf9-613b2afca504
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880265464 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3880265464
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.3226391661
Short name T891
Test name
Test status
Simulation time 1696441000 ps
CPU time 385.55 seconds
Started Jun 13 03:23:09 PM PDT 24
Finished Jun 13 03:29:35 PM PDT 24
Peak memory 263464 kb
Host smart-5b6738ac-8c7b-40c2-90c0-4c77215e348b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226391661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.3226391661
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.1673188843
Short name T512
Test name
Test status
Simulation time 32653000 ps
CPU time 13.6 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:23:30 PM PDT 24
Peak memory 259244 kb
Host smart-d65ba949-5dfa-4360-89fa-9b25d14b2134
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673188843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.1673188843
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3260932913
Short name T129
Test name
Test status
Simulation time 3705415800 ps
CPU time 1500.4 seconds
Started Jun 13 03:23:09 PM PDT 24
Finished Jun 13 03:48:11 PM PDT 24
Peak memory 286780 kb
Host smart-06c40e40-6b03-4067-96d5-5b420e836417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260932913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3260932913
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1513527389
Short name T511
Test name
Test status
Simulation time 78965300 ps
CPU time 35.25 seconds
Started Jun 13 03:23:18 PM PDT 24
Finished Jun 13 03:23:53 PM PDT 24
Peak memory 277820 kb
Host smart-83a2b5be-bf9d-4fec-a6de-ed513b5dc866
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513527389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1513527389
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2400787556
Short name T438
Test name
Test status
Simulation time 2037745900 ps
CPU time 111.85 seconds
Started Jun 13 03:23:17 PM PDT 24
Finished Jun 13 03:25:09 PM PDT 24
Peak memory 282164 kb
Host smart-f5aca713-03f5-4a8a-b9b6-ceaf3a42a492
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400787556 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2400787556
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.3594693913
Short name T752
Test name
Test status
Simulation time 16511061500 ps
CPU time 776.69 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:36:14 PM PDT 24
Peak memory 318208 kb
Host smart-d321e798-8d7e-47e2-b772-e3c7df2368c0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594693913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.3594693913
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.3723945275
Short name T665
Test name
Test status
Simulation time 29224300 ps
CPU time 31.03 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:23:48 PM PDT 24
Peak memory 277704 kb
Host smart-f7369902-de1c-4599-a9ab-f5317ca7d231
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723945275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.3723945275
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.187027574
Short name T1087
Test name
Test status
Simulation time 43837500 ps
CPU time 30.81 seconds
Started Jun 13 03:23:17 PM PDT 24
Finished Jun 13 03:23:48 PM PDT 24
Peak memory 275372 kb
Host smart-d81254b3-abbc-4493-a185-09706cd9b03e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187027574 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.187027574
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.989159851
Short name T993
Test name
Test status
Simulation time 7573928600 ps
CPU time 180.29 seconds
Started Jun 13 03:23:09 PM PDT 24
Finished Jun 13 03:26:10 PM PDT 24
Peak memory 282032 kb
Host smart-30158585-5911-4f34-9db9-1a0ca5553eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989159851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.989159851
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.318951186
Short name T501
Test name
Test status
Simulation time 11028661400 ps
CPU time 230.13 seconds
Started Jun 13 03:23:16 PM PDT 24
Finished Jun 13 03:27:07 PM PDT 24
Peak memory 259708 kb
Host smart-50cb4891-efb4-44d5-bcbb-f116f0355209
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318951186 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.318951186
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3641686608
Short name T440
Test name
Test status
Simulation time 96048000 ps
CPU time 13.78 seconds
Started Jun 13 03:23:37 PM PDT 24
Finished Jun 13 03:23:52 PM PDT 24
Peak memory 265604 kb
Host smart-23e26fe7-9b6e-4a84-9b9e-679d43c40a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641686608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3641686608
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2140137613
Short name T1058
Test name
Test status
Simulation time 45163700 ps
CPU time 16.06 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:23:50 PM PDT 24
Peak memory 275328 kb
Host smart-78044e23-12f1-42df-ad3d-2cea3735435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140137613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2140137613
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2097570672
Short name T1005
Test name
Test status
Simulation time 15010300 ps
CPU time 21.74 seconds
Started Jun 13 03:23:34 PM PDT 24
Finished Jun 13 03:23:58 PM PDT 24
Peak memory 265944 kb
Host smart-d819a15e-bcd4-46a1-8441-db457cce13b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097570672 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2097570672
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3836133372
Short name T273
Test name
Test status
Simulation time 10051871400 ps
CPU time 71.23 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:24:56 PM PDT 24
Peak memory 266960 kb
Host smart-9e31eec7-2579-40f2-8b5d-50951129c030
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836133372 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3836133372
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.105189143
Short name T214
Test name
Test status
Simulation time 15999600 ps
CPU time 13.47 seconds
Started Jun 13 03:23:39 PM PDT 24
Finished Jun 13 03:23:53 PM PDT 24
Peak memory 265328 kb
Host smart-bbad1118-1197-4b81-b282-9254455dbe39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105189143 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.105189143
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1340399366
Short name T856
Test name
Test status
Simulation time 40127141700 ps
CPU time 978.21 seconds
Started Jun 13 03:23:28 PM PDT 24
Finished Jun 13 03:39:49 PM PDT 24
Peak memory 265560 kb
Host smart-cc335640-8c16-424e-96fc-37d2b07515ab
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340399366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1340399366
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.105229706
Short name T961
Test name
Test status
Simulation time 1933857600 ps
CPU time 42.45 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:24:18 PM PDT 24
Peak memory 263076 kb
Host smart-96a769af-310b-4bcc-ad43-28823893cfe8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105229706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_h
w_sec_otp.105229706
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2342026997
Short name T1036
Test name
Test status
Simulation time 5815622300 ps
CPU time 131.18 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:25:46 PM PDT 24
Peak memory 293408 kb
Host smart-1e05b0e6-629c-4d56-a7c4-98b9327055dc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342026997 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2342026997
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.2029189474
Short name T1067
Test name
Test status
Simulation time 2494635500 ps
CPU time 89.21 seconds
Started Jun 13 03:23:29 PM PDT 24
Finished Jun 13 03:25:00 PM PDT 24
Peak memory 260820 kb
Host smart-2a9f8de1-1927-48ca-8c37-7030b8a54103
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029189474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2
029189474
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1251462100
Short name T735
Test name
Test status
Simulation time 15017200 ps
CPU time 13.69 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:23:46 PM PDT 24
Peak memory 260244 kb
Host smart-0fa2fff1-0c8c-4970-82bc-dfae43261fa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251462100 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1251462100
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.3624410240
Short name T1031
Test name
Test status
Simulation time 99663935300 ps
CPU time 572.69 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:33:08 PM PDT 24
Peak memory 274784 kb
Host smart-36beb0b1-9e87-46a3-a457-7e0301b5652f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624410240 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.3624410240
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1317267697
Short name T356
Test name
Test status
Simulation time 145646200 ps
CPU time 130.29 seconds
Started Jun 13 03:23:30 PM PDT 24
Finished Jun 13 03:25:42 PM PDT 24
Peak memory 260476 kb
Host smart-5ad72c6c-f9d9-467a-8caa-fc48d167690f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317267697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1317267697
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.4202066030
Short name T1001
Test name
Test status
Simulation time 139097200 ps
CPU time 153.18 seconds
Started Jun 13 03:23:24 PM PDT 24
Finished Jun 13 03:25:59 PM PDT 24
Peak memory 263556 kb
Host smart-02a83dd5-be09-4649-bfd1-7497767807fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202066030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.4202066030
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1063863064
Short name T576
Test name
Test status
Simulation time 55444300 ps
CPU time 198 seconds
Started Jun 13 03:23:23 PM PDT 24
Finished Jun 13 03:26:43 PM PDT 24
Peak memory 281216 kb
Host smart-e289f6a1-8f4e-4dec-a9a5-a2ed69cba48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063863064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1063863064
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.4043904490
Short name T619
Test name
Test status
Simulation time 470322400 ps
CPU time 34.94 seconds
Started Jun 13 03:23:40 PM PDT 24
Finished Jun 13 03:24:16 PM PDT 24
Peak memory 270580 kb
Host smart-57e6d759-d3f7-407b-9558-cf7942248ded
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043904490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.4043904490
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2262641649
Short name T76
Test name
Test status
Simulation time 643403000 ps
CPU time 126.77 seconds
Started Jun 13 03:23:28 PM PDT 24
Finished Jun 13 03:25:37 PM PDT 24
Peak memory 282268 kb
Host smart-7e60f7eb-b70f-462b-8eb8-0afa2ca3cc16
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262641649 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2262641649
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.1401839828
Short name T869
Test name
Test status
Simulation time 45561300 ps
CPU time 30.62 seconds
Started Jun 13 03:23:34 PM PDT 24
Finished Jun 13 03:24:07 PM PDT 24
Peak memory 275392 kb
Host smart-1ec0674a-ab92-4e26-8ac2-09280974a22e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401839828 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.1401839828
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.1375504347
Short name T987
Test name
Test status
Simulation time 1467507500 ps
CPU time 68.05 seconds
Started Jun 13 03:23:34 PM PDT 24
Finished Jun 13 03:24:44 PM PDT 24
Peak memory 264008 kb
Host smart-40ae9947-dc90-408c-b3cd-be8e5204b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375504347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.1375504347
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3123615459
Short name T424
Test name
Test status
Simulation time 25627600 ps
CPU time 98.49 seconds
Started Jun 13 03:23:21 PM PDT 24
Finished Jun 13 03:25:00 PM PDT 24
Peak memory 276076 kb
Host smart-37d265bd-d893-4987-b634-9d41fb01bb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123615459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3123615459
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2956909045
Short name T486
Test name
Test status
Simulation time 3915049600 ps
CPU time 140.63 seconds
Started Jun 13 03:23:32 PM PDT 24
Finished Jun 13 03:25:56 PM PDT 24
Peak memory 265588 kb
Host smart-a30c1bbc-d860-4f65-a645-a8f59ce519d6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956909045 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.2956909045
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.2865769537
Short name T885
Test name
Test status
Simulation time 43098300 ps
CPU time 13.41 seconds
Started Jun 13 03:24:12 PM PDT 24
Finished Jun 13 03:24:27 PM PDT 24
Peak memory 258736 kb
Host smart-50967228-8b17-4a3b-9052-235d72bf5a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865769537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
2865769537
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2667208041
Short name T397
Test name
Test status
Simulation time 14416000 ps
CPU time 16.12 seconds
Started Jun 13 03:23:52 PM PDT 24
Finished Jun 13 03:24:09 PM PDT 24
Peak memory 284572 kb
Host smart-4592e747-853d-4bf5-bed1-e6f1556830a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667208041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2667208041
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.245439417
Short name T343
Test name
Test status
Simulation time 43351600 ps
CPU time 22.17 seconds
Started Jun 13 03:23:50 PM PDT 24
Finished Jun 13 03:24:12 PM PDT 24
Peak memory 274156 kb
Host smart-2dc8e1dd-47d7-4eb0-85cf-8bb59b21e0fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245439417 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.245439417
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.2355285294
Short name T151
Test name
Test status
Simulation time 10012036100 ps
CPU time 318.32 seconds
Started Jun 13 03:24:07 PM PDT 24
Finished Jun 13 03:29:27 PM PDT 24
Peak memory 291784 kb
Host smart-01ec381e-04c7-490b-b26e-220263a2accb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355285294 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.2355285294
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3930774506
Short name T850
Test name
Test status
Simulation time 46699500 ps
CPU time 13.33 seconds
Started Jun 13 03:24:09 PM PDT 24
Finished Jun 13 03:24:24 PM PDT 24
Peak memory 265808 kb
Host smart-32a0f35a-bd71-4a63-b036-e8329f2546e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930774506 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3930774506
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3633095770
Short name T175
Test name
Test status
Simulation time 40127933700 ps
CPU time 914.99 seconds
Started Jun 13 03:23:40 PM PDT 24
Finished Jun 13 03:38:55 PM PDT 24
Peak memory 264720 kb
Host smart-27b37166-95dd-4baa-a0c8-b411e0df7232
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633095770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.3633095770
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1303023211
Short name T448
Test name
Test status
Simulation time 5621525800 ps
CPU time 96.03 seconds
Started Jun 13 03:23:38 PM PDT 24
Finished Jun 13 03:25:15 PM PDT 24
Peak memory 261276 kb
Host smart-d6437fe2-395e-4acc-ac48-c9be8a3d535b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303023211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1303023211
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2248420061
Short name T833
Test name
Test status
Simulation time 749204900 ps
CPU time 222.15 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:27:27 PM PDT 24
Peak memory 293988 kb
Host smart-055957a7-182c-4127-af11-1f154160e0dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248420061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2248420061
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2257656073
Short name T525
Test name
Test status
Simulation time 29974541100 ps
CPU time 169.15 seconds
Started Jun 13 03:23:45 PM PDT 24
Finished Jun 13 03:26:35 PM PDT 24
Peak memory 293472 kb
Host smart-d8a53ddd-c679-46bf-8c24-7ff87608b2dd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257656073 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2257656073
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.118389904
Short name T384
Test name
Test status
Simulation time 6531284000 ps
CPU time 61.2 seconds
Started Jun 13 03:23:39 PM PDT 24
Finished Jun 13 03:24:41 PM PDT 24
Peak memory 263676 kb
Host smart-0c7ba73a-e04c-4655-8ded-11ecf6e03c43
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118389904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.118389904
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1257255092
Short name T1050
Test name
Test status
Simulation time 44442100 ps
CPU time 13.32 seconds
Started Jun 13 03:23:51 PM PDT 24
Finished Jun 13 03:24:05 PM PDT 24
Peak memory 260352 kb
Host smart-70109e75-b0dc-454b-9a20-f6ef0b30cbcd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257255092 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1257255092
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.4146479831
Short name T1057
Test name
Test status
Simulation time 17255793000 ps
CPU time 251.98 seconds
Started Jun 13 03:23:41 PM PDT 24
Finished Jun 13 03:27:54 PM PDT 24
Peak memory 274972 kb
Host smart-c81af276-4d94-47d6-afc2-77f3a667f39c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146479831 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.4146479831
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3544728737
Short name T755
Test name
Test status
Simulation time 42819300 ps
CPU time 130.41 seconds
Started Jun 13 03:23:38 PM PDT 24
Finished Jun 13 03:25:50 PM PDT 24
Peak memory 260684 kb
Host smart-386fe156-3617-49eb-aabc-4b37e0ffcebc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544728737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3544728737
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.3422901335
Short name T517
Test name
Test status
Simulation time 678385900 ps
CPU time 127.19 seconds
Started Jun 13 03:23:38 PM PDT 24
Finished Jun 13 03:25:46 PM PDT 24
Peak memory 263436 kb
Host smart-8b755fee-7857-45e7-b12c-c27c40c9b0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422901335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3422901335
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2536253269
Short name T614
Test name
Test status
Simulation time 32195000 ps
CPU time 13.78 seconds
Started Jun 13 03:23:45 PM PDT 24
Finished Jun 13 03:23:59 PM PDT 24
Peak memory 265268 kb
Host smart-d151ec68-dc51-4c96-8b77-2579e6a10871
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536253269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2536253269
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1052350004
Short name T601
Test name
Test status
Simulation time 52898400 ps
CPU time 219.48 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:27:24 PM PDT 24
Peak memory 280892 kb
Host smart-e01559e9-8493-4b61-94c2-9beb28d4cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052350004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1052350004
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.467517293
Short name T31
Test name
Test status
Simulation time 155303400 ps
CPU time 33.83 seconds
Started Jun 13 03:23:49 PM PDT 24
Finished Jun 13 03:24:23 PM PDT 24
Peak memory 275868 kb
Host smart-3b569f9e-d375-4388-aafb-0afe17f1020f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467517293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.467517293
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3019633177
Short name T988
Test name
Test status
Simulation time 611128200 ps
CPU time 127.06 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:25:52 PM PDT 24
Peak memory 291964 kb
Host smart-62d89417-8a82-473d-902b-940c17ddda76
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019633177 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.3019633177
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.906795280
Short name T183
Test name
Test status
Simulation time 3867861900 ps
CPU time 638.77 seconds
Started Jun 13 03:23:43 PM PDT 24
Finished Jun 13 03:34:22 PM PDT 24
Peak memory 310248 kb
Host smart-a8e3ff84-a6fe-4d0f-89dd-ee6ee3a606ab
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906795280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_rw.906795280
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2185958418
Short name T437
Test name
Test status
Simulation time 78786100 ps
CPU time 31.03 seconds
Started Jun 13 03:23:51 PM PDT 24
Finished Jun 13 03:24:22 PM PDT 24
Peak memory 275352 kb
Host smart-d5f2df7d-657a-4850-9da8-e7e90c406841
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185958418 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2185958418
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1350911489
Short name T420
Test name
Test status
Simulation time 12066562300 ps
CPU time 63.63 seconds
Started Jun 13 03:23:52 PM PDT 24
Finished Jun 13 03:24:56 PM PDT 24
Peak memory 263132 kb
Host smart-34f96f8c-18ed-4787-a2b4-f79a03e46c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350911489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1350911489
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1810385338
Short name T715
Test name
Test status
Simulation time 47786800 ps
CPU time 145.24 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:26:10 PM PDT 24
Peak memory 278560 kb
Host smart-3934e19f-c2cc-411f-b826-bbbe2a7ce442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810385338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1810385338
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.1361704445
Short name T549
Test name
Test status
Simulation time 4640911600 ps
CPU time 201.9 seconds
Started Jun 13 03:23:44 PM PDT 24
Finished Jun 13 03:27:07 PM PDT 24
Peak memory 261388 kb
Host smart-098de7aa-95e6-453d-adeb-3348a2d22844
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361704445 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.1361704445
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3617188560
Short name T540
Test name
Test status
Simulation time 42286800 ps
CPU time 13.48 seconds
Started Jun 13 03:24:08 PM PDT 24
Finished Jun 13 03:24:23 PM PDT 24
Peak memory 265740 kb
Host smart-d7b30a1f-9899-41c6-8310-c4b5e3d625b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617188560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3617188560
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.332126827
Short name T697
Test name
Test status
Simulation time 16755100 ps
CPU time 15.84 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:24:28 PM PDT 24
Peak memory 284440 kb
Host smart-0e74af57-3af5-4ba3-9c85-1b31ed47d2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332126827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.332126827
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.921177394
Short name T759
Test name
Test status
Simulation time 15528100 ps
CPU time 21.55 seconds
Started Jun 13 03:24:15 PM PDT 24
Finished Jun 13 03:24:38 PM PDT 24
Peak memory 265780 kb
Host smart-5ec879a3-840a-465f-ad42-1e3f3abea63d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921177394 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.921177394
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.488676348
Short name T903
Test name
Test status
Simulation time 10017962700 ps
CPU time 180.75 seconds
Started Jun 13 03:24:09 PM PDT 24
Finished Jun 13 03:27:11 PM PDT 24
Peak memory 277128 kb
Host smart-526b2c4d-78e3-40ad-9880-69788386805c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488676348 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.488676348
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3813836364
Short name T761
Test name
Test status
Simulation time 47641700 ps
CPU time 13.62 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:24:26 PM PDT 24
Peak memory 259764 kb
Host smart-5bfc9e91-1c4c-4b63-9ecf-7b092b2698fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813836364 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3813836364
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1793892098
Short name T1076
Test name
Test status
Simulation time 270248078900 ps
CPU time 1086.05 seconds
Started Jun 13 03:24:09 PM PDT 24
Finished Jun 13 03:42:17 PM PDT 24
Peak memory 265476 kb
Host smart-f4689b37-eed9-4633-820d-dec2311a5495
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793892098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1793892098
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.152570874
Short name T294
Test name
Test status
Simulation time 1186211900 ps
CPU time 106.06 seconds
Started Jun 13 03:24:06 PM PDT 24
Finished Jun 13 03:25:53 PM PDT 24
Peak memory 263568 kb
Host smart-d47a4f19-2e74-4b5f-8307-b012a3d0daea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152570874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_h
w_sec_otp.152570874
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.3248735225
Short name T661
Test name
Test status
Simulation time 736659400 ps
CPU time 133.29 seconds
Started Jun 13 03:24:15 PM PDT 24
Finished Jun 13 03:26:30 PM PDT 24
Peak memory 291724 kb
Host smart-1a58dd1f-4b40-426d-84f4-7b62e813a994
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248735225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.3248735225
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3117443376
Short name T307
Test name
Test status
Simulation time 25936805800 ps
CPU time 358.51 seconds
Started Jun 13 03:24:11 PM PDT 24
Finished Jun 13 03:30:12 PM PDT 24
Peak memory 285276 kb
Host smart-d41216ec-456f-4be0-bb3e-4fd01f49604b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117443376 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3117443376
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.492051525
Short name T1007
Test name
Test status
Simulation time 2168480600 ps
CPU time 99.27 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:25:51 PM PDT 24
Peak memory 260860 kb
Host smart-5dcfb824-59d2-42cf-ab1c-ffd1827e78cb
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492051525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.492051525
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.338923921
Short name T762
Test name
Test status
Simulation time 25169600 ps
CPU time 13.39 seconds
Started Jun 13 03:24:07 PM PDT 24
Finished Jun 13 03:24:21 PM PDT 24
Peak memory 260368 kb
Host smart-bd91c4c2-6a21-4e2f-a228-0484ffec4abd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338923921 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.338923921
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.4047393445
Short name T135
Test name
Test status
Simulation time 28524625700 ps
CPU time 237.1 seconds
Started Jun 13 03:24:08 PM PDT 24
Finished Jun 13 03:28:07 PM PDT 24
Peak memory 274156 kb
Host smart-75dad8aa-4e01-4bb6-b759-63c67ee4c857
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047393445 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.4047393445
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1116011835
Short name T909
Test name
Test status
Simulation time 45227800 ps
CPU time 193.17 seconds
Started Jun 13 03:24:24 PM PDT 24
Finished Jun 13 03:27:38 PM PDT 24
Peak memory 263448 kb
Host smart-24e0a1bd-9286-484f-af46-1a23f9c325d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116011835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1116011835
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2066949550
Short name T915
Test name
Test status
Simulation time 2332594300 ps
CPU time 168.62 seconds
Started Jun 13 03:24:09 PM PDT 24
Finished Jun 13 03:26:59 PM PDT 24
Peak memory 260632 kb
Host smart-ee15f699-b36f-4505-98c9-c8d055571f71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066949550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.2066949550
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1518289211
Short name T852
Test name
Test status
Simulation time 68499400 ps
CPU time 328.79 seconds
Started Jun 13 03:24:11 PM PDT 24
Finished Jun 13 03:29:42 PM PDT 24
Peak memory 279556 kb
Host smart-5534a1ad-5825-43b2-8942-4b578bf47e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518289211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1518289211
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2123095867
Short name T841
Test name
Test status
Simulation time 1464190300 ps
CPU time 134.05 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:26:26 PM PDT 24
Peak memory 290504 kb
Host smart-fa790e43-62f6-4106-8d45-208b53031444
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123095867 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2123095867
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1693108652
Short name T544
Test name
Test status
Simulation time 31004900 ps
CPU time 30.75 seconds
Started Jun 13 03:24:17 PM PDT 24
Finished Jun 13 03:24:49 PM PDT 24
Peak memory 276092 kb
Host smart-5cc61c06-333a-4594-a888-aa83df43e2d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693108652 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1693108652
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2917645116
Short name T532
Test name
Test status
Simulation time 17155010500 ps
CPU time 84.07 seconds
Started Jun 13 03:24:07 PM PDT 24
Finished Jun 13 03:25:33 PM PDT 24
Peak memory 264012 kb
Host smart-c1d1cb41-59c5-454b-871c-300dab28a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917645116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2917645116
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.50901343
Short name T709
Test name
Test status
Simulation time 83479200 ps
CPU time 194.64 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:27:27 PM PDT 24
Peak memory 279136 kb
Host smart-97edda3d-3f71-4a9c-acfc-9e81b37ada53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50901343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.50901343
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1094146231
Short name T664
Test name
Test status
Simulation time 5691730900 ps
CPU time 173.99 seconds
Started Jun 13 03:24:10 PM PDT 24
Finished Jun 13 03:27:06 PM PDT 24
Peak memory 260364 kb
Host smart-2a787a6d-c3a7-4ef9-ae3e-10bfbb2853cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094146231 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1094146231
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.274741483
Short name T474
Test name
Test status
Simulation time 66502600 ps
CPU time 13.41 seconds
Started Jun 13 03:24:41 PM PDT 24
Finished Jun 13 03:24:55 PM PDT 24
Peak memory 265712 kb
Host smart-77a7fd6a-249a-4dfa-ba6c-53f408d9135a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274741483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.274741483
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.1739741956
Short name T1045
Test name
Test status
Simulation time 26948800 ps
CPU time 16.11 seconds
Started Jun 13 03:24:26 PM PDT 24
Finished Jun 13 03:24:43 PM PDT 24
Peak memory 275284 kb
Host smart-c3a04f97-eb41-4c5d-bb0a-041d52aae324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739741956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1739741956
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.2484143388
Short name T632
Test name
Test status
Simulation time 10684200 ps
CPU time 21.78 seconds
Started Jun 13 03:24:22 PM PDT 24
Finished Jun 13 03:24:45 PM PDT 24
Peak memory 274160 kb
Host smart-9dd6d7da-91c1-4462-a894-f07f435db8aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484143388 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.2484143388
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2979300757
Short name T1068
Test name
Test status
Simulation time 10018989600 ps
CPU time 177.81 seconds
Started Jun 13 03:24:27 PM PDT 24
Finished Jun 13 03:27:26 PM PDT 24
Peak memory 297228 kb
Host smart-48e078a5-6007-446e-9ff0-690432661309
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979300757 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2979300757
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2682763045
Short name T868
Test name
Test status
Simulation time 15096400 ps
CPU time 13.51 seconds
Started Jun 13 03:24:52 PM PDT 24
Finished Jun 13 03:25:08 PM PDT 24
Peak memory 258736 kb
Host smart-7d61d5a0-f48c-45e2-8530-df35e2b94857
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682763045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2682763045
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.4108130404
Short name T671
Test name
Test status
Simulation time 160190338800 ps
CPU time 936.72 seconds
Started Jun 13 03:24:16 PM PDT 24
Finished Jun 13 03:39:54 PM PDT 24
Peak memory 264508 kb
Host smart-474cd873-63db-4a79-a9b0-680587a56e1c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108130404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.4108130404
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3991597500
Short name T292
Test name
Test status
Simulation time 504089200 ps
CPU time 57 seconds
Started Jun 13 03:24:14 PM PDT 24
Finished Jun 13 03:25:12 PM PDT 24
Peak memory 263260 kb
Host smart-a40c0bc6-2b5d-4ebb-8f8e-2e9750d74059
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991597500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.3991597500
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.673350299
Short name T235
Test name
Test status
Simulation time 7956176900 ps
CPU time 134.38 seconds
Started Jun 13 03:24:14 PM PDT 24
Finished Jun 13 03:26:30 PM PDT 24
Peak memory 294324 kb
Host smart-cf543b74-716c-43f9-a7da-57aac9b0340f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673350299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.673350299
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3399194260
Short name T936
Test name
Test status
Simulation time 23275033800 ps
CPU time 187.99 seconds
Started Jun 13 03:24:16 PM PDT 24
Finished Jun 13 03:27:25 PM PDT 24
Peak memory 293484 kb
Host smart-c1aecf05-550b-41ee-bb3a-37d0a2a31051
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399194260 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3399194260
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.1937072500
Short name T198
Test name
Test status
Simulation time 3576278800 ps
CPU time 67.77 seconds
Started Jun 13 03:24:13 PM PDT 24
Finished Jun 13 03:25:23 PM PDT 24
Peak memory 260936 kb
Host smart-4501028c-5303-4ce2-83bc-0858cf3a97b7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937072500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1
937072500
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1052432629
Short name T154
Test name
Test status
Simulation time 15308400 ps
CPU time 13.32 seconds
Started Jun 13 03:24:27 PM PDT 24
Finished Jun 13 03:24:41 PM PDT 24
Peak memory 265396 kb
Host smart-bce3e29d-647a-4fd4-a48a-6eff5cd003c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052432629 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1052432629
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.993359473
Short name T639
Test name
Test status
Simulation time 74687900 ps
CPU time 109.1 seconds
Started Jun 13 03:24:14 PM PDT 24
Finished Jun 13 03:26:04 PM PDT 24
Peak memory 260328 kb
Host smart-43242915-44e0-489c-8abf-080e35df5ac7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993359473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ot
p_reset.993359473
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.874187568
Short name T623
Test name
Test status
Simulation time 2071282200 ps
CPU time 369.74 seconds
Started Jun 13 03:24:15 PM PDT 24
Finished Jun 13 03:30:26 PM PDT 24
Peak memory 263448 kb
Host smart-581f11a9-06c4-4495-8044-ffd3ff2a4090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874187568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.874187568
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2169000910
Short name T408
Test name
Test status
Simulation time 18042900 ps
CPU time 13.52 seconds
Started Jun 13 03:24:24 PM PDT 24
Finished Jun 13 03:24:38 PM PDT 24
Peak memory 265636 kb
Host smart-210c4f09-76c1-4e7c-a911-797b4f4863b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169000910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2169000910
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.301373230
Short name T583
Test name
Test status
Simulation time 175485600 ps
CPU time 247.23 seconds
Started Jun 13 03:24:16 PM PDT 24
Finished Jun 13 03:28:24 PM PDT 24
Peak memory 281996 kb
Host smart-05fdcd2b-6b3d-4076-aab4-283fcc1c72f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301373230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.301373230
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2883711260
Short name T655
Test name
Test status
Simulation time 234528200 ps
CPU time 34.93 seconds
Started Jun 13 03:24:25 PM PDT 24
Finished Jun 13 03:25:00 PM PDT 24
Peak memory 277188 kb
Host smart-cd1752f8-20ac-44e9-bfa3-df77c61bbe8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883711260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2883711260
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3179820521
Short name T195
Test name
Test status
Simulation time 1853195500 ps
CPU time 120.68 seconds
Started Jun 13 03:24:15 PM PDT 24
Finished Jun 13 03:26:17 PM PDT 24
Peak memory 289680 kb
Host smart-37f6f285-49b6-48fb-a865-ae4229bed769
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179820521 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.3179820521
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.1367457936
Short name T862
Test name
Test status
Simulation time 73017000 ps
CPU time 31.24 seconds
Started Jun 13 03:24:21 PM PDT 24
Finished Jun 13 03:24:54 PM PDT 24
Peak memory 277196 kb
Host smart-d4c537ea-ef79-41d7-9ba0-985317d9a58f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367457936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.1367457936
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3902029376
Short name T126
Test name
Test status
Simulation time 44063700 ps
CPU time 31.61 seconds
Started Jun 13 03:24:25 PM PDT 24
Finished Jun 13 03:24:57 PM PDT 24
Peak memory 275396 kb
Host smart-172834b1-151c-4a7f-bd7a-a3fc272a3c93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902029376 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3902029376
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3654674740
Short name T586
Test name
Test status
Simulation time 2296239200 ps
CPU time 56.48 seconds
Started Jun 13 03:24:21 PM PDT 24
Finished Jun 13 03:25:19 PM PDT 24
Peak memory 260060 kb
Host smart-7b2d13ca-4f64-4c24-9710-f035f752b391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654674740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3654674740
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2950402718
Short name T543
Test name
Test status
Simulation time 45836300 ps
CPU time 123.31 seconds
Started Jun 13 03:24:23 PM PDT 24
Finished Jun 13 03:26:27 PM PDT 24
Peak memory 277800 kb
Host smart-9ea7a362-7e29-414b-8e7e-e999bdd635ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950402718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2950402718
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.2459469524
Short name T1072
Test name
Test status
Simulation time 2625881900 ps
CPU time 212.36 seconds
Started Jun 13 03:24:14 PM PDT 24
Finished Jun 13 03:27:48 PM PDT 24
Peak memory 265476 kb
Host smart-127caeb9-51ee-4ebf-bb46-3756f0235227
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459469524 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.2459469524
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.2910671440
Short name T7
Test name
Test status
Simulation time 170201300 ps
CPU time 13.75 seconds
Started Jun 13 03:18:06 PM PDT 24
Finished Jun 13 03:18:22 PM PDT 24
Peak memory 265864 kb
Host smart-42cad26c-ff9a-45b3-8e22-ed3d770f31b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910671440 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2910671440
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.1454434552
Short name T842
Test name
Test status
Simulation time 220498700 ps
CPU time 14.45 seconds
Started Jun 13 03:18:18 PM PDT 24
Finished Jun 13 03:18:33 PM PDT 24
Peak memory 258676 kb
Host smart-d748f7ef-7e8a-42bb-9c9d-f50f232cb8ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454434552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1
454434552
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3732509455
Short name T707
Test name
Test status
Simulation time 15996300 ps
CPU time 15.97 seconds
Started Jun 13 03:18:02 PM PDT 24
Finished Jun 13 03:18:19 PM PDT 24
Peak memory 284836 kb
Host smart-f7011d20-08a0-41e4-a475-b6812d93a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732509455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3732509455
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.1031885081
Short name T468
Test name
Test status
Simulation time 1512150900 ps
CPU time 103.55 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:19:40 PM PDT 24
Peak memory 282268 kb
Host smart-134fb888-6ee4-47a8-b2b3-bb650b58501d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031885081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.1031885081
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.2090638270
Short name T504
Test name
Test status
Simulation time 44175400 ps
CPU time 21.48 seconds
Started Jun 13 03:18:00 PM PDT 24
Finished Jun 13 03:18:22 PM PDT 24
Peak memory 274200 kb
Host smart-0ca8f503-c49e-4882-a83f-a9a60acb0afc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090638270 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.2090638270
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.3400276680
Short name T612
Test name
Test status
Simulation time 4169404400 ps
CPU time 545.21 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 03:26:55 PM PDT 24
Peak memory 263748 kb
Host smart-1efed8d7-f68c-43fe-b4d0-4113ba6a4c8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400276680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.3400276680
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.220943862
Short name T645
Test name
Test status
Simulation time 6999677400 ps
CPU time 2774.4 seconds
Started Jun 13 03:17:55 PM PDT 24
Finished Jun 13 04:04:12 PM PDT 24
Peak memory 264936 kb
Host smart-35107e92-9fd1-4b0f-8bee-d4d05167a3be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220943862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erro
r_mp.220943862
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3466071295
Short name T74
Test name
Test status
Simulation time 5702548500 ps
CPU time 2074.51 seconds
Started Jun 13 03:17:51 PM PDT 24
Finished Jun 13 03:52:26 PM PDT 24
Peak memory 265300 kb
Host smart-07edf873-ec3c-47bf-a7db-90c29225e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466071295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3466071295
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2558799708
Short name T178
Test name
Test status
Simulation time 916084200 ps
CPU time 954.46 seconds
Started Jun 13 03:17:55 PM PDT 24
Finished Jun 13 03:33:52 PM PDT 24
Peak memory 270748 kb
Host smart-ebbe395b-63c3-4a08-ab1f-26e1bde9d877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558799708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2558799708
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.2866980671
Short name T500
Test name
Test status
Simulation time 331425900 ps
CPU time 23.06 seconds
Started Jun 13 03:17:49 PM PDT 24
Finished Jun 13 03:18:14 PM PDT 24
Peak memory 262752 kb
Host smart-47b379d1-e65e-4d1d-a2a5-7b4e7bd36d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866980671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2866980671
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2754561911
Short name T267
Test name
Test status
Simulation time 1329384000 ps
CPU time 40.71 seconds
Started Jun 13 03:18:05 PM PDT 24
Finished Jun 13 03:18:48 PM PDT 24
Peak memory 265784 kb
Host smart-4d77527d-9795-4773-94fa-34b0c4023f75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754561911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2754561911
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.3871363258
Short name T121
Test name
Test status
Simulation time 159102320200 ps
CPU time 2846.6 seconds
Started Jun 13 03:17:55 PM PDT 24
Finished Jun 13 04:05:24 PM PDT 24
Peak memory 263492 kb
Host smart-8ff15dfc-8af9-47ee-9c6b-564177578b18
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871363258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.3871363258
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.952136838
Short name T960
Test name
Test status
Simulation time 255744700 ps
CPU time 90.3 seconds
Started Jun 13 03:17:45 PM PDT 24
Finished Jun 13 03:19:16 PM PDT 24
Peak memory 265668 kb
Host smart-e1c0e008-cd2e-4f81-bcf2-cd69afc171f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952136838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.952136838
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1667609804
Short name T681
Test name
Test status
Simulation time 26014400 ps
CPU time 13.85 seconds
Started Jun 13 03:18:19 PM PDT 24
Finished Jun 13 03:18:34 PM PDT 24
Peak memory 258964 kb
Host smart-3dfcd213-3cc8-494a-95b0-b59f57ad3d93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667609804 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1667609804
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.111808394
Short name T778
Test name
Test status
Simulation time 379975404100 ps
CPU time 2061 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 03:52:11 PM PDT 24
Peak memory 265548 kb
Host smart-21df1a32-7ca6-4b88-b4f8-3beea898b2bf
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111808394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_hw_rma.111808394
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.4230623588
Short name T907
Test name
Test status
Simulation time 160190191900 ps
CPU time 974.51 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:34:04 PM PDT 24
Peak memory 264680 kb
Host smart-44fc6051-3ba2-43d6-8928-a345af184483
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230623588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.4230623588
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1079098517
Short name T1034
Test name
Test status
Simulation time 3797332900 ps
CPU time 133.43 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:20:02 PM PDT 24
Peak memory 263492 kb
Host smart-75ddde68-46d5-4292-8d81-0292fc66bc36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079098517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1079098517
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.3096772546
Short name T310
Test name
Test status
Simulation time 3038175000 ps
CPU time 208.27 seconds
Started Jun 13 03:17:52 PM PDT 24
Finished Jun 13 03:21:21 PM PDT 24
Peak memory 285488 kb
Host smart-2fc76de5-0d85-4b36-9a8f-69356339a19f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096772546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.3096772546
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1587952775
Short name T142
Test name
Test status
Simulation time 12034382800 ps
CPU time 143.01 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:20:17 PM PDT 24
Peak memory 292888 kb
Host smart-b82f500b-984d-495f-b657-170300ac4925
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587952775 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.1587952775
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3789081395
Short name T912
Test name
Test status
Simulation time 6790170600 ps
CPU time 66.24 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:19:02 PM PDT 24
Peak memory 260384 kb
Host smart-1b600f27-bc35-4056-b28d-64b0a955fd01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789081395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3789081395
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1238889491
Short name T882
Test name
Test status
Simulation time 84509213500 ps
CPU time 186.72 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:21:03 PM PDT 24
Peak memory 260348 kb
Host smart-cc08ca44-5d7c-421d-b28b-c56f83d5fbc7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123
8889491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1238889491
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.1435747095
Short name T478
Test name
Test status
Simulation time 16033187200 ps
CPU time 105.99 seconds
Started Jun 13 03:17:52 PM PDT 24
Finished Jun 13 03:19:39 PM PDT 24
Peak memory 263392 kb
Host smart-248e6669-e4cc-4b33-bc40-39db978a6734
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435747095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1435747095
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.2566002788
Short name T530
Test name
Test status
Simulation time 61335477600 ps
CPU time 137.69 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 03:20:07 PM PDT 24
Peak memory 265604 kb
Host smart-12ef95e3-e3b0-439b-88fe-fb4753e6ac47
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566002788 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.2566002788
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.1868238506
Short name T933
Test name
Test status
Simulation time 128846600 ps
CPU time 131.84 seconds
Started Jun 13 03:17:45 PM PDT 24
Finished Jun 13 03:19:59 PM PDT 24
Peak memory 260336 kb
Host smart-f290af38-5453-4f16-9f6d-e3f3c76c768e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868238506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.1868238506
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.963061640
Short name T1097
Test name
Test status
Simulation time 1456760100 ps
CPU time 197.05 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:21:11 PM PDT 24
Peak memory 282348 kb
Host smart-0b7fe2fb-c324-4f01-a591-b9aad818e4ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963061640 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.963061640
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3580968852
Short name T1023
Test name
Test status
Simulation time 1414213100 ps
CPU time 509.18 seconds
Started Jun 13 03:17:47 PM PDT 24
Finished Jun 13 03:26:19 PM PDT 24
Peak memory 263492 kb
Host smart-ac45af95-cf01-498d-b9ee-9f0161736007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580968852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3580968852
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.4061417800
Short name T1088
Test name
Test status
Simulation time 19120600 ps
CPU time 14.17 seconds
Started Jun 13 03:18:13 PM PDT 24
Finished Jun 13 03:18:29 PM PDT 24
Peak memory 266004 kb
Host smart-424430ea-1ee3-4ee0-8b5c-a721540e18d6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061417800 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.4061417800
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3064230292
Short name T955
Test name
Test status
Simulation time 39142500 ps
CPU time 13.5 seconds
Started Jun 13 03:17:52 PM PDT 24
Finished Jun 13 03:18:06 PM PDT 24
Peak memory 265564 kb
Host smart-4682f3a0-af0f-4c73-85cd-33d59185f985
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064230292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3064230292
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2280243119
Short name T125
Test name
Test status
Simulation time 7864065000 ps
CPU time 1000.68 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:34:30 PM PDT 24
Peak memory 288772 kb
Host smart-bd7fe68d-ad31-47c8-bd25-9019697726b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280243119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2280243119
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2499029142
Short name T721
Test name
Test status
Simulation time 55803900 ps
CPU time 100.96 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:19:30 PM PDT 24
Peak memory 263032 kb
Host smart-f8d7d0b8-e9b9-4869-856d-25f779c95464
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2499029142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2499029142
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.805601286
Short name T926
Test name
Test status
Simulation time 116334500 ps
CPU time 33.56 seconds
Started Jun 13 03:18:04 PM PDT 24
Finished Jun 13 03:18:40 PM PDT 24
Peak memory 273568 kb
Host smart-0839a340-2a84-4a91-a00f-f79b0e1ae806
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805601286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.805601286
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1878976315
Short name T464
Test name
Test status
Simulation time 149035300 ps
CPU time 33.01 seconds
Started Jun 13 03:17:59 PM PDT 24
Finished Jun 13 03:18:33 PM PDT 24
Peak memory 275816 kb
Host smart-16aca962-a070-4fdd-8744-7bcab1f2061a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878976315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1878976315
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.150642151
Short name T917
Test name
Test status
Simulation time 22421500 ps
CPU time 23.1 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:18:19 PM PDT 24
Peak memory 265376 kb
Host smart-08233535-ba82-4265-809e-0ff4177c4276
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150642151 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.150642151
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2154438871
Short name T875
Test name
Test status
Simulation time 40393400 ps
CPU time 21.26 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:18:17 PM PDT 24
Peak memory 265828 kb
Host smart-4845783e-7766-447c-bbec-7ce896340775
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154438871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.2154438871
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2422120063
Short name T171
Test name
Test status
Simulation time 39748396200 ps
CPU time 892.85 seconds
Started Jun 13 03:18:13 PM PDT 24
Finished Jun 13 03:33:08 PM PDT 24
Peak memory 261732 kb
Host smart-f26ee49d-cbe2-4d65-8c6b-7e5ef890a328
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422120063 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2422120063
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.4206971745
Short name T1015
Test name
Test status
Simulation time 2475969600 ps
CPU time 126.77 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:20:03 PM PDT 24
Peak memory 290392 kb
Host smart-042b4700-7b77-4653-ba4f-5fcca3a8a4f3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206971745 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.4206971745
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.3134501103
Short name T782
Test name
Test status
Simulation time 567765700 ps
CPU time 144.27 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:20:18 PM PDT 24
Peak memory 282356 kb
Host smart-c5118826-8ad0-443e-81b8-833164786555
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3134501103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3134501103
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3530091901
Short name T441
Test name
Test status
Simulation time 466195700 ps
CPU time 127.07 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:20:02 PM PDT 24
Peak memory 290524 kb
Host smart-3acf9885-be2e-4709-a735-962664920564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530091901 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3530091901
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.3564140726
Short name T123
Test name
Test status
Simulation time 8187439800 ps
CPU time 558.03 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:27:14 PM PDT 24
Peak memory 309972 kb
Host smart-d15ea838-be60-42c0-846f-e3719eab41a9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564140726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.3564140726
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.570745029
Short name T867
Test name
Test status
Simulation time 6745856700 ps
CPU time 559.6 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:27:16 PM PDT 24
Peak memory 332008 kb
Host smart-e51fa25c-0096-4c5e-974e-65428a516ba5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570745029 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_rw_derr.570745029
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.2316395153
Short name T999
Test name
Test status
Simulation time 104260800 ps
CPU time 30.33 seconds
Started Jun 13 03:17:59 PM PDT 24
Finished Jun 13 03:18:30 PM PDT 24
Peak memory 267968 kb
Host smart-5bba4d9e-2606-47a3-9b6c-3f8b04c01e7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316395153 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.2316395153
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3359447530
Short name T1046
Test name
Test status
Simulation time 14441295300 ps
CPU time 534.05 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:26:50 PM PDT 24
Peak memory 321388 kb
Host smart-90e506e7-5664-4047-b8c7-54ca50398c78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359447530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.3359447530
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1060577774
Short name T670
Test name
Test status
Simulation time 1568834400 ps
CPU time 60.83 seconds
Started Jun 13 03:18:05 PM PDT 24
Finished Jun 13 03:19:09 PM PDT 24
Peak memory 265040 kb
Host smart-270f5f19-ebd2-4807-9157-20e824d446a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060577774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1060577774
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3300388865
Short name T974
Test name
Test status
Simulation time 635803500 ps
CPU time 66.05 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:19:02 PM PDT 24
Peak memory 274084 kb
Host smart-e493bb82-1e80-4480-b8d0-1a3558709b9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300388865 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3300388865
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.2572173940
Short name T553
Test name
Test status
Simulation time 1292391200 ps
CPU time 74.76 seconds
Started Jun 13 03:17:54 PM PDT 24
Finished Jun 13 03:19:11 PM PDT 24
Peak memory 274156 kb
Host smart-9fec16ed-8dab-4c14-a09f-441987843d34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572173940 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.2572173940
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.292313683
Short name T766
Test name
Test status
Simulation time 1399667900 ps
CPU time 181.59 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:20:50 PM PDT 24
Peak memory 281972 kb
Host smart-2d4afbe8-68f7-4fb0-8fe0-bb291841481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292313683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.292313683
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.4095617442
Short name T865
Test name
Test status
Simulation time 52313400 ps
CPU time 26.7 seconds
Started Jun 13 03:17:45 PM PDT 24
Finished Jun 13 03:18:13 PM PDT 24
Peak memory 260032 kb
Host smart-326fb25e-012b-4cf5-9609-2b7879aad3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095617442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.4095617442
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.3309845197
Short name T1016
Test name
Test status
Simulation time 214513100 ps
CPU time 346.03 seconds
Started Jun 13 03:18:05 PM PDT 24
Finished Jun 13 03:23:54 PM PDT 24
Peak memory 278584 kb
Host smart-f846854c-e29e-478a-89d1-c262443d918e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309845197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.3309845197
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3746502902
Short name T978
Test name
Test status
Simulation time 94395100 ps
CPU time 24.39 seconds
Started Jun 13 03:17:46 PM PDT 24
Finished Jun 13 03:18:14 PM PDT 24
Peak memory 260080 kb
Host smart-df3b7f33-062f-4cf8-8cd3-ea024f23b0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746502902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3746502902
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.3314123908
Short name T976
Test name
Test status
Simulation time 2821086600 ps
CPU time 200.25 seconds
Started Jun 13 03:17:53 PM PDT 24
Finished Jun 13 03:21:15 PM PDT 24
Peak memory 259744 kb
Host smart-1e7e994f-9ada-4e75-9d79-ebc695896fb3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314123908 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.3314123908
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.3121091771
Short name T251
Test name
Test status
Simulation time 137295500 ps
CPU time 15.04 seconds
Started Jun 13 03:18:05 PM PDT 24
Finished Jun 13 03:18:23 PM PDT 24
Peak memory 265364 kb
Host smart-0fa1b43e-09f6-4ef8-b885-b7370f3df93d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121091771 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3121091771
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.3897105588
Short name T695
Test name
Test status
Simulation time 17173900 ps
CPU time 13.42 seconds
Started Jun 13 03:24:32 PM PDT 24
Finished Jun 13 03:24:46 PM PDT 24
Peak memory 265632 kb
Host smart-2ad33ecc-b2cf-48ec-a0d7-099c131b161b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897105588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
3897105588
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.4064151391
Short name T640
Test name
Test status
Simulation time 32814400 ps
CPU time 16.08 seconds
Started Jun 13 03:24:32 PM PDT 24
Finished Jun 13 03:24:49 PM PDT 24
Peak memory 275156 kb
Host smart-7567c0b0-5657-4334-baa0-172274361e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064151391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.4064151391
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2038410251
Short name T679
Test name
Test status
Simulation time 37653100 ps
CPU time 20.68 seconds
Started Jun 13 03:24:31 PM PDT 24
Finished Jun 13 03:24:52 PM PDT 24
Peak memory 274160 kb
Host smart-268dd687-6320-4ea3-8154-5c2daa1b09cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038410251 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2038410251
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2142269685
Short name T405
Test name
Test status
Simulation time 1322898200 ps
CPU time 111.4 seconds
Started Jun 13 03:24:25 PM PDT 24
Finished Jun 13 03:26:17 PM PDT 24
Peak memory 263020 kb
Host smart-656a7349-df9f-487a-80cf-917a647301f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142269685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2142269685
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3318693135
Short name T931
Test name
Test status
Simulation time 5834537900 ps
CPU time 200.29 seconds
Started Jun 13 03:25:29 PM PDT 24
Finished Jun 13 03:28:50 PM PDT 24
Peak memory 285248 kb
Host smart-cce5f9c2-5dd2-4f2e-a96f-cbf144e86d66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318693135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3318693135
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.755229941
Short name T450
Test name
Test status
Simulation time 23095995700 ps
CPU time 140.09 seconds
Started Jun 13 03:24:28 PM PDT 24
Finished Jun 13 03:26:49 PM PDT 24
Peak memory 292916 kb
Host smart-d22b4c88-f5fb-4337-b429-966f994ba083
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755229941 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.755229941
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1299219138
Short name T967
Test name
Test status
Simulation time 39803000 ps
CPU time 109.03 seconds
Started Jun 13 03:24:28 PM PDT 24
Finished Jun 13 03:26:18 PM PDT 24
Peak memory 260344 kb
Host smart-1ed48ad8-f898-40b0-bdc5-3b71a979c000
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299219138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1299219138
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.4287947350
Short name T708
Test name
Test status
Simulation time 37540300 ps
CPU time 13.91 seconds
Started Jun 13 03:24:28 PM PDT 24
Finished Jun 13 03:24:43 PM PDT 24
Peak memory 259104 kb
Host smart-19714110-219a-460a-9fda-1e6a8cbf62f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287947350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.4287947350
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.3494482389
Short name T316
Test name
Test status
Simulation time 38903700 ps
CPU time 27.95 seconds
Started Jun 13 03:24:34 PM PDT 24
Finished Jun 13 03:25:03 PM PDT 24
Peak memory 275960 kb
Host smart-18018d83-4461-4036-9cde-2d2962576856
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494482389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.3494482389
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2634644350
Short name T40
Test name
Test status
Simulation time 289474100 ps
CPU time 31.48 seconds
Started Jun 13 03:24:31 PM PDT 24
Finished Jun 13 03:25:04 PM PDT 24
Peak memory 268264 kb
Host smart-47bf4495-a167-4f47-93c0-8979de4408e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634644350 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2634644350
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1134776882
Short name T237
Test name
Test status
Simulation time 38599500 ps
CPU time 192.15 seconds
Started Jun 13 03:24:25 PM PDT 24
Finished Jun 13 03:27:38 PM PDT 24
Peak memory 278824 kb
Host smart-adee09b2-fc97-4058-ab3d-94bf848084e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134776882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1134776882
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.1057402643
Short name T831
Test name
Test status
Simulation time 47681100 ps
CPU time 13.54 seconds
Started Jun 13 03:24:44 PM PDT 24
Finished Jun 13 03:24:59 PM PDT 24
Peak memory 258556 kb
Host smart-6e2d8dcc-23c7-4546-884c-1435bcf1922f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057402643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
1057402643
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2943574907
Short name T176
Test name
Test status
Simulation time 16149700 ps
CPU time 15.89 seconds
Started Jun 13 03:24:44 PM PDT 24
Finished Jun 13 03:25:00 PM PDT 24
Peak memory 275104 kb
Host smart-7b93f91c-f383-4af8-ac19-a31e4a6085cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943574907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2943574907
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3153215408
Short name T656
Test name
Test status
Simulation time 15889000 ps
CPU time 21.58 seconds
Started Jun 13 03:24:37 PM PDT 24
Finished Jun 13 03:24:59 PM PDT 24
Peak memory 265904 kb
Host smart-1cb4d1ae-913f-4532-8b71-2164e8f34329
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153215408 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3153215408
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.3693120589
Short name T710
Test name
Test status
Simulation time 4025061100 ps
CPU time 120.19 seconds
Started Jun 13 03:24:38 PM PDT 24
Finished Jun 13 03:26:39 PM PDT 24
Peak memory 263408 kb
Host smart-5199d356-fd42-4e5a-a08e-463b094dd0ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693120589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.3693120589
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.2149489705
Short name T266
Test name
Test status
Simulation time 1567982700 ps
CPU time 129.75 seconds
Started Jun 13 03:24:39 PM PDT 24
Finished Jun 13 03:26:49 PM PDT 24
Peak memory 285636 kb
Host smart-c1c98506-6114-4292-bf3b-2d0aa3bff439
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149489705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.2149489705
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1408061958
Short name T38
Test name
Test status
Simulation time 49321952800 ps
CPU time 299.72 seconds
Started Jun 13 03:24:38 PM PDT 24
Finished Jun 13 03:29:38 PM PDT 24
Peak memory 292800 kb
Host smart-7945e010-9cc1-4b61-b58d-eaac1eacc32e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408061958 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1408061958
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.771914647
Short name T157
Test name
Test status
Simulation time 133313000 ps
CPU time 132.04 seconds
Started Jun 13 03:24:38 PM PDT 24
Finished Jun 13 03:26:51 PM PDT 24
Peak memory 265768 kb
Host smart-166073a4-603b-4a5e-9295-d397f83c9e88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771914647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.771914647
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1512411254
Short name T952
Test name
Test status
Simulation time 142496900 ps
CPU time 13.68 seconds
Started Jun 13 03:24:38 PM PDT 24
Finished Jun 13 03:24:52 PM PDT 24
Peak memory 259072 kb
Host smart-e5017e89-b2c3-4213-80b1-fcd4f1c37dec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512411254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.1512411254
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.1093632510
Short name T571
Test name
Test status
Simulation time 74568600 ps
CPU time 30.92 seconds
Started Jun 13 03:24:37 PM PDT 24
Finished Jun 13 03:25:08 PM PDT 24
Peak memory 276140 kb
Host smart-ee318041-2693-420f-bcfb-3b84e02ea219
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093632510 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.1093632510
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2289481502
Short name T519
Test name
Test status
Simulation time 13315073500 ps
CPU time 86.81 seconds
Started Jun 13 03:24:39 PM PDT 24
Finished Jun 13 03:26:06 PM PDT 24
Peak memory 263968 kb
Host smart-3d414293-6332-4a73-a697-61e6b73ab415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289481502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2289481502
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.3620241237
Short name T523
Test name
Test status
Simulation time 219129400 ps
CPU time 99.18 seconds
Started Jun 13 03:24:33 PM PDT 24
Finished Jun 13 03:26:14 PM PDT 24
Peak memory 276556 kb
Host smart-4fc7530e-53d5-4a6f-8eed-e99e8bab78f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620241237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3620241237
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.3796456436
Short name T702
Test name
Test status
Simulation time 37002500 ps
CPU time 13.59 seconds
Started Jun 13 03:24:50 PM PDT 24
Finished Jun 13 03:25:05 PM PDT 24
Peak memory 258624 kb
Host smart-32227842-c08e-4af5-9dd1-17027cd8884b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796456436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
3796456436
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2358473758
Short name T560
Test name
Test status
Simulation time 75932200 ps
CPU time 13.14 seconds
Started Jun 13 03:24:49 PM PDT 24
Finished Jun 13 03:25:04 PM PDT 24
Peak memory 275204 kb
Host smart-4abe8564-9f12-439b-a678-8e1ff3ff2a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358473758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2358473758
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2579568581
Short name T87
Test name
Test status
Simulation time 31437000 ps
CPU time 22.29 seconds
Started Jun 13 03:24:49 PM PDT 24
Finished Jun 13 03:25:12 PM PDT 24
Peak memory 274072 kb
Host smart-ec2131ae-86f9-47bb-b81c-029cc1864d42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579568581 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2579568581
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2069885848
Short name T482
Test name
Test status
Simulation time 3526976600 ps
CPU time 63.85 seconds
Started Jun 13 03:24:46 PM PDT 24
Finished Jun 13 03:25:50 PM PDT 24
Peak memory 263556 kb
Host smart-4c603442-746b-4d33-9f10-02a9bd244b21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069885848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2069885848
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3396245565
Short name T309
Test name
Test status
Simulation time 3613829500 ps
CPU time 133.43 seconds
Started Jun 13 03:24:45 PM PDT 24
Finished Jun 13 03:26:59 PM PDT 24
Peak memory 294976 kb
Host smart-87c6ce1c-61fe-4075-8f97-96f799fb4398
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396245565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3396245565
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.4149381508
Short name T932
Test name
Test status
Simulation time 48684902500 ps
CPU time 274.61 seconds
Started Jun 13 03:24:45 PM PDT 24
Finished Jun 13 03:29:20 PM PDT 24
Peak memory 285244 kb
Host smart-156dced4-7621-42f7-8908-ddc092264e4d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149381508 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.4149381508
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.1250367802
Short name T705
Test name
Test status
Simulation time 150028400 ps
CPU time 137.09 seconds
Started Jun 13 03:24:45 PM PDT 24
Finished Jun 13 03:27:03 PM PDT 24
Peak memory 264648 kb
Host smart-1062a5b3-a673-406a-9f5a-1bc9b4b3d9ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250367802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.1250367802
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3033383059
Short name T213
Test name
Test status
Simulation time 60989200 ps
CPU time 13.67 seconds
Started Jun 13 03:24:44 PM PDT 24
Finished Jun 13 03:24:59 PM PDT 24
Peak memory 259232 kb
Host smart-233ea15c-23c0-4a55-96b7-dd361cd8fa2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033383059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3033383059
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1944873898
Short name T1004
Test name
Test status
Simulation time 81004700 ps
CPU time 30.09 seconds
Started Jun 13 03:24:46 PM PDT 24
Finished Jun 13 03:25:16 PM PDT 24
Peak memory 275904 kb
Host smart-986307b7-a620-4433-8958-2d6a95adb02a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944873898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1944873898
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.2195148127
Short name T1080
Test name
Test status
Simulation time 2855760400 ps
CPU time 61.43 seconds
Started Jun 13 03:24:49 PM PDT 24
Finished Jun 13 03:25:52 PM PDT 24
Peak memory 263540 kb
Host smart-163b31ed-bfbd-4578-a0aa-5e40d413be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195148127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.2195148127
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.886001910
Short name T984
Test name
Test status
Simulation time 696857400 ps
CPU time 115.46 seconds
Started Jun 13 03:24:42 PM PDT 24
Finished Jun 13 03:26:38 PM PDT 24
Peak memory 279904 kb
Host smart-c05ca528-e6c5-439c-b99b-4724b5c0d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886001910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.886001910
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.2234862366
Short name T400
Test name
Test status
Simulation time 508572600 ps
CPU time 14.06 seconds
Started Jun 13 03:24:58 PM PDT 24
Finished Jun 13 03:25:13 PM PDT 24
Peak memory 265664 kb
Host smart-301d9bc6-230c-4d89-be1e-adef1defc0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234862366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
2234862366
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.457995830
Short name T555
Test name
Test status
Simulation time 184063400 ps
CPU time 16.1 seconds
Started Jun 13 03:24:55 PM PDT 24
Finished Jun 13 03:25:13 PM PDT 24
Peak memory 275280 kb
Host smart-fe5f428c-b0af-42e4-88b2-6662538df30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457995830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.457995830
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.1430382177
Short name T966
Test name
Test status
Simulation time 28256600 ps
CPU time 22.34 seconds
Started Jun 13 03:24:57 PM PDT 24
Finished Jun 13 03:25:21 PM PDT 24
Peak memory 265868 kb
Host smart-357764c9-daa4-43a3-98fa-4c6b8f6224f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430382177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.1430382177
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3134841971
Short name T964
Test name
Test status
Simulation time 3941160600 ps
CPU time 179.66 seconds
Started Jun 13 03:24:48 PM PDT 24
Finished Jun 13 03:27:48 PM PDT 24
Peak memory 263516 kb
Host smart-7d074ff8-40aa-4d5f-befe-0384ebc14aa4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134841971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3134841971
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3765089938
Short name T989
Test name
Test status
Simulation time 6246692300 ps
CPU time 223.59 seconds
Started Jun 13 03:24:48 PM PDT 24
Finished Jun 13 03:28:33 PM PDT 24
Peak memory 285380 kb
Host smart-3d7b2e25-ec4a-42d7-b2f6-7f3942f888c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765089938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3765089938
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.991030082
Short name T648
Test name
Test status
Simulation time 47712445000 ps
CPU time 299.75 seconds
Started Jun 13 03:24:51 PM PDT 24
Finished Jun 13 03:29:53 PM PDT 24
Peak memory 285312 kb
Host smart-f27a0935-90af-40d1-abf1-5322e657e4df
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991030082 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.991030082
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.677795335
Short name T514
Test name
Test status
Simulation time 147136100 ps
CPU time 111.5 seconds
Started Jun 13 03:24:49 PM PDT 24
Finished Jun 13 03:26:42 PM PDT 24
Peak memory 260592 kb
Host smart-c7f45276-d64d-41a2-af41-70b0e0d4fd92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677795335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot
p_reset.677795335
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3684285216
Short name T606
Test name
Test status
Simulation time 65501600 ps
CPU time 13.45 seconds
Started Jun 13 03:24:50 PM PDT 24
Finished Jun 13 03:25:05 PM PDT 24
Peak memory 265736 kb
Host smart-80291330-edab-4e77-8409-f68be51ae205
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684285216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3684285216
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1752481581
Short name T513
Test name
Test status
Simulation time 34501700 ps
CPU time 28.38 seconds
Started Jun 13 03:24:49 PM PDT 24
Finished Jun 13 03:25:19 PM PDT 24
Peak memory 276156 kb
Host smart-d4a986d4-9708-4b5c-82de-2db14c3098b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752481581 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1752481581
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.4185861809
Short name T642
Test name
Test status
Simulation time 26634300 ps
CPU time 119.49 seconds
Started Jun 13 03:24:48 PM PDT 24
Finished Jun 13 03:26:48 PM PDT 24
Peak memory 277464 kb
Host smart-8e75f470-8e60-45bf-8141-02c850061e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185861809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.4185861809
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3076474219
Short name T950
Test name
Test status
Simulation time 43554500 ps
CPU time 13.36 seconds
Started Jun 13 03:25:00 PM PDT 24
Finished Jun 13 03:25:15 PM PDT 24
Peak memory 258612 kb
Host smart-009ee881-b235-4c8a-9a07-7f836792ec1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076474219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3076474219
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3148416958
Short name T1056
Test name
Test status
Simulation time 21756600 ps
CPU time 16 seconds
Started Jun 13 03:25:02 PM PDT 24
Finished Jun 13 03:25:19 PM PDT 24
Peak memory 275076 kb
Host smart-00f303f9-b193-4b08-bb8d-64755a50f100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148416958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3148416958
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.1541091421
Short name T598
Test name
Test status
Simulation time 32997000 ps
CPU time 21.88 seconds
Started Jun 13 03:25:00 PM PDT 24
Finished Jun 13 03:25:23 PM PDT 24
Peak memory 274148 kb
Host smart-6ac49fb5-865a-4f26-9b96-5ab04de6df2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541091421 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.1541091421
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.160773535
Short name T290
Test name
Test status
Simulation time 2520942800 ps
CPU time 165.72 seconds
Started Jun 13 03:24:54 PM PDT 24
Finished Jun 13 03:27:41 PM PDT 24
Peak memory 263540 kb
Host smart-c36a22da-0ccd-46b9-b977-80be50b28309
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160773535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h
w_sec_otp.160773535
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.63619978
Short name T1012
Test name
Test status
Simulation time 2953693000 ps
CPU time 157.08 seconds
Started Jun 13 03:24:59 PM PDT 24
Finished Jun 13 03:27:37 PM PDT 24
Peak memory 294560 kb
Host smart-9ef67c3c-bbf9-48b7-a4e1-e2e03c5a7132
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63619978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash
_ctrl_intr_rd.63619978
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3947077127
Short name T691
Test name
Test status
Simulation time 48525396300 ps
CPU time 300.52 seconds
Started Jun 13 03:24:59 PM PDT 24
Finished Jun 13 03:30:01 PM PDT 24
Peak memory 291468 kb
Host smart-f65d58b9-9b7d-4bf9-9741-cfff3e9b2c1c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947077127 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3947077127
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.3936658469
Short name T163
Test name
Test status
Simulation time 39804100 ps
CPU time 109.3 seconds
Started Jun 13 03:25:02 PM PDT 24
Finished Jun 13 03:26:52 PM PDT 24
Peak memory 260452 kb
Host smart-4bd5a653-bdc0-4305-b51d-7b1d7eb6a6be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936658469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.3936658469
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.4107106655
Short name T622
Test name
Test status
Simulation time 73690200 ps
CPU time 13.71 seconds
Started Jun 13 03:25:04 PM PDT 24
Finished Jun 13 03:25:18 PM PDT 24
Peak memory 265760 kb
Host smart-27aef227-e639-41a2-8fbe-ae172c5b87b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107106655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.4107106655
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.4011882109
Short name T807
Test name
Test status
Simulation time 47065800 ps
CPU time 31.21 seconds
Started Jun 13 03:25:06 PM PDT 24
Finished Jun 13 03:25:37 PM PDT 24
Peak memory 267908 kb
Host smart-2df1a6cc-218a-440c-8ccb-cf0967e4d63d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011882109 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.4011882109
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.3858304421
Short name T396
Test name
Test status
Simulation time 3448671000 ps
CPU time 65.61 seconds
Started Jun 13 03:25:01 PM PDT 24
Finished Jun 13 03:26:08 PM PDT 24
Peak memory 265116 kb
Host smart-69edc771-50a5-4152-b730-0375be3ea01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858304421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3858304421
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3022138252
Short name T847
Test name
Test status
Simulation time 62953800 ps
CPU time 144.98 seconds
Started Jun 13 03:24:58 PM PDT 24
Finished Jun 13 03:27:24 PM PDT 24
Peak memory 277336 kb
Host smart-3102eb86-8893-4642-993f-e5dfdc05c926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022138252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3022138252
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.2134742590
Short name T1048
Test name
Test status
Simulation time 61021000 ps
CPU time 13.85 seconds
Started Jun 13 03:25:06 PM PDT 24
Finished Jun 13 03:25:21 PM PDT 24
Peak memory 258604 kb
Host smart-dfa02157-0829-4144-85cc-51f29215c098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134742590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
2134742590
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2769500124
Short name T848
Test name
Test status
Simulation time 15198200 ps
CPU time 15.63 seconds
Started Jun 13 03:25:06 PM PDT 24
Finished Jun 13 03:25:22 PM PDT 24
Peak memory 284472 kb
Host smart-a6296fad-1fab-4a08-bbf1-f7367f36ce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769500124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2769500124
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1680162256
Short name T345
Test name
Test status
Simulation time 10369500 ps
CPU time 21.86 seconds
Started Jun 13 03:25:08 PM PDT 24
Finished Jun 13 03:25:30 PM PDT 24
Peak memory 265880 kb
Host smart-60b341aa-e5ad-43d4-834c-8fde8abcc531
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680162256 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1680162256
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3622975526
Short name T900
Test name
Test status
Simulation time 8248089700 ps
CPU time 113.62 seconds
Started Jun 13 03:24:58 PM PDT 24
Finished Jun 13 03:26:53 PM PDT 24
Peak memory 261284 kb
Host smart-1a67f9f9-3caa-4de7-a504-c37e916b9cd4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622975526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.3622975526
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.3464641046
Short name T712
Test name
Test status
Simulation time 6402411100 ps
CPU time 190.23 seconds
Started Jun 13 03:25:04 PM PDT 24
Finished Jun 13 03:28:15 PM PDT 24
Peak memory 285348 kb
Host smart-fb77e2a7-397c-4095-baf3-83043f8ee275
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464641046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.3464641046
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.83139984
Short name T970
Test name
Test status
Simulation time 22915385000 ps
CPU time 139.81 seconds
Started Jun 13 03:25:00 PM PDT 24
Finished Jun 13 03:27:21 PM PDT 24
Peak memory 293428 kb
Host smart-b521901e-5028-4c4b-97be-bfbe3b41d6e4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83139984 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.83139984
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1908220740
Short name T772
Test name
Test status
Simulation time 356081100 ps
CPU time 134.54 seconds
Started Jun 13 03:25:00 PM PDT 24
Finished Jun 13 03:27:15 PM PDT 24
Peak memory 260584 kb
Host smart-91ff89a8-7017-4cec-b1a0-aeada3e5787b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908220740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1908220740
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.4225435002
Short name T475
Test name
Test status
Simulation time 36992000 ps
CPU time 13.73 seconds
Started Jun 13 03:25:01 PM PDT 24
Finished Jun 13 03:25:15 PM PDT 24
Peak memory 259300 kb
Host smart-00232ab4-9fc0-44f4-93e9-80069df31c31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225435002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.4225435002
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.543539672
Short name T876
Test name
Test status
Simulation time 76141800 ps
CPU time 30.48 seconds
Started Jun 13 03:24:58 PM PDT 24
Finished Jun 13 03:25:30 PM PDT 24
Peak memory 275380 kb
Host smart-b635f358-0942-4f71-8016-30d386a2adb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543539672 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.543539672
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1137516097
Short name T368
Test name
Test status
Simulation time 1747131500 ps
CPU time 61.4 seconds
Started Jun 13 03:25:09 PM PDT 24
Finished Jun 13 03:26:11 PM PDT 24
Peak memory 264160 kb
Host smart-b77229d7-3299-4d49-a436-038a851711cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137516097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1137516097
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.548693529
Short name T879
Test name
Test status
Simulation time 25394200 ps
CPU time 123.13 seconds
Started Jun 13 03:25:00 PM PDT 24
Finished Jun 13 03:27:05 PM PDT 24
Peak memory 276808 kb
Host smart-22fa1f25-533f-4328-84de-7ae04e05df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548693529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.548693529
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1448824516
Short name T1013
Test name
Test status
Simulation time 53303800 ps
CPU time 13.91 seconds
Started Jun 13 03:25:17 PM PDT 24
Finished Jun 13 03:25:32 PM PDT 24
Peak memory 265624 kb
Host smart-ea84f994-bde0-4421-9d94-c10951bfe6e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448824516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1448824516
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.784300947
Short name T401
Test name
Test status
Simulation time 48554200 ps
CPU time 15.81 seconds
Started Jun 13 03:25:15 PM PDT 24
Finished Jun 13 03:25:33 PM PDT 24
Peak memory 275272 kb
Host smart-34668ed5-0907-450d-b9fc-40b8b56f3d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784300947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.784300947
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2969520824
Short name T354
Test name
Test status
Simulation time 11048900 ps
CPU time 21.64 seconds
Started Jun 13 03:25:11 PM PDT 24
Finished Jun 13 03:25:34 PM PDT 24
Peak memory 274108 kb
Host smart-363f20da-74a4-4bf0-904e-848ad529af81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969520824 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2969520824
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3937574327
Short name T91
Test name
Test status
Simulation time 451858700 ps
CPU time 43.4 seconds
Started Jun 13 03:25:05 PM PDT 24
Finished Jun 13 03:25:49 PM PDT 24
Peak memory 263504 kb
Host smart-7c9bbaad-4775-4d46-845f-2e4231523660
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937574327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3937574327
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3357002531
Short name T1024
Test name
Test status
Simulation time 6773523200 ps
CPU time 201.13 seconds
Started Jun 13 03:25:09 PM PDT 24
Finished Jun 13 03:28:31 PM PDT 24
Peak memory 285368 kb
Host smart-c5c9a7fb-be31-48df-bda2-1f1240586264
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357002531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3357002531
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1780216614
Short name T392
Test name
Test status
Simulation time 22231097100 ps
CPU time 172.08 seconds
Started Jun 13 03:25:11 PM PDT 24
Finished Jun 13 03:28:04 PM PDT 24
Peak memory 293520 kb
Host smart-2830da12-f571-4f20-b933-e524255b422f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780216614 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1780216614
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.615460206
Short name T435
Test name
Test status
Simulation time 42790000 ps
CPU time 133.84 seconds
Started Jun 13 03:25:07 PM PDT 24
Finished Jun 13 03:27:22 PM PDT 24
Peak memory 261404 kb
Host smart-95a25821-487c-4a9c-a17f-c20c5b44688c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615460206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.615460206
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.4267067008
Short name T1059
Test name
Test status
Simulation time 6421364300 ps
CPU time 177.44 seconds
Started Jun 13 03:25:12 PM PDT 24
Finished Jun 13 03:28:11 PM PDT 24
Peak memory 260584 kb
Host smart-00a74397-3fba-48b9-b2b6-850e71a15ac0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267067008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.4267067008
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2432583611
Short name T975
Test name
Test status
Simulation time 32343200 ps
CPU time 31.05 seconds
Started Jun 13 03:25:12 PM PDT 24
Finished Jun 13 03:25:44 PM PDT 24
Peak memory 275328 kb
Host smart-882e30eb-c70e-4994-998d-fd94aaf11a64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432583611 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.2432583611
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.596565011
Short name T371
Test name
Test status
Simulation time 430119100 ps
CPU time 54.51 seconds
Started Jun 13 03:25:11 PM PDT 24
Finished Jun 13 03:26:07 PM PDT 24
Peak memory 264212 kb
Host smart-b54ff88b-9128-4d52-a740-8d8211c7f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596565011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.596565011
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3559840252
Short name T564
Test name
Test status
Simulation time 27818900 ps
CPU time 77.55 seconds
Started Jun 13 03:25:06 PM PDT 24
Finished Jun 13 03:26:25 PM PDT 24
Peak memory 275960 kb
Host smart-8f946a96-9364-4b95-b4b5-c30ce352b3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559840252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3559840252
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1453556644
Short name T743
Test name
Test status
Simulation time 34858300 ps
CPU time 13.72 seconds
Started Jun 13 03:25:23 PM PDT 24
Finished Jun 13 03:25:38 PM PDT 24
Peak memory 258704 kb
Host smart-72882d70-08fe-4245-a71a-257555d171bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453556644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1453556644
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.763388681
Short name T1051
Test name
Test status
Simulation time 37322000 ps
CPU time 13.33 seconds
Started Jun 13 03:25:24 PM PDT 24
Finished Jun 13 03:25:38 PM PDT 24
Peak memory 275116 kb
Host smart-11742b76-1a52-40b9-a5aa-f2c94e38cb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763388681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.763388681
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3616667076
Short name T357
Test name
Test status
Simulation time 10600600 ps
CPU time 20.37 seconds
Started Jun 13 03:25:16 PM PDT 24
Finished Jun 13 03:25:38 PM PDT 24
Peak memory 274092 kb
Host smart-fd4c05bd-ad22-4d25-a886-f1ceb283226e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616667076 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3616667076
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.896998195
Short name T925
Test name
Test status
Simulation time 3508093600 ps
CPU time 104.27 seconds
Started Jun 13 03:25:17 PM PDT 24
Finished Jun 13 03:27:03 PM PDT 24
Peak memory 263060 kb
Host smart-7869bf37-e043-49f7-a055-ea02131b9817
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896998195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.896998195
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.832646402
Short name T945
Test name
Test status
Simulation time 908360000 ps
CPU time 197.4 seconds
Started Jun 13 03:25:15 PM PDT 24
Finished Jun 13 03:28:34 PM PDT 24
Peak memory 294464 kb
Host smart-631c2216-6f17-40cc-9cc0-95229da8f9fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832646402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flas
h_ctrl_intr_rd.832646402
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1346435858
Short name T684
Test name
Test status
Simulation time 12040425500 ps
CPU time 295.14 seconds
Started Jun 13 03:25:19 PM PDT 24
Finished Jun 13 03:30:15 PM PDT 24
Peak memory 291444 kb
Host smart-8dfca23e-f4d4-45fd-9102-3d2fcf756462
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346435858 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1346435858
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.597618326
Short name T393
Test name
Test status
Simulation time 42251100 ps
CPU time 131.02 seconds
Started Jun 13 03:25:15 PM PDT 24
Finished Jun 13 03:27:28 PM PDT 24
Peak memory 260260 kb
Host smart-dfc0e118-f1b2-4696-91fd-3db98d1338ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597618326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.597618326
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.495159918
Short name T894
Test name
Test status
Simulation time 4080624900 ps
CPU time 168.68 seconds
Started Jun 13 03:25:18 PM PDT 24
Finished Jun 13 03:28:07 PM PDT 24
Peak memory 259964 kb
Host smart-83b33ca5-9687-4d0b-920e-8e5a7efc5bbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495159918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.495159918
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.4099174377
Short name T737
Test name
Test status
Simulation time 66331200 ps
CPU time 31.4 seconds
Started Jun 13 03:25:18 PM PDT 24
Finished Jun 13 03:25:50 PM PDT 24
Peak memory 277480 kb
Host smart-44831f76-14ae-48a2-b173-7ecf5de0d546
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099174377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.4099174377
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4263231420
Short name T826
Test name
Test status
Simulation time 68943400 ps
CPU time 30.58 seconds
Started Jun 13 03:25:16 PM PDT 24
Finished Jun 13 03:25:48 PM PDT 24
Peak memory 268352 kb
Host smart-b8ddbeb3-7059-49e8-b9d3-0beaf262ba95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263231420 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.4263231420
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1000779368
Short name T458
Test name
Test status
Simulation time 2076708100 ps
CPU time 82.52 seconds
Started Jun 13 03:25:23 PM PDT 24
Finished Jun 13 03:26:47 PM PDT 24
Peak memory 260260 kb
Host smart-586bdbd5-85bd-4ab3-b812-7204a121a9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000779368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1000779368
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.694115703
Short name T247
Test name
Test status
Simulation time 132395800 ps
CPU time 51.92 seconds
Started Jun 13 03:25:17 PM PDT 24
Finished Jun 13 03:26:10 PM PDT 24
Peak memory 271536 kb
Host smart-088f4f88-f9c9-4b71-893c-a2a8f049a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694115703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.694115703
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.3874861896
Short name T81
Test name
Test status
Simulation time 34368400 ps
CPU time 13.69 seconds
Started Jun 13 03:25:40 PM PDT 24
Finished Jun 13 03:25:54 PM PDT 24
Peak memory 258644 kb
Host smart-c9eb6de2-42f7-4be6-b31d-0173a84acc67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874861896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
3874861896
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2280879613
Short name T911
Test name
Test status
Simulation time 49652600 ps
CPU time 15.98 seconds
Started Jun 13 03:25:43 PM PDT 24
Finished Jun 13 03:26:00 PM PDT 24
Peak memory 284580 kb
Host smart-2ebd13df-7695-4d23-bd16-c6b1dc60192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280879613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2280879613
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.4263153411
Short name T90
Test name
Test status
Simulation time 13448500 ps
CPU time 20.19 seconds
Started Jun 13 03:25:30 PM PDT 24
Finished Jun 13 03:25:51 PM PDT 24
Peak memory 274104 kb
Host smart-418580ce-654b-4f6b-a4ce-7887a376a6bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263153411 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.4263153411
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.125411073
Short name T913
Test name
Test status
Simulation time 901692700 ps
CPU time 43.33 seconds
Started Jun 13 03:25:25 PM PDT 24
Finished Jun 13 03:26:09 PM PDT 24
Peak memory 263356 kb
Host smart-7684238f-e43b-45f1-8512-74925ef8b711
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125411073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_h
w_sec_otp.125411073
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.500999654
Short name T311
Test name
Test status
Simulation time 29213486700 ps
CPU time 256.59 seconds
Started Jun 13 03:25:28 PM PDT 24
Finished Jun 13 03:29:45 PM PDT 24
Peak memory 285288 kb
Host smart-48268f1e-3d26-4cbf-b8e8-365df8a4a01b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500999654 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.500999654
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.3199663939
Short name T783
Test name
Test status
Simulation time 199776200 ps
CPU time 132.67 seconds
Started Jun 13 03:25:21 PM PDT 24
Finished Jun 13 03:27:35 PM PDT 24
Peak memory 260660 kb
Host smart-47764182-2558-499a-94e0-9ca6b4277966
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199663939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.3199663939
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.2244429441
Short name T293
Test name
Test status
Simulation time 61126300 ps
CPU time 13.53 seconds
Started Jun 13 03:25:41 PM PDT 24
Finished Jun 13 03:25:56 PM PDT 24
Peak memory 259060 kb
Host smart-260237ad-013c-43de-bf09-0b3451102d2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244429441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.2244429441
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.4199996006
Short name T653
Test name
Test status
Simulation time 32279000 ps
CPU time 30.85 seconds
Started Jun 13 03:25:30 PM PDT 24
Finished Jun 13 03:26:01 PM PDT 24
Peak memory 276560 kb
Host smart-8e611bd2-8d5a-4dad-97b6-382ee675abb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199996006 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.4199996006
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2799574067
Short name T889
Test name
Test status
Simulation time 39087900 ps
CPU time 76.8 seconds
Started Jun 13 03:25:22 PM PDT 24
Finished Jun 13 03:26:41 PM PDT 24
Peak memory 276936 kb
Host smart-4239314a-ce5c-453b-bfcf-feca816af575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799574067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2799574067
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3931676453
Short name T562
Test name
Test status
Simulation time 77407800 ps
CPU time 13.7 seconds
Started Jun 13 03:25:44 PM PDT 24
Finished Jun 13 03:25:58 PM PDT 24
Peak memory 258676 kb
Host smart-1944c6d5-58c6-40af-84ca-e690ead91d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931676453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3931676453
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.813534433
Short name T394
Test name
Test status
Simulation time 95730000 ps
CPU time 16.17 seconds
Started Jun 13 03:25:41 PM PDT 24
Finished Jun 13 03:25:58 PM PDT 24
Peak memory 275312 kb
Host smart-547b2a73-6c33-4270-bc85-0f0f82af3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813534433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.813534433
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.4175662830
Short name T898
Test name
Test status
Simulation time 21860000 ps
CPU time 22.28 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:26:05 PM PDT 24
Peak memory 274004 kb
Host smart-8278387a-3583-4c37-a20c-b2ba976c3ef5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175662830 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.4175662830
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1934527762
Short name T996
Test name
Test status
Simulation time 3047860200 ps
CPU time 106.41 seconds
Started Jun 13 03:25:26 PM PDT 24
Finished Jun 13 03:27:13 PM PDT 24
Peak memory 263464 kb
Host smart-a526f74a-e6ad-47bb-a286-9d428258b9b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934527762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1934527762
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1418545462
Short name T887
Test name
Test status
Simulation time 1562836300 ps
CPU time 217.42 seconds
Started Jun 13 03:25:28 PM PDT 24
Finished Jun 13 03:29:06 PM PDT 24
Peak memory 285360 kb
Host smart-89575070-6586-4ab0-a695-be7ce0293ecb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418545462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1418545462
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3231500038
Short name T825
Test name
Test status
Simulation time 32408282400 ps
CPU time 301.93 seconds
Started Jun 13 03:25:30 PM PDT 24
Finished Jun 13 03:30:33 PM PDT 24
Peak memory 285464 kb
Host smart-4f3281e8-22c7-4b44-a84d-d6a9b7e72c1b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231500038 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3231500038
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.218788542
Short name T638
Test name
Test status
Simulation time 38717600 ps
CPU time 111.04 seconds
Started Jun 13 03:25:28 PM PDT 24
Finished Jun 13 03:27:20 PM PDT 24
Peak memory 260304 kb
Host smart-dc8ad2df-4481-4158-9338-d0110668049f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218788542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.218788542
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1632155666
Short name T528
Test name
Test status
Simulation time 2373881900 ps
CPU time 201.61 seconds
Started Jun 13 03:25:44 PM PDT 24
Finished Jun 13 03:29:06 PM PDT 24
Peak memory 260064 kb
Host smart-e5a92ec4-c753-4847-9eb9-8e11f1b0f898
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632155666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.1632155666
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3142430348
Short name T574
Test name
Test status
Simulation time 29167200 ps
CPU time 28.88 seconds
Started Jun 13 03:25:43 PM PDT 24
Finished Jun 13 03:26:12 PM PDT 24
Peak memory 275936 kb
Host smart-0d4f4f22-f688-4370-bc34-ee6a86aaa6f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142430348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3142430348
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1834400797
Short name T470
Test name
Test status
Simulation time 49096300 ps
CPU time 30.82 seconds
Started Jun 13 03:25:44 PM PDT 24
Finished Jun 13 03:26:16 PM PDT 24
Peak memory 275300 kb
Host smart-0ef9dfa7-0944-4cc9-8319-c3cb946d0bc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834400797 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1834400797
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.2455076891
Short name T181
Test name
Test status
Simulation time 670425300 ps
CPU time 67.6 seconds
Started Jun 13 03:25:41 PM PDT 24
Finished Jun 13 03:26:49 PM PDT 24
Peak memory 263500 kb
Host smart-af5aba2e-bce8-4c4a-8cff-d4fa6536d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455076891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.2455076891
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.2102188936
Short name T821
Test name
Test status
Simulation time 87897900 ps
CPU time 99.15 seconds
Started Jun 13 03:25:28 PM PDT 24
Finished Jun 13 03:27:08 PM PDT 24
Peak memory 269128 kb
Host smart-503e7425-b792-42f1-b4aa-673edab88e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102188936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2102188936
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.2064104024
Short name T764
Test name
Test status
Simulation time 139885600 ps
CPU time 13.73 seconds
Started Jun 13 03:18:54 PM PDT 24
Finished Jun 13 03:19:08 PM PDT 24
Peak memory 258668 kb
Host smart-78dd1aec-0c88-4832-9b49-6a4907cd50b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064104024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2
064104024
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3767608604
Short name T340
Test name
Test status
Simulation time 21877400 ps
CPU time 13.94 seconds
Started Jun 13 03:18:46 PM PDT 24
Finished Jun 13 03:19:01 PM PDT 24
Peak memory 265244 kb
Host smart-e61c7375-e124-408a-a3bc-6cf248e29fc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767608604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3767608604
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3552360834
Short name T460
Test name
Test status
Simulation time 86497500 ps
CPU time 15.77 seconds
Started Jun 13 03:18:38 PM PDT 24
Finished Jun 13 03:18:55 PM PDT 24
Peak memory 284660 kb
Host smart-c3b8bfd9-68de-4c1b-8817-9061c0421e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552360834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3552360834
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.787882664
Short name T248
Test name
Test status
Simulation time 126031800 ps
CPU time 106.2 seconds
Started Jun 13 03:18:38 PM PDT 24
Finished Jun 13 03:20:25 PM PDT 24
Peak memory 282336 kb
Host smart-ff7bedc4-5738-4f72-9f8d-815c08c1a616
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787882664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_derr_detect.787882664
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2706420525
Short name T355
Test name
Test status
Simulation time 10290800 ps
CPU time 22.19 seconds
Started Jun 13 03:18:42 PM PDT 24
Finished Jun 13 03:19:05 PM PDT 24
Peak memory 274168 kb
Host smart-0a37d103-08a3-4996-9165-f53c78862aba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706420525 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2706420525
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2120009346
Short name T977
Test name
Test status
Simulation time 2755591400 ps
CPU time 494.85 seconds
Started Jun 13 03:18:18 PM PDT 24
Finished Jun 13 03:26:33 PM PDT 24
Peak memory 263788 kb
Host smart-785cb733-0131-4d05-8156-caf0c79ded77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120009346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2120009346
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.4146110488
Short name T211
Test name
Test status
Simulation time 10270847100 ps
CPU time 2556.2 seconds
Started Jun 13 03:18:29 PM PDT 24
Finished Jun 13 04:01:06 PM PDT 24
Peak memory 263096 kb
Host smart-80d6651c-5715-46e5-9ff0-a36df5cc220e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146110488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.4146110488
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.240395800
Short name T73
Test name
Test status
Simulation time 914223400 ps
CPU time 2793.8 seconds
Started Jun 13 03:18:29 PM PDT 24
Finished Jun 13 04:05:04 PM PDT 24
Peak memory 264420 kb
Host smart-d2d13d15-b540-4efd-867c-2af6540fa57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240395800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.240395800
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1258177954
Short name T276
Test name
Test status
Simulation time 2615565100 ps
CPU time 868.81 seconds
Started Jun 13 03:18:28 PM PDT 24
Finished Jun 13 03:32:58 PM PDT 24
Peak memory 273600 kb
Host smart-ca369082-f7b1-4267-8196-e05a57f14b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258177954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1258177954
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.1811781655
Short name T456
Test name
Test status
Simulation time 334183900 ps
CPU time 39.7 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:19:21 PM PDT 24
Peak memory 263384 kb
Host smart-49b5c726-4d95-4b96-9791-19602a4f5f8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811781655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.1811781655
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.4220396664
Short name T117
Test name
Test status
Simulation time 97825503400 ps
CPU time 4448.48 seconds
Started Jun 13 03:18:26 PM PDT 24
Finished Jun 13 04:32:35 PM PDT 24
Peak memory 265640 kb
Host smart-e2a63315-9a6b-4d3e-9e83-22e4ee42d339
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220396664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.4220396664
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3454429235
Short name T968
Test name
Test status
Simulation time 1176127232900 ps
CPU time 2235.94 seconds
Started Jun 13 03:18:24 PM PDT 24
Finished Jun 13 03:55:41 PM PDT 24
Peak memory 265696 kb
Host smart-08567c8e-2275-4d5c-986b-7d5df5cc920b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454429235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.3454429235
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3886055871
Short name T1042
Test name
Test status
Simulation time 197728700 ps
CPU time 98.47 seconds
Started Jun 13 03:18:19 PM PDT 24
Finished Jun 13 03:19:58 PM PDT 24
Peak memory 265632 kb
Host smart-43779bef-e799-4701-aed6-244df27f4960
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886055871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3886055871
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2754027605
Short name T800
Test name
Test status
Simulation time 10017780500 ps
CPU time 92.04 seconds
Started Jun 13 03:18:55 PM PDT 24
Finished Jun 13 03:20:28 PM PDT 24
Peak memory 332396 kb
Host smart-e708e5a4-5ad8-41dd-8182-5547109e905b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754027605 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2754027605
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.335887606
Short name T741
Test name
Test status
Simulation time 25518200 ps
CPU time 13.25 seconds
Started Jun 13 03:18:45 PM PDT 24
Finished Jun 13 03:18:59 PM PDT 24
Peak memory 265324 kb
Host smart-c94106f4-e9ab-4499-8366-8914fec67c40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335887606 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.335887606
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3309084714
Short name T399
Test name
Test status
Simulation time 5496498600 ps
CPU time 158.25 seconds
Started Jun 13 03:18:17 PM PDT 24
Finished Jun 13 03:20:56 PM PDT 24
Peak memory 262948 kb
Host smart-62cbaf3f-221b-4ec0-bd1b-e3eb5f0da835
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309084714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3309084714
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.3771612543
Short name T239
Test name
Test status
Simulation time 21354808300 ps
CPU time 666.84 seconds
Started Jun 13 03:18:36 PM PDT 24
Finished Jun 13 03:29:43 PM PDT 24
Peak memory 350620 kb
Host smart-c4d92d19-ef7b-4519-a4d4-8c165d480748
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771612543 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.3771612543
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2192897749
Short name T923
Test name
Test status
Simulation time 501865300 ps
CPU time 141.46 seconds
Started Jun 13 03:18:41 PM PDT 24
Finished Jun 13 03:21:04 PM PDT 24
Peak memory 294184 kb
Host smart-d50d1b6b-c682-4586-bc0f-113e1fa1183f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192897749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2192897749
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4228432513
Short name T628
Test name
Test status
Simulation time 11816641600 ps
CPU time 154.08 seconds
Started Jun 13 03:18:41 PM PDT 24
Finished Jun 13 03:21:17 PM PDT 24
Peak memory 293476 kb
Host smart-24c3bc60-420d-4b5b-8b2a-b6aed6ffec9a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228432513 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.4228432513
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3887410396
Short name T608
Test name
Test status
Simulation time 39087543100 ps
CPU time 167.14 seconds
Started Jun 13 03:18:41 PM PDT 24
Finished Jun 13 03:21:30 PM PDT 24
Peak memory 260916 kb
Host smart-5dab2e7b-d3ac-478c-981c-840d083b20ec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388
7410396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3887410396
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.3030142811
Short name T69
Test name
Test status
Simulation time 3836794300 ps
CPU time 63.15 seconds
Started Jun 13 03:18:29 PM PDT 24
Finished Jun 13 03:19:33 PM PDT 24
Peak memory 263376 kb
Host smart-acc0ad09-3702-49ab-9d3c-a345ddc43602
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030142811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.3030142811
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.473332051
Short name T503
Test name
Test status
Simulation time 30699000 ps
CPU time 13.43 seconds
Started Jun 13 03:18:46 PM PDT 24
Finished Jun 13 03:19:01 PM PDT 24
Peak memory 265384 kb
Host smart-a24f4e55-ecee-4cc9-82a0-8327d73ad073
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473332051 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.473332051
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.3124135943
Short name T120
Test name
Test status
Simulation time 12962612500 ps
CPU time 250.94 seconds
Started Jun 13 03:18:24 PM PDT 24
Finished Jun 13 03:22:35 PM PDT 24
Peak memory 275484 kb
Host smart-5726a9d1-980d-4187-bc5f-efd3baedb1cc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124135943 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.3124135943
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3480839244
Short name T595
Test name
Test status
Simulation time 37134600 ps
CPU time 110.16 seconds
Started Jun 13 03:18:23 PM PDT 24
Finished Jun 13 03:20:14 PM PDT 24
Peak memory 265724 kb
Host smart-eeaa74a9-1e1e-4b7f-b90f-48ad040d8397
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480839244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3480839244
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.2261492797
Short name T767
Test name
Test status
Simulation time 3901795000 ps
CPU time 250.86 seconds
Started Jun 13 03:18:37 PM PDT 24
Finished Jun 13 03:22:49 PM PDT 24
Peak memory 282352 kb
Host smart-8c611210-89a2-4efe-949d-0e83aa83b221
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261492797 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2261492797
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.809460808
Short name T58
Test name
Test status
Simulation time 25229600 ps
CPU time 13.89 seconds
Started Jun 13 03:18:47 PM PDT 24
Finished Jun 13 03:19:02 PM PDT 24
Peak memory 279388 kb
Host smart-e0681afa-a363-40d4-bf74-a216e7ee90a4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=809460808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.809460808
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.943284062
Short name T212
Test name
Test status
Simulation time 721471700 ps
CPU time 217.06 seconds
Started Jun 13 03:18:16 PM PDT 24
Finished Jun 13 03:21:55 PM PDT 24
Peak memory 263472 kb
Host smart-9e360c63-dd12-447a-9002-5d2df8e66524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943284062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.943284062
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3712474559
Short name T51
Test name
Test status
Simulation time 937349000 ps
CPU time 17.41 seconds
Started Jun 13 03:18:39 PM PDT 24
Finished Jun 13 03:18:57 PM PDT 24
Peak memory 266008 kb
Host smart-e16a7d06-76f0-4234-9fc2-13d0367aacc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712474559 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3712474559
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.932856081
Short name T205
Test name
Test status
Simulation time 21313600 ps
CPU time 13.85 seconds
Started Jun 13 03:18:44 PM PDT 24
Finished Jun 13 03:18:59 PM PDT 24
Peak memory 266092 kb
Host smart-88a361ed-46d5-446a-87b9-db3aafc31ffc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932856081 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.932856081
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1275643837
Short name T785
Test name
Test status
Simulation time 196912600 ps
CPU time 13.73 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:18:55 PM PDT 24
Peak memory 265792 kb
Host smart-e6f21fcf-b36b-4187-ad0b-904ce3da0405
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275643837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1275643837
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1308501382
Short name T1060
Test name
Test status
Simulation time 99307900 ps
CPU time 440.12 seconds
Started Jun 13 03:18:18 PM PDT 24
Finished Jun 13 03:25:39 PM PDT 24
Peak memory 281996 kb
Host smart-e77c3b1b-01b8-49e5-a6b5-c6bf1279b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308501382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1308501382
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3622810367
Short name T250
Test name
Test status
Simulation time 103519800 ps
CPU time 100.88 seconds
Started Jun 13 03:18:21 PM PDT 24
Finished Jun 13 03:20:02 PM PDT 24
Peak memory 263164 kb
Host smart-4ed2c549-86a9-4cf8-89f2-ab572f6fffed
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3622810367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3622810367
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.4221518357
Short name T613
Test name
Test status
Simulation time 342332500 ps
CPU time 36.78 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:19:18 PM PDT 24
Peak memory 275728 kb
Host smart-02ce38b3-f110-4b2f-b73e-2f5bb24ada65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221518357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.4221518357
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2391252292
Short name T953
Test name
Test status
Simulation time 33019300 ps
CPU time 22.75 seconds
Started Jun 13 03:18:36 PM PDT 24
Finished Jun 13 03:18:59 PM PDT 24
Peak memory 265360 kb
Host smart-cd186914-cf7a-4425-9269-cfd2d676a956
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391252292 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2391252292
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.963802934
Short name T924
Test name
Test status
Simulation time 25910200 ps
CPU time 23.34 seconds
Started Jun 13 03:18:37 PM PDT 24
Finished Jun 13 03:19:00 PM PDT 24
Peak memory 265792 kb
Host smart-4d1e6f40-165e-499d-a92e-49f597df73e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963802934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_read_word_sweep_serr.963802934
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.1165170974
Short name T956
Test name
Test status
Simulation time 517417700 ps
CPU time 119.16 seconds
Started Jun 13 03:18:36 PM PDT 24
Finished Jun 13 03:20:35 PM PDT 24
Peak memory 282332 kb
Host smart-8b3c87a1-814a-4350-8c1a-ccc77424501b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165170974 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.1165170974
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.3618592621
Short name T200
Test name
Test status
Simulation time 1445027800 ps
CPU time 138.05 seconds
Started Jun 13 03:18:34 PM PDT 24
Finished Jun 13 03:20:53 PM PDT 24
Peak memory 283384 kb
Host smart-ad8181ca-d5e0-469c-a84c-a7cabfe0cbbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3618592621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3618592621
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.403584802
Short name T799
Test name
Test status
Simulation time 3777422100 ps
CPU time 128.87 seconds
Started Jun 13 03:18:34 PM PDT 24
Finished Jun 13 03:20:44 PM PDT 24
Peak memory 295316 kb
Host smart-43e35442-566d-4fb2-97d6-19c9c1ee5b85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403584802 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.403584802
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.920072362
Short name T187
Test name
Test status
Simulation time 7111608000 ps
CPU time 640.25 seconds
Started Jun 13 03:18:38 PM PDT 24
Finished Jun 13 03:29:19 PM PDT 24
Peak memory 309820 kb
Host smart-f954b5fa-4c3f-4f78-828e-29d2a05b76e8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920072362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_rw.920072362
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1864557122
Short name T196
Test name
Test status
Simulation time 4705160900 ps
CPU time 619.94 seconds
Started Jun 13 03:18:37 PM PDT 24
Finished Jun 13 03:28:58 PM PDT 24
Peak memory 328048 kb
Host smart-03242696-c650-4810-a52b-af7fea5cbb1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864557122 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1864557122
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.3550124890
Short name T790
Test name
Test status
Simulation time 48474700 ps
CPU time 28.99 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:19:11 PM PDT 24
Peak memory 275892 kb
Host smart-b6a4ee3e-e1b3-44f9-9e39-c93a2b7a7eda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550124890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.3550124890
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2930708215
Short name T788
Test name
Test status
Simulation time 41564500 ps
CPU time 31.1 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:19:13 PM PDT 24
Peak memory 267956 kb
Host smart-828b9c2d-9693-42cd-b1c3-964f440fe51b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930708215 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2930708215
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.3032568603
Short name T880
Test name
Test status
Simulation time 26150522500 ps
CPU time 667.61 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:29:49 PM PDT 24
Peak memory 321360 kb
Host smart-14a6aef0-969c-4c5b-82db-b78570fd7dc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032568603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.3032568603
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.303089533
Short name T16
Test name
Test status
Simulation time 1160431700 ps
CPU time 4998.89 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 04:42:00 PM PDT 24
Peak memory 284404 kb
Host smart-0bed8e90-bb03-4d0a-87f4-1cee0ff594b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303089533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.303089533
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.333987278
Short name T666
Test name
Test status
Simulation time 633781400 ps
CPU time 52.35 seconds
Started Jun 13 03:18:40 PM PDT 24
Finished Jun 13 03:19:34 PM PDT 24
Peak memory 264072 kb
Host smart-0e5ba6e1-14e8-4847-8dcc-84c362cdaf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333987278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.333987278
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.3454048318
Short name T893
Test name
Test status
Simulation time 14060067900 ps
CPU time 106.22 seconds
Started Jun 13 03:18:34 PM PDT 24
Finished Jun 13 03:20:21 PM PDT 24
Peak memory 266052 kb
Host smart-c618252c-ecd4-4876-8ca7-b5d9d6e2f1f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454048318 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.3454048318
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.2641119836
Short name T39
Test name
Test status
Simulation time 1434843100 ps
CPU time 81 seconds
Started Jun 13 03:18:33 PM PDT 24
Finished Jun 13 03:19:56 PM PDT 24
Peak memory 274164 kb
Host smart-0d3619bd-ba12-42b8-9864-0e5bf3bf3af5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641119836 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.2641119836
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3743699764
Short name T428
Test name
Test status
Simulation time 27894200 ps
CPU time 144.22 seconds
Started Jun 13 03:18:20 PM PDT 24
Finished Jun 13 03:20:45 PM PDT 24
Peak memory 276992 kb
Host smart-b4ad84fc-81a2-4d1f-9ac4-a154470d6886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743699764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3743699764
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.524689144
Short name T771
Test name
Test status
Simulation time 27910100 ps
CPU time 26.24 seconds
Started Jun 13 03:18:17 PM PDT 24
Finished Jun 13 03:18:45 PM PDT 24
Peak memory 260152 kb
Host smart-3a4ab260-0f25-47b6-8a37-d33f37812653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524689144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.524689144
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1744981161
Short name T485
Test name
Test status
Simulation time 3138673100 ps
CPU time 772.57 seconds
Started Jun 13 03:18:41 PM PDT 24
Finished Jun 13 03:31:35 PM PDT 24
Peak memory 284448 kb
Host smart-bf381820-ddb6-4b16-a46d-cedf57ba1853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744981161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1744981161
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.473875703
Short name T391
Test name
Test status
Simulation time 139142800 ps
CPU time 26.69 seconds
Started Jun 13 03:18:20 PM PDT 24
Finished Jun 13 03:18:47 PM PDT 24
Peak memory 260060 kb
Host smart-6508e324-e2d2-4c5b-8a35-27e36dee77eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473875703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.473875703
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.450159016
Short name T430
Test name
Test status
Simulation time 5430486600 ps
CPU time 232.2 seconds
Started Jun 13 03:18:35 PM PDT 24
Finished Jun 13 03:22:28 PM PDT 24
Peak memory 259772 kb
Host smart-fdda0eea-6473-48f6-80a0-e84d708797dd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450159016 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_wo.450159016
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1368192145
Short name T954
Test name
Test status
Simulation time 65595300 ps
CPU time 13.64 seconds
Started Jun 13 03:25:46 PM PDT 24
Finished Jun 13 03:26:01 PM PDT 24
Peak memory 258616 kb
Host smart-ca8b5b95-315a-4c96-ba9d-25da79ce29f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368192145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1368192145
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3093292081
Short name T22
Test name
Test status
Simulation time 46332800 ps
CPU time 16.19 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:25:59 PM PDT 24
Peak memory 275272 kb
Host smart-2673ef4f-fd7a-4d5b-8cb7-5fa114eaae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093292081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3093292081
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2722792982
Short name T866
Test name
Test status
Simulation time 40096900 ps
CPU time 21.84 seconds
Started Jun 13 03:25:41 PM PDT 24
Finished Jun 13 03:26:04 PM PDT 24
Peak memory 274104 kb
Host smart-9152be0b-434d-4209-b032-74988e4b1273
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722792982 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2722792982
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3508411032
Short name T589
Test name
Test status
Simulation time 48235032700 ps
CPU time 253.01 seconds
Started Jun 13 03:25:40 PM PDT 24
Finished Jun 13 03:29:54 PM PDT 24
Peak memory 261520 kb
Host smart-c9dd026e-00b2-477b-9990-d276cee636d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508411032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3508411032
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2869428538
Short name T733
Test name
Test status
Simulation time 6041298000 ps
CPU time 136.93 seconds
Started Jun 13 03:25:40 PM PDT 24
Finished Jun 13 03:27:58 PM PDT 24
Peak memory 293484 kb
Host smart-849e0a25-a5cc-45d0-846e-464dddabbf4f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869428538 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2869428538
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1592040769
Short name T1
Test name
Test status
Simulation time 316351300 ps
CPU time 130.44 seconds
Started Jun 13 03:25:46 PM PDT 24
Finished Jun 13 03:27:57 PM PDT 24
Peak memory 261472 kb
Host smart-4cf94c5e-99fe-477a-9fc4-afd7247b2929
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592040769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1592040769
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.1319860235
Short name T516
Test name
Test status
Simulation time 29037600 ps
CPU time 30.2 seconds
Started Jun 13 03:25:45 PM PDT 24
Finished Jun 13 03:26:15 PM PDT 24
Peak memory 275692 kb
Host smart-148e7b99-07c2-4bdc-8482-72fad24b886b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319860235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.1319860235
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3798295655
Short name T322
Test name
Test status
Simulation time 46068300 ps
CPU time 31.19 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:26:14 PM PDT 24
Peak memory 276148 kb
Host smart-a4cb0db5-739a-4f41-b236-bdf37201001f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798295655 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3798295655
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2832647011
Short name T42
Test name
Test status
Simulation time 11986502600 ps
CPU time 67.51 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:26:50 PM PDT 24
Peak memory 263960 kb
Host smart-f76bac5c-30fd-42f2-a8d6-2c425641131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832647011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2832647011
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.4055878616
Short name T45
Test name
Test status
Simulation time 92420600 ps
CPU time 141.67 seconds
Started Jun 13 03:25:40 PM PDT 24
Finished Jun 13 03:28:03 PM PDT 24
Peak memory 276904 kb
Host smart-e8850394-6a24-470b-af74-45563a25c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055878616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.4055878616
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.1100066452
Short name T545
Test name
Test status
Simulation time 147343600 ps
CPU time 13.69 seconds
Started Jun 13 03:25:49 PM PDT 24
Finished Jun 13 03:26:04 PM PDT 24
Peak memory 265084 kb
Host smart-190f025f-53b7-4614-ac0b-0f7337e63004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100066452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
1100066452
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3403779455
Short name T609
Test name
Test status
Simulation time 37259600 ps
CPU time 15.88 seconds
Started Jun 13 03:25:50 PM PDT 24
Finished Jun 13 03:26:07 PM PDT 24
Peak memory 275200 kb
Host smart-effbd144-9906-45d8-adeb-8c30d238640b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403779455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3403779455
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.2363571756
Short name T963
Test name
Test status
Simulation time 39787300 ps
CPU time 22.01 seconds
Started Jun 13 03:25:48 PM PDT 24
Finished Jun 13 03:26:10 PM PDT 24
Peak memory 265860 kb
Host smart-3639d2e7-9fb7-45ae-a9f5-928aa617d2b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363571756 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.2363571756
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3954772956
Short name T658
Test name
Test status
Simulation time 11324138800 ps
CPU time 97.51 seconds
Started Jun 13 03:25:43 PM PDT 24
Finished Jun 13 03:27:21 PM PDT 24
Peak memory 262996 kb
Host smart-608829e9-ddcd-4e35-8bbf-c21ff6adac32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954772956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3954772956
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1858151467
Short name T1074
Test name
Test status
Simulation time 1542929400 ps
CPU time 203.64 seconds
Started Jun 13 03:26:46 PM PDT 24
Finished Jun 13 03:30:10 PM PDT 24
Peak memory 285344 kb
Host smart-84de7e29-9fab-422d-8031-20cfde2e64e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858151467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1858151467
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1852470615
Short name T763
Test name
Test status
Simulation time 21721623700 ps
CPU time 152.64 seconds
Started Jun 13 03:25:50 PM PDT 24
Finished Jun 13 03:28:24 PM PDT 24
Peak memory 292916 kb
Host smart-9dc1271a-5f93-4e7a-8a52-a534f4674273
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852470615 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1852470615
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.4023727268
Short name T935
Test name
Test status
Simulation time 40738900 ps
CPU time 132.26 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:27:55 PM PDT 24
Peak memory 260376 kb
Host smart-50fea9c3-2d17-4685-bc8d-a18d9bb3b0a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023727268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.4023727268
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2515263366
Short name T768
Test name
Test status
Simulation time 96122700 ps
CPU time 31.55 seconds
Started Jun 13 03:25:50 PM PDT 24
Finished Jun 13 03:26:22 PM PDT 24
Peak memory 267940 kb
Host smart-4b3d99a8-52d1-4f9a-8cd0-03a24d9c9077
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515263366 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2515263366
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.6122508
Short name T245
Test name
Test status
Simulation time 35788700 ps
CPU time 74.97 seconds
Started Jun 13 03:25:42 PM PDT 24
Finished Jun 13 03:26:58 PM PDT 24
Peak memory 277072 kb
Host smart-329e57c3-3f2a-43d1-85fb-4827c87a13ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6122508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.6122508
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.4241726104
Short name T829
Test name
Test status
Simulation time 25456900 ps
CPU time 13.68 seconds
Started Jun 13 03:25:53 PM PDT 24
Finished Jun 13 03:26:08 PM PDT 24
Peak memory 258624 kb
Host smart-865420d1-98a4-4406-9aa0-d3b9b8243028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241726104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
4241726104
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.70468097
Short name T605
Test name
Test status
Simulation time 14536400 ps
CPU time 13.39 seconds
Started Jun 13 03:25:54 PM PDT 24
Finished Jun 13 03:26:08 PM PDT 24
Peak memory 275176 kb
Host smart-fdf7bfa1-f1ef-45bb-9eae-766c69b39aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70468097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.70468097
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.2514200644
Short name T390
Test name
Test status
Simulation time 1510025100 ps
CPU time 63.42 seconds
Started Jun 13 03:25:50 PM PDT 24
Finished Jun 13 03:26:54 PM PDT 24
Peak memory 263416 kb
Host smart-3a23c4f6-6f68-4c2d-b8c5-6d1b2df554f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514200644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.2514200644
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1316687673
Short name T667
Test name
Test status
Simulation time 737520300 ps
CPU time 170.09 seconds
Started Jun 13 03:25:51 PM PDT 24
Finished Jun 13 03:28:42 PM PDT 24
Peak memory 293492 kb
Host smart-b9056ef7-6e5c-445a-8749-6d228c6c0207
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316687673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.1316687673
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1742000180
Short name T746
Test name
Test status
Simulation time 63569258100 ps
CPU time 142.88 seconds
Started Jun 13 03:25:57 PM PDT 24
Finished Jun 13 03:28:21 PM PDT 24
Peak memory 292844 kb
Host smart-3c2ca3bc-9a74-4596-acaa-84900350620d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742000180 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1742000180
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.1540631089
Short name T1094
Test name
Test status
Simulation time 247640700 ps
CPU time 110.53 seconds
Started Jun 13 03:25:49 PM PDT 24
Finished Jun 13 03:27:40 PM PDT 24
Peak memory 260564 kb
Host smart-dd024e54-1fe7-497d-b791-c0dbdf416299
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540631089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.1540631089
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.118432599
Short name T233
Test name
Test status
Simulation time 32334000 ps
CPU time 31.04 seconds
Started Jun 13 03:25:53 PM PDT 24
Finished Jun 13 03:26:26 PM PDT 24
Peak memory 270248 kb
Host smart-76e20a89-f4e2-43cf-b37e-6a7929991926
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118432599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.118432599
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3544397993
Short name T738
Test name
Test status
Simulation time 41167000 ps
CPU time 30.45 seconds
Started Jun 13 03:25:56 PM PDT 24
Finished Jun 13 03:26:27 PM PDT 24
Peak memory 267932 kb
Host smart-03d6e119-279b-4169-9d0e-268f61493265
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544397993 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3544397993
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3504206631
Short name T725
Test name
Test status
Simulation time 7776306700 ps
CPU time 76.13 seconds
Started Jun 13 03:25:52 PM PDT 24
Finished Jun 13 03:27:09 PM PDT 24
Peak memory 263996 kb
Host smart-e70a4fb5-1ec2-4d0b-aca2-9d823f6bca48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504206631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3504206631
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3637173360
Short name T433
Test name
Test status
Simulation time 184481300 ps
CPU time 122.16 seconds
Started Jun 13 03:25:49 PM PDT 24
Finished Jun 13 03:27:52 PM PDT 24
Peak memory 276492 kb
Host smart-1e7756ba-f379-402e-9cd5-d78fa6faa1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637173360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3637173360
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.730195800
Short name T447
Test name
Test status
Simulation time 117689100 ps
CPU time 13.56 seconds
Started Jun 13 03:26:00 PM PDT 24
Finished Jun 13 03:26:15 PM PDT 24
Peak memory 258612 kb
Host smart-9050f94c-3a51-406c-8355-0055d8cdadc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730195800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.730195800
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.985583602
Short name T750
Test name
Test status
Simulation time 17062500 ps
CPU time 16.16 seconds
Started Jun 13 03:26:00 PM PDT 24
Finished Jun 13 03:26:17 PM PDT 24
Peak memory 284676 kb
Host smart-e8faf241-de66-43ad-a320-188c86c472ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985583602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.985583602
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3935420172
Short name T973
Test name
Test status
Simulation time 13292600 ps
CPU time 21.86 seconds
Started Jun 13 03:26:01 PM PDT 24
Finished Jun 13 03:26:24 PM PDT 24
Peak memory 281316 kb
Host smart-ceb647c2-0d7b-496e-989c-67c41916ea9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935420172 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3935420172
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.2113542716
Short name T854
Test name
Test status
Simulation time 4979073800 ps
CPU time 102.56 seconds
Started Jun 13 03:25:54 PM PDT 24
Finished Jun 13 03:27:37 PM PDT 24
Peak memory 261388 kb
Host smart-40bdcdb1-cbb9-4834-ac11-49289a0b7fa7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113542716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.2113542716
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1536122093
Short name T1065
Test name
Test status
Simulation time 23412979500 ps
CPU time 123.9 seconds
Started Jun 13 03:26:00 PM PDT 24
Finished Jun 13 03:28:05 PM PDT 24
Peak memory 293488 kb
Host smart-0a3e26bd-d7c0-4471-bdd0-c712a78f9328
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536122093 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1536122093
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1063679221
Short name T236
Test name
Test status
Simulation time 100283100 ps
CPU time 110.42 seconds
Started Jun 13 03:25:54 PM PDT 24
Finished Jun 13 03:27:45 PM PDT 24
Peak memory 261456 kb
Host smart-24997830-d1c2-4ca2-b358-40ba8c884661
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063679221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1063679221
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3381418083
Short name T626
Test name
Test status
Simulation time 282029100 ps
CPU time 31.38 seconds
Started Jun 13 03:26:02 PM PDT 24
Finished Jun 13 03:26:34 PM PDT 24
Peak memory 275752 kb
Host smart-0bec786c-0eee-4717-a4dd-8eaa44968d1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381418083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3381418083
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.844728437
Short name T533
Test name
Test status
Simulation time 30766100 ps
CPU time 30.73 seconds
Started Jun 13 03:25:59 PM PDT 24
Finished Jun 13 03:26:31 PM PDT 24
Peak memory 276592 kb
Host smart-082c3417-ae2c-465c-99d6-c65e974131fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844728437 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.844728437
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.197444147
Short name T369
Test name
Test status
Simulation time 17681974800 ps
CPU time 70.75 seconds
Started Jun 13 03:26:00 PM PDT 24
Finished Jun 13 03:27:12 PM PDT 24
Peak memory 265108 kb
Host smart-2acd4030-797e-424c-9b54-562cfa7c2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197444147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.197444147
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.661051760
Short name T44
Test name
Test status
Simulation time 64790900 ps
CPU time 49.53 seconds
Started Jun 13 03:25:57 PM PDT 24
Finished Jun 13 03:26:48 PM PDT 24
Peak memory 271480 kb
Host smart-c4653185-4306-4ccf-8ea6-16bc76aca364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661051760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.661051760
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.563836156
Short name T599
Test name
Test status
Simulation time 62153400 ps
CPU time 13.91 seconds
Started Jun 13 03:26:08 PM PDT 24
Finished Jun 13 03:26:23 PM PDT 24
Peak memory 265560 kb
Host smart-4fd44c93-94c4-45bc-a835-a994a22da66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563836156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.563836156
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.94183793
Short name T520
Test name
Test status
Simulation time 16717600 ps
CPU time 13.62 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:26:24 PM PDT 24
Peak memory 275252 kb
Host smart-ef950f78-cca3-41dd-96d0-c13416d1cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94183793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.94183793
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.759338993
Short name T916
Test name
Test status
Simulation time 14920000 ps
CPU time 21.57 seconds
Started Jun 13 03:26:05 PM PDT 24
Finished Jun 13 03:26:27 PM PDT 24
Peak memory 274216 kb
Host smart-0fb2b8b5-f6cb-4433-8bc5-1ab866bee541
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759338993 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.759338993
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1108405509
Short name T406
Test name
Test status
Simulation time 10239749300 ps
CPU time 122.77 seconds
Started Jun 13 03:26:01 PM PDT 24
Finished Jun 13 03:28:05 PM PDT 24
Peak memory 263632 kb
Host smart-63cd4b01-1ac9-4c72-a548-be16abdc1d01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108405509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1108405509
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.2499751013
Short name T1063
Test name
Test status
Simulation time 4717402600 ps
CPU time 156.38 seconds
Started Jun 13 03:26:00 PM PDT 24
Finished Jun 13 03:28:37 PM PDT 24
Peak memory 294612 kb
Host smart-a11a4216-d9df-4ae3-ab74-b4671a9d75af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499751013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.2499751013
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.68080448
Short name T308
Test name
Test status
Simulation time 50528702200 ps
CPU time 314.81 seconds
Started Jun 13 03:26:05 PM PDT 24
Finished Jun 13 03:31:20 PM PDT 24
Peak memory 285392 kb
Host smart-1c0fcdc1-5ceb-4e5c-bcd2-0d2dcebc4730
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68080448 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.68080448
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2434037223
Short name T1037
Test name
Test status
Simulation time 80433400 ps
CPU time 110.55 seconds
Started Jun 13 03:25:59 PM PDT 24
Finished Jun 13 03:27:51 PM PDT 24
Peak memory 261416 kb
Host smart-822d5a11-47a1-4183-91b9-d36db9d349ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434037223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2434037223
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1236179767
Short name T522
Test name
Test status
Simulation time 364214200 ps
CPU time 58.63 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:27:10 PM PDT 24
Peak memory 265072 kb
Host smart-c535b1f5-a834-4c2b-b2ed-5d7083869be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236179767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1236179767
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.704368979
Short name T630
Test name
Test status
Simulation time 78979700 ps
CPU time 122.54 seconds
Started Jun 13 03:26:01 PM PDT 24
Finished Jun 13 03:28:04 PM PDT 24
Peak memory 276900 kb
Host smart-5803bc1f-5a29-4e30-bc5b-77252c707843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704368979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.704368979
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.413220454
Short name T580
Test name
Test status
Simulation time 38658600 ps
CPU time 13.86 seconds
Started Jun 13 03:26:16 PM PDT 24
Finished Jun 13 03:26:32 PM PDT 24
Peak memory 258688 kb
Host smart-4ac52503-fa86-4919-80c7-ea5edadfaa26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413220454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.413220454
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.4036248967
Short name T806
Test name
Test status
Simulation time 19011800 ps
CPU time 15.73 seconds
Started Jun 13 03:26:11 PM PDT 24
Finished Jun 13 03:26:27 PM PDT 24
Peak memory 275408 kb
Host smart-8468e07f-44e2-48d2-af37-699aca498648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036248967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.4036248967
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.3796725992
Short name T347
Test name
Test status
Simulation time 29475300 ps
CPU time 21.84 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:26:33 PM PDT 24
Peak memory 274156 kb
Host smart-144cfa77-098a-430c-ba62-e9b178748a3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796725992 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.3796725992
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3005190566
Short name T662
Test name
Test status
Simulation time 9831485900 ps
CPU time 92.11 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:27:43 PM PDT 24
Peak memory 263084 kb
Host smart-ac063f56-31b0-412c-84e7-83ce4924b6cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005190566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3005190566
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.588801753
Short name T754
Test name
Test status
Simulation time 3030858300 ps
CPU time 189.86 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:29:21 PM PDT 24
Peak memory 285024 kb
Host smart-fc03ecb9-d613-4e86-bd9c-4b1d19daa18b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588801753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.588801753
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3696109841
Short name T751
Test name
Test status
Simulation time 11511679800 ps
CPU time 152.76 seconds
Started Jun 13 03:26:12 PM PDT 24
Finished Jun 13 03:28:45 PM PDT 24
Peak memory 293488 kb
Host smart-6691eade-5271-470d-836e-8de0700a0a71
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696109841 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3696109841
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.586507318
Short name T851
Test name
Test status
Simulation time 183156300 ps
CPU time 133.61 seconds
Started Jun 13 03:26:09 PM PDT 24
Finished Jun 13 03:28:23 PM PDT 24
Peak memory 261404 kb
Host smart-a2a0bf4c-0bc6-4367-a06f-2dff4af497cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586507318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.586507318
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.2931405294
Short name T41
Test name
Test status
Simulation time 32903100 ps
CPU time 31.01 seconds
Started Jun 13 03:26:09 PM PDT 24
Finished Jun 13 03:26:40 PM PDT 24
Peak memory 277768 kb
Host smart-90480ff9-b578-4d95-b0f9-39a80bc793a6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931405294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.2931405294
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1911939568
Short name T131
Test name
Test status
Simulation time 44139300 ps
CPU time 30.97 seconds
Started Jun 13 03:26:12 PM PDT 24
Finished Jun 13 03:26:43 PM PDT 24
Peak memory 268048 kb
Host smart-dc6f55f5-c686-4d3a-b2cc-dae538959e40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911939568 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1911939568
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1737531167
Short name T827
Test name
Test status
Simulation time 7028549200 ps
CPU time 78.78 seconds
Started Jun 13 03:26:12 PM PDT 24
Finished Jun 13 03:27:32 PM PDT 24
Peak memory 264012 kb
Host smart-715f2073-40ea-40c7-a349-29507ad9649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737531167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1737531167
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.473727598
Short name T249
Test name
Test status
Simulation time 43330800 ps
CPU time 75.8 seconds
Started Jun 13 03:26:10 PM PDT 24
Finished Jun 13 03:27:26 PM PDT 24
Peak memory 275844 kb
Host smart-d96253fd-1f87-4ce9-bf77-7256e42a5923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473727598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.473727598
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3641369300
Short name T637
Test name
Test status
Simulation time 82494200 ps
CPU time 14.4 seconds
Started Jun 13 03:26:23 PM PDT 24
Finished Jun 13 03:26:39 PM PDT 24
Peak memory 265656 kb
Host smart-528c641b-bc21-4ab8-a349-6aec07c29d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641369300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3641369300
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.676040409
Short name T416
Test name
Test status
Simulation time 13935100 ps
CPU time 16.2 seconds
Started Jun 13 03:26:17 PM PDT 24
Finished Jun 13 03:26:35 PM PDT 24
Peak memory 275304 kb
Host smart-95f1b644-52e4-4d6f-b6cf-26d8381b082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676040409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.676040409
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.2685829001
Short name T689
Test name
Test status
Simulation time 10347900 ps
CPU time 20.7 seconds
Started Jun 13 03:26:17 PM PDT 24
Finished Jun 13 03:26:39 PM PDT 24
Peak memory 265936 kb
Host smart-e3d889ae-7922-4442-af0a-53a8ea041844
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685829001 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.2685829001
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3922094900
Short name T462
Test name
Test status
Simulation time 1100980900 ps
CPU time 49.86 seconds
Started Jun 13 03:26:17 PM PDT 24
Finished Jun 13 03:27:09 PM PDT 24
Peak memory 263004 kb
Host smart-ebc134da-06d7-4bff-a18f-d8d9b356d55d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922094900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3922094900
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.2395395305
Short name T774
Test name
Test status
Simulation time 20725528100 ps
CPU time 280.39 seconds
Started Jun 13 03:26:19 PM PDT 24
Finished Jun 13 03:31:01 PM PDT 24
Peak memory 285168 kb
Host smart-992b7e9e-065b-4caa-a9b5-1b958c85eac3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395395305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.2395395305
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1770052887
Short name T929
Test name
Test status
Simulation time 70728694200 ps
CPU time 273.18 seconds
Started Jun 13 03:26:19 PM PDT 24
Finished Jun 13 03:30:53 PM PDT 24
Peak memory 291480 kb
Host smart-1335104f-d480-429b-aae9-f91ba063be4f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770052887 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.1770052887
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.3716074754
Short name T949
Test name
Test status
Simulation time 42577300 ps
CPU time 130.85 seconds
Started Jun 13 03:26:17 PM PDT 24
Finished Jun 13 03:28:30 PM PDT 24
Peak memory 265504 kb
Host smart-27f6fced-b3a1-4adc-85bf-309e72fe80ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716074754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.3716074754
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2367250459
Short name T1055
Test name
Test status
Simulation time 43541600 ps
CPU time 31.17 seconds
Started Jun 13 03:26:19 PM PDT 24
Finished Jun 13 03:26:51 PM PDT 24
Peak memory 277152 kb
Host smart-13375b7e-0b87-4fc8-8da8-2f6ff88fedc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367250459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2367250459
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3546799714
Short name T729
Test name
Test status
Simulation time 157291900 ps
CPU time 31.36 seconds
Started Jun 13 03:26:17 PM PDT 24
Finished Jun 13 03:26:50 PM PDT 24
Peak memory 268016 kb
Host smart-d2132e9e-25f1-4eb6-8810-11d7a42a24f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546799714 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3546799714
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.81789252
Short name T920
Test name
Test status
Simulation time 526185800 ps
CPU time 61.87 seconds
Started Jun 13 03:26:16 PM PDT 24
Finished Jun 13 03:27:20 PM PDT 24
Peak memory 263516 kb
Host smart-201e46a6-3dca-4d60-a435-3852499b6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81789252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.81789252
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.1719426426
Short name T230
Test name
Test status
Simulation time 80391700 ps
CPU time 170.67 seconds
Started Jun 13 03:26:16 PM PDT 24
Finished Jun 13 03:29:09 PM PDT 24
Peak memory 278432 kb
Host smart-16bd0f2c-474b-4c94-a0eb-f0cb7d4821f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719426426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1719426426
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1298150001
Short name T418
Test name
Test status
Simulation time 37743000 ps
CPU time 13.98 seconds
Started Jun 13 03:26:29 PM PDT 24
Finished Jun 13 03:26:44 PM PDT 24
Peak memory 258688 kb
Host smart-46b15521-c125-466e-8ba8-1e1f699111f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298150001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1298150001
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.3445078839
Short name T797
Test name
Test status
Simulation time 16292000 ps
CPU time 15.78 seconds
Started Jun 13 03:26:27 PM PDT 24
Finished Jun 13 03:26:43 PM PDT 24
Peak memory 275296 kb
Host smart-73aebefb-aeb6-40fc-8820-e5b93571f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445078839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3445078839
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2380741105
Short name T756
Test name
Test status
Simulation time 25145300 ps
CPU time 20.16 seconds
Started Jun 13 03:26:28 PM PDT 24
Finished Jun 13 03:26:49 PM PDT 24
Peak memory 274124 kb
Host smart-222e8b92-6b09-478d-86c8-8fac2597ad4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380741105 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2380741105
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1743814212
Short name T616
Test name
Test status
Simulation time 1346302000 ps
CPU time 111.97 seconds
Started Jun 13 03:26:21 PM PDT 24
Finished Jun 13 03:28:14 PM PDT 24
Peak memory 263048 kb
Host smart-cb7348ff-63df-4381-98d3-7262d021c333
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743814212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1743814212
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.373121723
Short name T941
Test name
Test status
Simulation time 812046000 ps
CPU time 131.69 seconds
Started Jun 13 03:26:22 PM PDT 24
Finished Jun 13 03:28:35 PM PDT 24
Peak memory 294568 kb
Host smart-098741d0-da9c-46b9-9456-9f77432901cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373121723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas
h_ctrl_intr_rd.373121723
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.4065860040
Short name T1052
Test name
Test status
Simulation time 5754289100 ps
CPU time 147.95 seconds
Started Jun 13 03:26:23 PM PDT 24
Finished Jun 13 03:28:53 PM PDT 24
Peak memory 293324 kb
Host smart-2089d103-2f00-41f9-84fc-39cec0e15a8f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065860040 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.4065860040
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2766525513
Short name T11
Test name
Test status
Simulation time 309399500 ps
CPU time 130.48 seconds
Started Jun 13 03:26:23 PM PDT 24
Finished Jun 13 03:28:35 PM PDT 24
Peak memory 260412 kb
Host smart-df805c70-8419-46f1-8213-a28ac1ad7114
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766525513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2766525513
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2992924299
Short name T473
Test name
Test status
Simulation time 54613300 ps
CPU time 28.8 seconds
Started Jun 13 03:26:24 PM PDT 24
Finished Jun 13 03:26:54 PM PDT 24
Peak memory 275896 kb
Host smart-0013007e-ec02-4304-a641-e26e4c11552f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992924299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2992924299
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3546194196
Short name T471
Test name
Test status
Simulation time 51023400 ps
CPU time 31.02 seconds
Started Jun 13 03:26:30 PM PDT 24
Finished Jun 13 03:27:02 PM PDT 24
Peak memory 268296 kb
Host smart-84c7d1c1-9655-448f-b18a-2bb25317bebd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546194196 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3546194196
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1940307094
Short name T452
Test name
Test status
Simulation time 2029340900 ps
CPU time 71.52 seconds
Started Jun 13 03:26:28 PM PDT 24
Finished Jun 13 03:27:42 PM PDT 24
Peak memory 264192 kb
Host smart-f17cc895-26ed-41e5-96f2-b5747f89039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940307094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1940307094
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.364802658
Short name T997
Test name
Test status
Simulation time 93442700 ps
CPU time 193.9 seconds
Started Jun 13 03:26:23 PM PDT 24
Finished Jun 13 03:29:39 PM PDT 24
Peak memory 277600 kb
Host smart-09113199-8860-413a-808d-d08d52395717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364802658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.364802658
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.35287589
Short name T714
Test name
Test status
Simulation time 67518300 ps
CPU time 13.46 seconds
Started Jun 13 03:26:35 PM PDT 24
Finished Jun 13 03:26:50 PM PDT 24
Peak memory 258616 kb
Host smart-891ba8cb-51e3-4bd6-8d7c-c443eca87087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35287589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.35287589
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.2506601717
Short name T824
Test name
Test status
Simulation time 14826300 ps
CPU time 15.74 seconds
Started Jun 13 03:26:33 PM PDT 24
Finished Jun 13 03:26:51 PM PDT 24
Peak memory 275112 kb
Host smart-e943c022-dc80-485a-a5b0-3308f202dd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506601717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2506601717
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.4149489509
Short name T864
Test name
Test status
Simulation time 12371700 ps
CPU time 22.51 seconds
Started Jun 13 03:26:30 PM PDT 24
Finished Jun 13 03:26:54 PM PDT 24
Peak memory 274072 kb
Host smart-09df0887-04ef-460f-8b3a-214a71f853b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149489509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.4149489509
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2622767386
Short name T83
Test name
Test status
Simulation time 3477158300 ps
CPU time 33.38 seconds
Started Jun 13 03:26:30 PM PDT 24
Finished Jun 13 03:27:04 PM PDT 24
Peak memory 263504 kb
Host smart-478ab270-89c8-4455-abc2-714230ac4de3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622767386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2622767386
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.1529909386
Short name T304
Test name
Test status
Simulation time 6085095900 ps
CPU time 187.43 seconds
Started Jun 13 03:26:29 PM PDT 24
Finished Jun 13 03:29:38 PM PDT 24
Peak memory 285816 kb
Host smart-e59f8203-bacd-49da-9849-fc7a2d759f7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529909386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.1529909386
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1334881258
Short name T407
Test name
Test status
Simulation time 23194679600 ps
CPU time 158.81 seconds
Started Jun 13 03:26:28 PM PDT 24
Finished Jun 13 03:29:08 PM PDT 24
Peak memory 293504 kb
Host smart-b6329f4b-f96a-4f66-875b-f515397fac1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334881258 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1334881258
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1241294853
Short name T13
Test name
Test status
Simulation time 41660100 ps
CPU time 134.99 seconds
Started Jun 13 03:26:29 PM PDT 24
Finished Jun 13 03:28:45 PM PDT 24
Peak memory 263876 kb
Host smart-6fef332d-f788-41b6-9b2f-17f6346c66a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241294853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1241294853
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1697549436
Short name T906
Test name
Test status
Simulation time 38559400 ps
CPU time 30.56 seconds
Started Jun 13 03:26:29 PM PDT 24
Finished Jun 13 03:27:01 PM PDT 24
Peak memory 275876 kb
Host smart-ebbb1ccf-8f4a-458e-80a3-82c35b51bcc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697549436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1697549436
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.3605008291
Short name T791
Test name
Test status
Simulation time 42296900 ps
CPU time 32.33 seconds
Started Jun 13 03:26:28 PM PDT 24
Finished Jun 13 03:27:01 PM PDT 24
Peak memory 273516 kb
Host smart-74934878-77ce-4dd7-abf5-aec2f09a0a1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605008291 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.3605008291
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.4070203291
Short name T362
Test name
Test status
Simulation time 2379275000 ps
CPU time 63.55 seconds
Started Jun 13 03:26:35 PM PDT 24
Finished Jun 13 03:27:40 PM PDT 24
Peak memory 264048 kb
Host smart-5e83bf2a-ef10-464a-8ddb-dd7348c9762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070203291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.4070203291
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3120194736
Short name T412
Test name
Test status
Simulation time 153489400 ps
CPU time 76.1 seconds
Started Jun 13 03:26:29 PM PDT 24
Finished Jun 13 03:27:46 PM PDT 24
Peak memory 275916 kb
Host smart-c7f8a184-ee3e-435f-8289-b3fb8a8d314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120194736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3120194736
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3756876978
Short name T1041
Test name
Test status
Simulation time 36613700 ps
CPU time 13.7 seconds
Started Jun 13 03:26:40 PM PDT 24
Finished Jun 13 03:26:55 PM PDT 24
Peak memory 258764 kb
Host smart-31f8bf53-4421-4690-a747-03552643a898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756876978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3756876978
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3141822371
Short name T734
Test name
Test status
Simulation time 16693200 ps
CPU time 16.1 seconds
Started Jun 13 03:26:46 PM PDT 24
Finished Jun 13 03:27:03 PM PDT 24
Peak memory 275184 kb
Host smart-8aa83ca4-10e6-4e6e-8869-e9ba2e6f4aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141822371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3141822371
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.592227552
Short name T352
Test name
Test status
Simulation time 14781800 ps
CPU time 20.74 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:27:03 PM PDT 24
Peak memory 266148 kb
Host smart-2fea2d61-26f9-4796-99df-0769f0e4cab7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592227552 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.592227552
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.90280771
Short name T857
Test name
Test status
Simulation time 7802452900 ps
CPU time 165.55 seconds
Started Jun 13 03:26:34 PM PDT 24
Finished Jun 13 03:29:21 PM PDT 24
Peak memory 263508 kb
Host smart-9f303344-3f3d-4f8c-a2d0-f3aa19afaa4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90280771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw
_sec_otp.90280771
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1678049675
Short name T980
Test name
Test status
Simulation time 1942791700 ps
CPU time 229.48 seconds
Started Jun 13 03:26:33 PM PDT 24
Finished Jun 13 03:30:24 PM PDT 24
Peak memory 291680 kb
Host smart-bb351abf-8336-4f14-b894-b43ecb16bf6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678049675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1678049675
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2144239938
Short name T315
Test name
Test status
Simulation time 115097574300 ps
CPU time 280.03 seconds
Started Jun 13 03:26:35 PM PDT 24
Finished Jun 13 03:31:16 PM PDT 24
Peak memory 291416 kb
Host smart-208da3d4-144f-49ad-8547-666a139976ec
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144239938 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2144239938
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1361902352
Short name T793
Test name
Test status
Simulation time 148642200 ps
CPU time 109.84 seconds
Started Jun 13 03:26:33 PM PDT 24
Finished Jun 13 03:28:25 PM PDT 24
Peak memory 260444 kb
Host smart-bd6afc3d-8252-4013-9729-71103fa1610d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361902352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1361902352
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2640449912
Short name T477
Test name
Test status
Simulation time 83457100 ps
CPU time 31.94 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:27:14 PM PDT 24
Peak memory 268200 kb
Host smart-2607d94a-71fa-46cb-ab0d-8c2d61a280bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640449912 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2640449912
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.2597943728
Short name T1073
Test name
Test status
Simulation time 2507161800 ps
CPU time 84.88 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:28:07 PM PDT 24
Peak memory 264620 kb
Host smart-cb677cf1-5be1-4801-8601-5cc257051b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597943728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2597943728
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1564236207
Short name T434
Test name
Test status
Simulation time 68553300 ps
CPU time 173.64 seconds
Started Jun 13 03:26:34 PM PDT 24
Finished Jun 13 03:29:29 PM PDT 24
Peak memory 277572 kb
Host smart-f6a73c03-346d-440d-9cd9-049583880e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564236207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1564236207
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.168617674
Short name T398
Test name
Test status
Simulation time 60175300 ps
CPU time 13.94 seconds
Started Jun 13 03:19:35 PM PDT 24
Finished Jun 13 03:19:50 PM PDT 24
Peak memory 258692 kb
Host smart-b93b80f2-3ad3-4fa6-96bf-33ce488ff62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168617674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.168617674
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3824398441
Short name T948
Test name
Test status
Simulation time 37211700 ps
CPU time 13.65 seconds
Started Jun 13 03:19:32 PM PDT 24
Finished Jun 13 03:19:46 PM PDT 24
Peak memory 261892 kb
Host smart-4126dc8c-df63-4d20-9273-6a88b30b4bbf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824398441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3824398441
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3094184181
Short name T1083
Test name
Test status
Simulation time 51361700 ps
CPU time 15.8 seconds
Started Jun 13 03:19:20 PM PDT 24
Finished Jun 13 03:19:37 PM PDT 24
Peak memory 275180 kb
Host smart-68b85d72-41b2-4d7d-8514-b03712eca109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094184181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3094184181
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.172304760
Short name T1003
Test name
Test status
Simulation time 116865100 ps
CPU time 104.45 seconds
Started Jun 13 03:19:10 PM PDT 24
Finished Jun 13 03:20:56 PM PDT 24
Peak memory 282336 kb
Host smart-9436a47a-1f2b-4aaf-8eb5-db989cbbbdb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172304760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_derr_detect.172304760
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2153422536
Short name T496
Test name
Test status
Simulation time 18532500 ps
CPU time 21.91 seconds
Started Jun 13 03:19:23 PM PDT 24
Finished Jun 13 03:19:46 PM PDT 24
Peak memory 274172 kb
Host smart-62439020-0383-446e-8ea8-9f90cd1ab46c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153422536 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2153422536
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3972319954
Short name T144
Test name
Test status
Simulation time 8513184600 ps
CPU time 426.73 seconds
Started Jun 13 03:18:55 PM PDT 24
Finished Jun 13 03:26:03 PM PDT 24
Peak memory 263704 kb
Host smart-c7be11d0-f3e8-4c1e-a785-df217027e6d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3972319954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3972319954
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.1947299626
Short name T994
Test name
Test status
Simulation time 83009576900 ps
CPU time 2643.42 seconds
Started Jun 13 03:19:00 PM PDT 24
Finished Jun 13 04:03:04 PM PDT 24
Peak memory 263092 kb
Host smart-81490389-7d24-4001-af1a-fbd829aa30ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947299626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.1947299626
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.600925105
Short name T75
Test name
Test status
Simulation time 3662909100 ps
CPU time 2194.04 seconds
Started Jun 13 03:19:01 PM PDT 24
Finished Jun 13 03:55:36 PM PDT 24
Peak memory 264140 kb
Host smart-d9f92be5-fcc9-4e64-915f-b36559d2e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600925105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.600925105
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.2997252529
Short name T795
Test name
Test status
Simulation time 1939140000 ps
CPU time 856.95 seconds
Started Jun 13 03:18:59 PM PDT 24
Finished Jun 13 03:33:16 PM PDT 24
Peak memory 273788 kb
Host smart-d35e73ad-c184-49b4-83ed-48a69a6d9767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997252529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2997252529
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2968641107
Short name T1079
Test name
Test status
Simulation time 246930400 ps
CPU time 20.67 seconds
Started Jun 13 03:18:58 PM PDT 24
Finished Jun 13 03:19:19 PM PDT 24
Peak memory 262888 kb
Host smart-440be632-9566-42fc-9827-cd9a3fd2a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968641107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2968641107
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.3218854714
Short name T71
Test name
Test status
Simulation time 3061792500 ps
CPU time 43.32 seconds
Started Jun 13 03:19:23 PM PDT 24
Finished Jun 13 03:20:07 PM PDT 24
Peak memory 265616 kb
Host smart-917b21b6-500e-46b0-bd03-eb99fef0c17a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218854714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.3218854714
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.3303354119
Short name T119
Test name
Test status
Simulation time 175471385700 ps
CPU time 2550.57 seconds
Started Jun 13 03:18:58 PM PDT 24
Finished Jun 13 04:01:30 PM PDT 24
Peak memory 265788 kb
Host smart-1f9a059e-6096-4a41-87af-308876ac1990
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303354119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.3303354119
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.3526406664
Short name T835
Test name
Test status
Simulation time 416269000 ps
CPU time 114.25 seconds
Started Jun 13 03:18:52 PM PDT 24
Finished Jun 13 03:20:47 PM PDT 24
Peak memory 265688 kb
Host smart-68875654-2c4c-4a18-97f6-a9f5a6a69b66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526406664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3526406664
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1479725618
Short name T271
Test name
Test status
Simulation time 10012281500 ps
CPU time 99.18 seconds
Started Jun 13 03:19:42 PM PDT 24
Finished Jun 13 03:21:22 PM PDT 24
Peak memory 283592 kb
Host smart-15d4ea04-b02b-4d3a-a80d-054ddc40da18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479725618 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1479725618
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2217611006
Short name T744
Test name
Test status
Simulation time 28999100 ps
CPU time 13.27 seconds
Started Jun 13 03:19:30 PM PDT 24
Finished Jun 13 03:19:44 PM PDT 24
Peak memory 259848 kb
Host smart-2cf5bcec-65d1-43be-b470-41897c1645d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217611006 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2217611006
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2006849247
Short name T566
Test name
Test status
Simulation time 40126168400 ps
CPU time 880.75 seconds
Started Jun 13 03:19:02 PM PDT 24
Finished Jun 13 03:33:43 PM PDT 24
Peak memory 264588 kb
Host smart-3303cf14-d1ee-4218-8610-4a497443e47f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006849247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2006849247
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.175980122
Short name T723
Test name
Test status
Simulation time 12770441600 ps
CPU time 264.95 seconds
Started Jun 13 03:18:53 PM PDT 24
Finished Jun 13 03:23:18 PM PDT 24
Peak memory 263548 kb
Host smart-e4a03d4f-ac70-4582-bb48-6ebad8200ce6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175980122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw
_sec_otp.175980122
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.4213283508
Short name T660
Test name
Test status
Simulation time 834062100 ps
CPU time 167.22 seconds
Started Jun 13 03:19:16 PM PDT 24
Finished Jun 13 03:22:04 PM PDT 24
Peak memory 293508 kb
Host smart-becfc421-1a41-4bac-ba6e-c2db08838df2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213283508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.4213283508
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.4155381243
Short name T673
Test name
Test status
Simulation time 26895239600 ps
CPU time 259.55 seconds
Started Jun 13 03:19:17 PM PDT 24
Finished Jun 13 03:23:37 PM PDT 24
Peak memory 294540 kb
Host smart-3ef1822d-1325-49db-90ed-9deb43d2025d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155381243 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.4155381243
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.2230536981
Short name T1086
Test name
Test status
Simulation time 8525120800 ps
CPU time 75.96 seconds
Started Jun 13 03:19:16 PM PDT 24
Finished Jun 13 03:20:33 PM PDT 24
Peak memory 265484 kb
Host smart-f20b0a9f-4394-4b83-b7af-c69b91b490e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230536981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.2230536981
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.987816863
Short name T27
Test name
Test status
Simulation time 17409404700 ps
CPU time 157.26 seconds
Started Jun 13 03:19:17 PM PDT 24
Finished Jun 13 03:21:55 PM PDT 24
Peak memory 260288 kb
Host smart-df99a775-3873-4615-b71d-079264e921c7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987
816863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.987816863
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1623051038
Short name T1038
Test name
Test status
Simulation time 3906172500 ps
CPU time 101.76 seconds
Started Jun 13 03:19:06 PM PDT 24
Finished Jun 13 03:20:48 PM PDT 24
Peak memory 260976 kb
Host smart-53736898-5bf9-4d30-bd1a-7759c72fef95
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623051038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1623051038
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.4037723230
Short name T982
Test name
Test status
Simulation time 15351900 ps
CPU time 14.28 seconds
Started Jun 13 03:19:30 PM PDT 24
Finished Jun 13 03:19:45 PM PDT 24
Peak memory 260332 kb
Host smart-a28cbf71-0d51-4951-81c3-970524e4ab8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037723230 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.4037723230
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.3054267885
Short name T150
Test name
Test status
Simulation time 857409200 ps
CPU time 75.26 seconds
Started Jun 13 03:19:06 PM PDT 24
Finished Jun 13 03:20:22 PM PDT 24
Peak memory 260848 kb
Host smart-3dc72806-a044-4ad9-a87f-7939b7306dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054267885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3054267885
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.397498840
Short name T959
Test name
Test status
Simulation time 27565404100 ps
CPU time 907.86 seconds
Started Jun 13 03:18:58 PM PDT 24
Finished Jun 13 03:34:07 PM PDT 24
Peak memory 275280 kb
Host smart-71540445-ae38-4afb-818a-902d1df01fc2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397498840 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_mp_regions.397498840
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1431968262
Short name T155
Test name
Test status
Simulation time 119023500 ps
CPU time 111.69 seconds
Started Jun 13 03:19:00 PM PDT 24
Finished Jun 13 03:20:52 PM PDT 24
Peak memory 261436 kb
Host smart-1d83f034-a166-441d-baa2-16d154be164b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431968262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1431968262
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3296149828
Short name T507
Test name
Test status
Simulation time 8144415300 ps
CPU time 224.03 seconds
Started Jun 13 03:19:12 PM PDT 24
Finished Jun 13 03:22:56 PM PDT 24
Peak memory 295620 kb
Host smart-af73990b-c586-4784-a4ed-c273db1b29f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296149828 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3296149828
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.569682863
Short name T492
Test name
Test status
Simulation time 137675200 ps
CPU time 191.99 seconds
Started Jun 13 03:18:55 PM PDT 24
Finished Jun 13 03:22:08 PM PDT 24
Peak memory 263464 kb
Host smart-f0bf1e11-294b-401a-9652-0e0767d0c1aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=569682863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.569682863
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.477528930
Short name T607
Test name
Test status
Simulation time 19966400 ps
CPU time 13.71 seconds
Started Jun 13 03:19:16 PM PDT 24
Finished Jun 13 03:19:30 PM PDT 24
Peak memory 265576 kb
Host smart-a19d967b-573f-4151-a53c-3f571ec509b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477528930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.477528930
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3101692063
Short name T881
Test name
Test status
Simulation time 106201900 ps
CPU time 148.88 seconds
Started Jun 13 03:18:55 PM PDT 24
Finished Jun 13 03:21:25 PM PDT 24
Peak memory 278456 kb
Host smart-db44fc5a-04ad-4b6d-90ab-d707aa9d2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101692063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3101692063
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.1532968325
Short name T61
Test name
Test status
Simulation time 145038500 ps
CPU time 100.38 seconds
Started Jun 13 03:18:54 PM PDT 24
Finished Jun 13 03:20:36 PM PDT 24
Peak memory 262972 kb
Host smart-ac396df0-9837-49f3-b9c1-ca5c20c916c5
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532968325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1532968325
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.339152001
Short name T561
Test name
Test status
Simulation time 699415100 ps
CPU time 35.05 seconds
Started Jun 13 03:19:23 PM PDT 24
Finished Jun 13 03:19:58 PM PDT 24
Peak memory 275840 kb
Host smart-0cfdd8b0-da87-4a62-9250-20e3f4763663
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339152001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_re_evict.339152001
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3925959813
Short name T476
Test name
Test status
Simulation time 18163500 ps
CPU time 20.79 seconds
Started Jun 13 03:19:13 PM PDT 24
Finished Jun 13 03:19:35 PM PDT 24
Peak memory 265796 kb
Host smart-f0a62912-7de8-4843-986e-65286593663c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925959813 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3925959813
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.2939636317
Short name T965
Test name
Test status
Simulation time 24501700 ps
CPU time 22.79 seconds
Started Jun 13 03:19:04 PM PDT 24
Finished Jun 13 03:19:27 PM PDT 24
Peak memory 265580 kb
Host smart-303e19db-8518-496f-9886-c5e958bb6338
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939636317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.2939636317
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.659062756
Short name T627
Test name
Test status
Simulation time 1185537700 ps
CPU time 133.86 seconds
Started Jun 13 03:19:06 PM PDT 24
Finished Jun 13 03:21:21 PM PDT 24
Peak memory 282232 kb
Host smart-6293466c-c804-4323-ba2a-6be242b162b1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659062756 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_ro.659062756
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.62004094
Short name T52
Test name
Test status
Simulation time 2356356600 ps
CPU time 145.8 seconds
Started Jun 13 03:19:10 PM PDT 24
Finished Jun 13 03:21:37 PM PDT 24
Peak memory 283404 kb
Host smart-ce8a49e5-e9f6-4d54-b99f-30bebfab4101
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
62004094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.62004094
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2489133837
Short name T469
Test name
Test status
Simulation time 1300725200 ps
CPU time 139.3 seconds
Started Jun 13 03:19:05 PM PDT 24
Finished Jun 13 03:21:25 PM PDT 24
Peak memory 295648 kb
Host smart-20e10f01-c314-4b61-a812-302873f88f3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489133837 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2489133837
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.137208570
Short name T674
Test name
Test status
Simulation time 14847401400 ps
CPU time 599.58 seconds
Started Jun 13 03:19:05 PM PDT 24
Finished Jun 13 03:29:05 PM PDT 24
Peak memory 314188 kb
Host smart-b6dda905-ba33-40f7-98ca-9ba63c49f903
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137208570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_rw.137208570
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.3937397207
Short name T946
Test name
Test status
Simulation time 58304000 ps
CPU time 31.48 seconds
Started Jun 13 03:19:20 PM PDT 24
Finished Jun 13 03:19:52 PM PDT 24
Peak memory 277188 kb
Host smart-b17e1c3d-a3a3-47ba-90cb-19da6f032b02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937397207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.3937397207
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3497407429
Short name T998
Test name
Test status
Simulation time 77468000 ps
CPU time 30.35 seconds
Started Jun 13 03:19:22 PM PDT 24
Finished Jun 13 03:19:53 PM PDT 24
Peak memory 275380 kb
Host smart-77ff5f0d-581e-4f5e-be72-eaa39d21fc82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497407429 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3497407429
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.4216246869
Short name T985
Test name
Test status
Simulation time 10560988400 ps
CPU time 638.94 seconds
Started Jun 13 03:19:10 PM PDT 24
Finished Jun 13 03:29:50 PM PDT 24
Peak memory 314372 kb
Host smart-eef9dea6-dc1e-432a-ab3a-3baec305d835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216246869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.4216246869
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3888213655
Short name T17
Test name
Test status
Simulation time 4999453300 ps
CPU time 4860.47 seconds
Started Jun 13 03:19:20 PM PDT 24
Finished Jun 13 04:40:22 PM PDT 24
Peak memory 285684 kb
Host smart-72e2d897-5b9f-4c2c-be55-22ebabf204a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888213655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3888213655
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1351006011
Short name T370
Test name
Test status
Simulation time 617428600 ps
CPU time 66.38 seconds
Started Jun 13 03:19:22 PM PDT 24
Finished Jun 13 03:20:29 PM PDT 24
Peak memory 263576 kb
Host smart-b967dd85-a0b9-4ef2-a6d5-e945cbd975e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351006011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1351006011
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2861312848
Short name T556
Test name
Test status
Simulation time 3659850900 ps
CPU time 79.56 seconds
Started Jun 13 03:19:10 PM PDT 24
Finished Jun 13 03:20:30 PM PDT 24
Peak memory 265772 kb
Host smart-c7f001f7-995d-4b6a-9df3-71472045000f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861312848 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2861312848
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.852218346
Short name T822
Test name
Test status
Simulation time 2082149500 ps
CPU time 69.16 seconds
Started Jun 13 03:19:10 PM PDT 24
Finished Jun 13 03:20:20 PM PDT 24
Peak memory 274760 kb
Host smart-19abc813-f70e-40ed-a514-9b894d318737
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852218346 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.852218346
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2011546623
Short name T55
Test name
Test status
Simulation time 50035700 ps
CPU time 52.82 seconds
Started Jun 13 03:18:55 PM PDT 24
Finished Jun 13 03:19:49 PM PDT 24
Peak memory 271512 kb
Host smart-b2b5748a-8b71-426d-bd34-f0db8de8e1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011546623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2011546623
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1624425495
Short name T594
Test name
Test status
Simulation time 97588000 ps
CPU time 26.17 seconds
Started Jun 13 03:18:54 PM PDT 24
Finished Jun 13 03:19:21 PM PDT 24
Peak memory 260160 kb
Host smart-49e8b370-b05a-4d2f-8887-42bf769861c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624425495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1624425495
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2555651997
Short name T515
Test name
Test status
Simulation time 234009300 ps
CPU time 1003.9 seconds
Started Jun 13 03:19:23 PM PDT 24
Finished Jun 13 03:36:07 PM PDT 24
Peak memory 286376 kb
Host smart-b3cb59e8-970b-4c59-bfa4-b6a41c5d7347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555651997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2555651997
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.784704215
Short name T488
Test name
Test status
Simulation time 23373600 ps
CPU time 24.18 seconds
Started Jun 13 03:18:54 PM PDT 24
Finished Jun 13 03:19:19 PM PDT 24
Peak memory 262704 kb
Host smart-1d44e246-3331-473d-a35b-5d41a9f9b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784704215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.784704215
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.98955756
Short name T631
Test name
Test status
Simulation time 1938827700 ps
CPU time 177.55 seconds
Started Jun 13 03:19:06 PM PDT 24
Finished Jun 13 03:22:04 PM PDT 24
Peak memory 265596 kb
Host smart-375624bd-de3a-4f57-885a-7d1da19c1634
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98955756 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_wo.98955756
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1323332224
Short name T526
Test name
Test status
Simulation time 87948500 ps
CPU time 13.86 seconds
Started Jun 13 03:26:51 PM PDT 24
Finished Jun 13 03:27:06 PM PDT 24
Peak memory 265636 kb
Host smart-856b9102-f2b4-45de-b909-deee250543de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323332224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1323332224
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.2555878512
Short name T451
Test name
Test status
Simulation time 16074300 ps
CPU time 13.41 seconds
Started Jun 13 03:26:47 PM PDT 24
Finished Jun 13 03:27:01 PM PDT 24
Peak memory 275116 kb
Host smart-e49f24cc-d0af-4e78-999a-8537996b89f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555878512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2555878512
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1242696574
Short name T981
Test name
Test status
Simulation time 31560400 ps
CPU time 20.73 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:27:02 PM PDT 24
Peak memory 265248 kb
Host smart-3e2402dc-a96d-4156-a544-9669ad014389
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242696574 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1242696574
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1255997007
Short name T694
Test name
Test status
Simulation time 1464289800 ps
CPU time 62.89 seconds
Started Jun 13 03:26:47 PM PDT 24
Finished Jun 13 03:27:51 PM PDT 24
Peak memory 263160 kb
Host smart-10ceae8e-e39f-4f86-ac79-bb0d0db96b25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255997007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1255997007
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.975991628
Short name T454
Test name
Test status
Simulation time 82284000 ps
CPU time 135.83 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:28:58 PM PDT 24
Peak memory 261504 kb
Host smart-c33e4a45-bf83-4a0d-ae83-ff8e066c97e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975991628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.975991628
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.644285347
Short name T509
Test name
Test status
Simulation time 2254067100 ps
CPU time 82.58 seconds
Started Jun 13 03:26:41 PM PDT 24
Finished Jun 13 03:28:05 PM PDT 24
Peak memory 265408 kb
Host smart-1e3e48be-de64-425a-ae51-e4961f6ccba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644285347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.644285347
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.1737914082
Short name T490
Test name
Test status
Simulation time 42368400 ps
CPU time 98.51 seconds
Started Jun 13 03:26:39 PM PDT 24
Finished Jun 13 03:28:18 PM PDT 24
Peak memory 276156 kb
Host smart-5c6f1ff2-820e-4ec8-a7d6-77a572d9d5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737914082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.1737914082
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1503262924
Short name T682
Test name
Test status
Simulation time 207175400 ps
CPU time 14.24 seconds
Started Jun 13 03:26:48 PM PDT 24
Finished Jun 13 03:27:03 PM PDT 24
Peak memory 265548 kb
Host smart-6e6d4eeb-7764-4a21-9083-a182b7fc4cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503262924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1503262924
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.1529826387
Short name T593
Test name
Test status
Simulation time 46213300 ps
CPU time 13.41 seconds
Started Jun 13 03:26:52 PM PDT 24
Finished Jun 13 03:27:06 PM PDT 24
Peak memory 284484 kb
Host smart-45099198-cac4-4a65-be5a-a64d5f8ed01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529826387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1529826387
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.496163748
Short name T358
Test name
Test status
Simulation time 10729800 ps
CPU time 20.64 seconds
Started Jun 13 03:26:44 PM PDT 24
Finished Jun 13 03:27:05 PM PDT 24
Peak memory 265456 kb
Host smart-987a22c3-6681-46fb-bfea-40461d6569fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496163748 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.496163748
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.2441516358
Short name T289
Test name
Test status
Simulation time 8428528100 ps
CPU time 105.69 seconds
Started Jun 13 03:26:47 PM PDT 24
Finished Jun 13 03:28:33 PM PDT 24
Peak memory 261288 kb
Host smart-8443e6ec-464b-4b6f-b708-e22a8bd1a4fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441516358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.2441516358
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.173625728
Short name T521
Test name
Test status
Simulation time 218034900 ps
CPU time 133.62 seconds
Started Jun 13 03:26:46 PM PDT 24
Finished Jun 13 03:29:00 PM PDT 24
Peak memory 260756 kb
Host smart-eb73874f-dda3-4170-85c0-d61616555c36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173625728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.173625728
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.3003833112
Short name T419
Test name
Test status
Simulation time 819769800 ps
CPU time 51.98 seconds
Started Jun 13 03:26:51 PM PDT 24
Finished Jun 13 03:27:44 PM PDT 24
Peak memory 265460 kb
Host smart-14d35986-e3d5-4379-9e47-d5da87d541c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003833112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3003833112
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2066200526
Short name T497
Test name
Test status
Simulation time 25981000 ps
CPU time 49.91 seconds
Started Jun 13 03:26:45 PM PDT 24
Finished Jun 13 03:27:35 PM PDT 24
Peak memory 271620 kb
Host smart-35b73b14-fce1-4fbc-8be2-2fdc304b69b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066200526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2066200526
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.964095385
Short name T758
Test name
Test status
Simulation time 36110000 ps
CPU time 13.46 seconds
Started Jun 13 03:26:50 PM PDT 24
Finished Jun 13 03:27:05 PM PDT 24
Peak memory 258760 kb
Host smart-677b339d-cc71-4379-947d-1facdfb148c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964095385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.964095385
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.892151872
Short name T552
Test name
Test status
Simulation time 15079200 ps
CPU time 16.16 seconds
Started Jun 13 03:26:49 PM PDT 24
Finished Jun 13 03:27:06 PM PDT 24
Peak memory 275280 kb
Host smart-d2541289-9fa2-4dce-9009-01e06275e9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892151872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.892151872
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.124123275
Short name T688
Test name
Test status
Simulation time 49203600 ps
CPU time 22.21 seconds
Started Jun 13 03:26:47 PM PDT 24
Finished Jun 13 03:27:10 PM PDT 24
Peak memory 274072 kb
Host smart-b028735f-09df-4ce6-ad04-468219822855
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124123275 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.124123275
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3625392355
Short name T559
Test name
Test status
Simulation time 2404974800 ps
CPU time 75.48 seconds
Started Jun 13 03:26:49 PM PDT 24
Finished Jun 13 03:28:05 PM PDT 24
Peak memory 260988 kb
Host smart-46afeb2a-dca4-4b33-b858-025e9445bd5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625392355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.3625392355
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.4183044165
Short name T1061
Test name
Test status
Simulation time 35544400 ps
CPU time 133.53 seconds
Started Jun 13 03:26:49 PM PDT 24
Finished Jun 13 03:29:04 PM PDT 24
Peak memory 260404 kb
Host smart-401bd445-6613-43a5-a53f-eaa593d69b20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183044165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.4183044165
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.1685510247
Short name T910
Test name
Test status
Simulation time 558232700 ps
CPU time 64.68 seconds
Started Jun 13 03:26:47 PM PDT 24
Finished Jun 13 03:27:53 PM PDT 24
Peak memory 265608 kb
Host smart-03282cb4-da51-46d5-a4f3-16373792e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685510247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.1685510247
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.713762834
Short name T4
Test name
Test status
Simulation time 20568900 ps
CPU time 100.56 seconds
Started Jun 13 03:26:46 PM PDT 24
Finished Jun 13 03:28:28 PM PDT 24
Peak memory 277464 kb
Host smart-67692673-258b-4c5a-850e-2747805ba047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713762834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.713762834
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.704348635
Short name T80
Test name
Test status
Simulation time 90859800 ps
CPU time 13.75 seconds
Started Jun 13 03:26:52 PM PDT 24
Finished Jun 13 03:27:06 PM PDT 24
Peak memory 258688 kb
Host smart-cb3e85cd-2d85-466c-8552-71097b951589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704348635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.704348635
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1662632537
Short name T1011
Test name
Test status
Simulation time 42583100 ps
CPU time 15.96 seconds
Started Jun 13 03:26:52 PM PDT 24
Finished Jun 13 03:27:10 PM PDT 24
Peak memory 275280 kb
Host smart-c2d1ba1f-1914-488a-94f1-630ac7073dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662632537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1662632537
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.1128121829
Short name T172
Test name
Test status
Simulation time 16877300 ps
CPU time 21.89 seconds
Started Jun 13 03:26:53 PM PDT 24
Finished Jun 13 03:27:16 PM PDT 24
Peak memory 274040 kb
Host smart-3db14c74-f368-4ff5-ad04-5486045ddbf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128121829 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.1128121829
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.3137900931
Short name T678
Test name
Test status
Simulation time 3076965300 ps
CPU time 104.92 seconds
Started Jun 13 03:26:52 PM PDT 24
Finished Jun 13 03:28:38 PM PDT 24
Peak memory 263108 kb
Host smart-501b51f2-1c2f-4ded-ab9d-3ab8e4edb8a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137900931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.3137900931
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1878862767
Short name T459
Test name
Test status
Simulation time 56744100 ps
CPU time 98.37 seconds
Started Jun 13 03:26:51 PM PDT 24
Finished Jun 13 03:28:30 PM PDT 24
Peak memory 276272 kb
Host smart-5360b6b7-d422-4d97-b621-810e92bbe716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878862767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1878862767
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.2695813850
Short name T779
Test name
Test status
Simulation time 126622300 ps
CPU time 13.77 seconds
Started Jun 13 03:26:56 PM PDT 24
Finished Jun 13 03:27:11 PM PDT 24
Peak memory 258664 kb
Host smart-8894be30-bd8a-47c1-b6a9-786df0d5d5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695813850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
2695813850
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.1679531469
Short name T288
Test name
Test status
Simulation time 13439600 ps
CPU time 13.24 seconds
Started Jun 13 03:26:57 PM PDT 24
Finished Jun 13 03:27:11 PM PDT 24
Peak memory 284576 kb
Host smart-8eb7c58b-eb2f-4345-9ef3-7e98a14f9049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679531469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1679531469
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1229893758
Short name T344
Test name
Test status
Simulation time 10469900 ps
CPU time 21.48 seconds
Started Jun 13 03:26:53 PM PDT 24
Finished Jun 13 03:27:16 PM PDT 24
Peak memory 274204 kb
Host smart-4ead4f0b-8d41-4fb5-9432-63f6e4227c74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229893758 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1229893758
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3341827134
Short name T1047
Test name
Test status
Simulation time 1581194700 ps
CPU time 115.17 seconds
Started Jun 13 03:26:53 PM PDT 24
Finished Jun 13 03:28:49 PM PDT 24
Peak memory 263472 kb
Host smart-d2e8d402-a322-4187-acf9-b9a006c3d979
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341827134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3341827134
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.1209021887
Short name T776
Test name
Test status
Simulation time 158567100 ps
CPU time 131.43 seconds
Started Jun 13 03:26:53 PM PDT 24
Finished Jun 13 03:29:06 PM PDT 24
Peak memory 261428 kb
Host smart-7c48af50-f48f-4485-ae03-8308d8b90e91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209021887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.1209021887
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.422557898
Short name T373
Test name
Test status
Simulation time 2258959800 ps
CPU time 74.61 seconds
Started Jun 13 03:26:58 PM PDT 24
Finished Jun 13 03:28:13 PM PDT 24
Peak memory 263968 kb
Host smart-4e611e41-e894-40ac-a5d8-31ff824f0597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422557898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.422557898
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.1073364471
Short name T246
Test name
Test status
Simulation time 22229800 ps
CPU time 97.93 seconds
Started Jun 13 03:26:50 PM PDT 24
Finished Jun 13 03:28:29 PM PDT 24
Peak memory 276248 kb
Host smart-4c96df62-469a-457c-9a18-0a6a1a01f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073364471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1073364471
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.678435986
Short name T413
Test name
Test status
Simulation time 187238600 ps
CPU time 13.74 seconds
Started Jun 13 03:27:05 PM PDT 24
Finished Jun 13 03:27:20 PM PDT 24
Peak memory 265528 kb
Host smart-b284d2c5-18d5-4bba-9448-3bc503f93df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678435986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.678435986
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.1922493116
Short name T620
Test name
Test status
Simulation time 50938400 ps
CPU time 15.63 seconds
Started Jun 13 03:27:02 PM PDT 24
Finished Jun 13 03:27:19 PM PDT 24
Peak memory 275164 kb
Host smart-43e688a3-f7c4-4d99-9e27-16b4df02b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922493116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1922493116
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1540456220
Short name T1025
Test name
Test status
Simulation time 13137787400 ps
CPU time 211.53 seconds
Started Jun 13 03:26:58 PM PDT 24
Finished Jun 13 03:30:30 PM PDT 24
Peak memory 263036 kb
Host smart-b761ce4a-2769-4c58-819f-27197c9c5b53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540456220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.1540456220
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1790963461
Short name T1020
Test name
Test status
Simulation time 354555100 ps
CPU time 109.96 seconds
Started Jun 13 03:26:58 PM PDT 24
Finished Jun 13 03:28:49 PM PDT 24
Peak memory 260520 kb
Host smart-ddc12fb2-0e5c-481b-bc8d-6e872c24b34e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790963461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1790963461
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2695566199
Short name T403
Test name
Test status
Simulation time 1696116100 ps
CPU time 82.18 seconds
Started Jun 13 03:27:16 PM PDT 24
Finished Jun 13 03:28:39 PM PDT 24
Peak memory 263996 kb
Host smart-8512dc9e-41d6-4cde-9e9f-04e398300326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695566199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2695566199
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1615866266
Short name T803
Test name
Test status
Simulation time 56440200 ps
CPU time 76.38 seconds
Started Jun 13 03:26:58 PM PDT 24
Finished Jun 13 03:28:15 PM PDT 24
Peak memory 276980 kb
Host smart-2d5d5857-6793-45d4-8970-afdd1e5aa04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615866266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1615866266
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1390426523
Short name T991
Test name
Test status
Simulation time 48554200 ps
CPU time 13.61 seconds
Started Jun 13 03:27:04 PM PDT 24
Finished Jun 13 03:27:18 PM PDT 24
Peak memory 258692 kb
Host smart-386a93d6-2553-469f-a5aa-0fd6b8fcd92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390426523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1390426523
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1259681458
Short name T457
Test name
Test status
Simulation time 34102000 ps
CPU time 13.35 seconds
Started Jun 13 03:27:07 PM PDT 24
Finished Jun 13 03:27:21 PM PDT 24
Peak memory 284744 kb
Host smart-5c4072bb-4e60-4ffc-8ce7-c51fd5e452e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259681458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1259681458
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.4204175578
Short name T173
Test name
Test status
Simulation time 9779400 ps
CPU time 21.79 seconds
Started Jun 13 03:27:04 PM PDT 24
Finished Jun 13 03:27:27 PM PDT 24
Peak memory 274112 kb
Host smart-25d6b0f4-d47a-472d-95d1-83ae96043cce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204175578 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.4204175578
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2288037850
Short name T465
Test name
Test status
Simulation time 8591385900 ps
CPU time 142.42 seconds
Started Jun 13 03:27:03 PM PDT 24
Finished Jun 13 03:29:27 PM PDT 24
Peak memory 263508 kb
Host smart-1b57233c-69f8-4620-b338-0d4356aa1231
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288037850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2288037850
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3085577116
Short name T1030
Test name
Test status
Simulation time 41600500 ps
CPU time 110.83 seconds
Started Jun 13 03:27:02 PM PDT 24
Finished Jun 13 03:28:54 PM PDT 24
Peak memory 261400 kb
Host smart-7967aed0-6451-4fc5-bcce-b31ae87b9674
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085577116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3085577116
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.843842556
Short name T914
Test name
Test status
Simulation time 4086683100 ps
CPU time 75.55 seconds
Started Jun 13 03:27:05 PM PDT 24
Finished Jun 13 03:28:22 PM PDT 24
Peak memory 264000 kb
Host smart-6d3aeb63-0198-45b4-85f1-3ec6b96be87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843842556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.843842556
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.4207420434
Short name T567
Test name
Test status
Simulation time 684692800 ps
CPU time 158.34 seconds
Started Jun 13 03:27:03 PM PDT 24
Finished Jun 13 03:29:42 PM PDT 24
Peak memory 281384 kb
Host smart-3bf55443-30a0-4af6-98fe-27bb5de24e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207420434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.4207420434
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.4051537549
Short name T748
Test name
Test status
Simulation time 62493900 ps
CPU time 13.34 seconds
Started Jun 13 03:27:08 PM PDT 24
Finished Jun 13 03:27:22 PM PDT 24
Peak memory 258716 kb
Host smart-8ce0e210-9b09-4f4a-b7f9-955317e0d29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051537549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
4051537549
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2291600884
Short name T604
Test name
Test status
Simulation time 18321200 ps
CPU time 13.45 seconds
Started Jun 13 03:27:09 PM PDT 24
Finished Jun 13 03:27:23 PM PDT 24
Peak memory 275184 kb
Host smart-3400ade5-a525-4e86-8bee-44e5d1cc8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291600884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2291600884
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.483462386
Short name T1089
Test name
Test status
Simulation time 10796400 ps
CPU time 20.7 seconds
Started Jun 13 03:27:10 PM PDT 24
Finished Jun 13 03:27:31 PM PDT 24
Peak memory 274184 kb
Host smart-c787f68c-3ac7-41f2-9ad3-728d877998bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483462386 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.483462386
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.3604233192
Short name T718
Test name
Test status
Simulation time 40256200 ps
CPU time 132.36 seconds
Started Jun 13 03:27:06 PM PDT 24
Finished Jun 13 03:29:19 PM PDT 24
Peak memory 261352 kb
Host smart-fc941932-d796-42b7-afb8-7f2aed0af2e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604233192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.3604233192
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.2519422705
Short name T361
Test name
Test status
Simulation time 1201394800 ps
CPU time 62.93 seconds
Started Jun 13 03:27:11 PM PDT 24
Finished Jun 13 03:28:14 PM PDT 24
Peak memory 264008 kb
Host smart-6b977def-4526-49d0-86bc-4e0bcfad7c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519422705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2519422705
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.4155548739
Short name T411
Test name
Test status
Simulation time 30240400 ps
CPU time 122.87 seconds
Started Jun 13 03:27:04 PM PDT 24
Finished Jun 13 03:29:08 PM PDT 24
Peak memory 276784 kb
Host smart-42fb84a3-a699-4615-b770-6d74363769ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155548739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.4155548739
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.2707788153
Short name T810
Test name
Test status
Simulation time 51144600 ps
CPU time 13.31 seconds
Started Jun 13 03:27:11 PM PDT 24
Finished Jun 13 03:27:25 PM PDT 24
Peak memory 265640 kb
Host smart-3807e468-5014-45cf-aa99-952990226573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707788153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
2707788153
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.3572581923
Short name T295
Test name
Test status
Simulation time 13384300 ps
CPU time 15.9 seconds
Started Jun 13 03:27:08 PM PDT 24
Finished Jun 13 03:27:25 PM PDT 24
Peak memory 284332 kb
Host smart-2a4e10a0-8f11-4686-a95e-74d769492d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572581923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3572581923
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.3942684509
Short name T353
Test name
Test status
Simulation time 14545400 ps
CPU time 21.72 seconds
Started Jun 13 03:27:11 PM PDT 24
Finished Jun 13 03:27:33 PM PDT 24
Peak memory 273976 kb
Host smart-4cde49e4-50f4-4ac1-9ea7-adfb12e65e6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942684509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.3942684509
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3269310306
Short name T930
Test name
Test status
Simulation time 4548436600 ps
CPU time 103.05 seconds
Started Jun 13 03:27:10 PM PDT 24
Finished Jun 13 03:28:54 PM PDT 24
Peak memory 263508 kb
Host smart-f390d385-cb54-43b5-8d55-b5a8f9e25354
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269310306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.3269310306
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2976711450
Short name T615
Test name
Test status
Simulation time 67512500 ps
CPU time 137.14 seconds
Started Jun 13 03:27:11 PM PDT 24
Finished Jun 13 03:29:29 PM PDT 24
Peak memory 260512 kb
Host smart-0dc02290-b315-499d-a0ba-0ab8532a8941
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976711450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2976711450
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.192472818
Short name T365
Test name
Test status
Simulation time 3819656900 ps
CPU time 68.55 seconds
Started Jun 13 03:27:09 PM PDT 24
Finished Jun 13 03:28:18 PM PDT 24
Peak memory 265584 kb
Host smart-aad3564e-4e82-4cc5-ba28-ddc8c2324cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192472818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.192472818
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2223451956
Short name T417
Test name
Test status
Simulation time 46023200 ps
CPU time 122.55 seconds
Started Jun 13 03:27:09 PM PDT 24
Finished Jun 13 03:29:12 PM PDT 24
Peak memory 276808 kb
Host smart-8d4fc0c5-ff41-4f5e-bc35-d027867592bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223451956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2223451956
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.3833307382
Short name T427
Test name
Test status
Simulation time 26161700 ps
CPU time 13.72 seconds
Started Jun 13 03:27:16 PM PDT 24
Finished Jun 13 03:27:31 PM PDT 24
Peak memory 265664 kb
Host smart-583bdca8-3920-445b-b7b3-4ab8786e90cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833307382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
3833307382
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2813938765
Short name T937
Test name
Test status
Simulation time 28456700 ps
CPU time 13.34 seconds
Started Jun 13 03:27:15 PM PDT 24
Finished Jun 13 03:27:29 PM PDT 24
Peak memory 275244 kb
Host smart-bf20e739-19af-46a8-b243-779a31c7d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813938765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2813938765
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.948075793
Short name T969
Test name
Test status
Simulation time 33714000 ps
CPU time 21.74 seconds
Started Jun 13 03:27:17 PM PDT 24
Finished Jun 13 03:27:39 PM PDT 24
Peak memory 265988 kb
Host smart-abfee731-638d-4886-b87d-d8d148a6ecb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948075793 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.948075793
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3038731410
Short name T585
Test name
Test status
Simulation time 2946419500 ps
CPU time 95.33 seconds
Started Jun 13 03:27:09 PM PDT 24
Finished Jun 13 03:28:45 PM PDT 24
Peak memory 263560 kb
Host smart-141f817a-3d35-4f93-a75c-02beea487890
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038731410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3038731410
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.433777077
Short name T100
Test name
Test status
Simulation time 75646800 ps
CPU time 108.81 seconds
Started Jun 13 03:27:19 PM PDT 24
Finished Jun 13 03:29:09 PM PDT 24
Peak memory 261328 kb
Host smart-5c3668b9-490d-41a0-a326-b319238669f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433777077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.433777077
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.965359872
Short name T379
Test name
Test status
Simulation time 4386404500 ps
CPU time 59.84 seconds
Started Jun 13 03:27:18 PM PDT 24
Finished Jun 13 03:28:19 PM PDT 24
Peak memory 264092 kb
Host smart-5711fa7b-77e3-4d01-9d37-532695a26f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965359872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.965359872
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3563160424
Short name T582
Test name
Test status
Simulation time 62903000 ps
CPU time 169.19 seconds
Started Jun 13 03:27:12 PM PDT 24
Finished Jun 13 03:30:01 PM PDT 24
Peak memory 277596 kb
Host smart-4c74b6d1-ebd8-4a1e-8885-e3dd8ab32560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563160424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3563160424
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.1609927487
Short name T1064
Test name
Test status
Simulation time 32411700 ps
CPU time 13.81 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:20:10 PM PDT 24
Peak memory 258736 kb
Host smart-d855e9a1-357e-48c1-b0d3-48a6e233fe9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609927487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1
609927487
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1174383796
Short name T243
Test name
Test status
Simulation time 13006900 ps
CPU time 16.32 seconds
Started Jun 13 03:19:48 PM PDT 24
Finished Jun 13 03:20:05 PM PDT 24
Peak memory 284592 kb
Host smart-3670aec5-5e1d-42ac-abd1-783988ee277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174383796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1174383796
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.1631241145
Short name T134
Test name
Test status
Simulation time 3913570200 ps
CPU time 2224.12 seconds
Started Jun 13 03:19:36 PM PDT 24
Finished Jun 13 03:56:41 PM PDT 24
Peak memory 263108 kb
Host smart-1a6b1038-2715-434b-8a03-a41c4bc1953c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631241145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.1631241145
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1824249732
Short name T277
Test name
Test status
Simulation time 3822640500 ps
CPU time 872.26 seconds
Started Jun 13 03:19:33 PM PDT 24
Finished Jun 13 03:34:07 PM PDT 24
Peak memory 273016 kb
Host smart-77a1f7ae-f450-4789-a15f-c8ae6a1da55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824249732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1824249732
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1772757821
Short name T47
Test name
Test status
Simulation time 871218300 ps
CPU time 22.64 seconds
Started Jun 13 03:19:41 PM PDT 24
Finished Jun 13 03:20:05 PM PDT 24
Peak memory 262828 kb
Host smart-8f3f6dba-d576-4fd4-b0e4-0dc495e80321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772757821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1772757821
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1911241212
Short name T161
Test name
Test status
Simulation time 10019046600 ps
CPU time 90.15 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:21:26 PM PDT 24
Peak memory 323744 kb
Host smart-0c2798cc-e74f-43f2-b5c4-56f2902c8b83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911241212 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1911241212
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1080195817
Short name T902
Test name
Test status
Simulation time 31892600 ps
CPU time 13.54 seconds
Started Jun 13 03:19:47 PM PDT 24
Finished Jun 13 03:20:02 PM PDT 24
Peak memory 258920 kb
Host smart-79db70cf-414a-4190-8e57-6ed0c7516a46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080195817 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1080195817
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.602645158
Short name T1049
Test name
Test status
Simulation time 40124178400 ps
CPU time 827.62 seconds
Started Jun 13 03:19:56 PM PDT 24
Finished Jun 13 03:33:44 PM PDT 24
Peak memory 261236 kb
Host smart-6f52f42f-6055-4c52-8329-749db1c3198a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602645158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.602645158
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1450068561
Short name T443
Test name
Test status
Simulation time 2715564900 ps
CPU time 199.05 seconds
Started Jun 13 03:19:41 PM PDT 24
Finished Jun 13 03:23:01 PM PDT 24
Peak memory 263512 kb
Host smart-47930185-cfcd-415d-9237-c3fb143088ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450068561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.1450068561
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.945743050
Short name T832
Test name
Test status
Simulation time 1167731900 ps
CPU time 121.85 seconds
Started Jun 13 03:19:42 PM PDT 24
Finished Jun 13 03:21:44 PM PDT 24
Peak memory 294608 kb
Host smart-5f5ad5af-4591-4901-8318-64223aacfca0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945743050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_intr_rd.945743050
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.637093328
Short name T314
Test name
Test status
Simulation time 25731873500 ps
CPU time 265.4 seconds
Started Jun 13 03:19:47 PM PDT 24
Finished Jun 13 03:24:13 PM PDT 24
Peak memory 291420 kb
Host smart-500f00d5-f6fd-4c03-8290-69cbb0db99f8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637093328 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.637093328
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2337607979
Short name T859
Test name
Test status
Simulation time 10778266700 ps
CPU time 80.4 seconds
Started Jun 13 03:19:42 PM PDT 24
Finished Jun 13 03:21:03 PM PDT 24
Peak memory 265500 kb
Host smart-20e1c84e-bf8f-4847-ab4a-9d2e7884568b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337607979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2337607979
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.635245325
Short name T740
Test name
Test status
Simulation time 18687226600 ps
CPU time 167.01 seconds
Started Jun 13 03:19:47 PM PDT 24
Finished Jun 13 03:22:34 PM PDT 24
Peak memory 260716 kb
Host smart-5ce3825b-02e6-4303-8b74-c05e6f60882e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635
245325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.635245325
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.96339340
Short name T426
Test name
Test status
Simulation time 6540253900 ps
CPU time 62 seconds
Started Jun 13 03:19:37 PM PDT 24
Finished Jun 13 03:20:39 PM PDT 24
Peak memory 260864 kb
Host smart-83b275d8-a562-4034-b17c-82a5c0be3748
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96339340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.96339340
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.1655564624
Short name T687
Test name
Test status
Simulation time 33809400 ps
CPU time 13.34 seconds
Started Jun 13 03:19:49 PM PDT 24
Finished Jun 13 03:20:04 PM PDT 24
Peak memory 265324 kb
Host smart-fb89fdb4-4d94-48ab-94d9-5c2290a6f94b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655564624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.1655564624
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2615433768
Short name T1071
Test name
Test status
Simulation time 12161014900 ps
CPU time 290.4 seconds
Started Jun 13 03:19:33 PM PDT 24
Finished Jun 13 03:24:25 PM PDT 24
Peak memory 275372 kb
Host smart-4d30af00-5e86-4806-89d2-7392f67786e9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615433768 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2615433768
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2920527246
Short name T647
Test name
Test status
Simulation time 104673100 ps
CPU time 132.22 seconds
Started Jun 13 03:19:36 PM PDT 24
Finished Jun 13 03:21:49 PM PDT 24
Peak memory 261488 kb
Host smart-ca8e5587-9391-4df7-953a-9aee5c5d4e93
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920527246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2920527246
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.273867181
Short name T1008
Test name
Test status
Simulation time 269675000 ps
CPU time 363.94 seconds
Started Jun 13 03:19:35 PM PDT 24
Finished Jun 13 03:25:39 PM PDT 24
Peak memory 263548 kb
Host smart-66a137ee-a6f4-4de2-bc32-9aabd3d61850
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273867181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.273867181
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3452046611
Short name T148
Test name
Test status
Simulation time 29092000 ps
CPU time 13.58 seconds
Started Jun 13 03:19:46 PM PDT 24
Finished Jun 13 03:20:00 PM PDT 24
Peak memory 259116 kb
Host smart-ec4934a1-2f51-41f1-9d89-ebb850621d04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452046611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3452046611
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.4126262430
Short name T722
Test name
Test status
Simulation time 155601000 ps
CPU time 293.45 seconds
Started Jun 13 03:19:35 PM PDT 24
Finished Jun 13 03:24:29 PM PDT 24
Peak memory 282004 kb
Host smart-bc49b9b6-26f2-4a8c-8a98-d0b23d807e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126262430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.4126262430
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2421692054
Short name T651
Test name
Test status
Simulation time 1077041800 ps
CPU time 110.31 seconds
Started Jun 13 03:19:40 PM PDT 24
Finished Jun 13 03:21:31 PM PDT 24
Peak memory 282320 kb
Host smart-125a7a00-4b3d-40d6-bab1-1ba746169ffc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421692054 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2421692054
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1979434985
Short name T510
Test name
Test status
Simulation time 1133013300 ps
CPU time 151.45 seconds
Started Jun 13 03:19:39 PM PDT 24
Finished Jun 13 03:22:11 PM PDT 24
Peak memory 282340 kb
Host smart-1c4f5e08-9502-409e-9d6a-e6869e2ffb3c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1979434985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1979434985
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3051494383
Short name T21
Test name
Test status
Simulation time 660703600 ps
CPU time 139.23 seconds
Started Jun 13 03:19:41 PM PDT 24
Finished Jun 13 03:22:02 PM PDT 24
Peak memory 295276 kb
Host smart-e166b9e5-f05d-4cf0-a984-e56f1b262be7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051494383 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3051494383
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.42437627
Short name T323
Test name
Test status
Simulation time 3515086700 ps
CPU time 571.79 seconds
Started Jun 13 03:19:41 PM PDT 24
Finished Jun 13 03:29:13 PM PDT 24
Peak memory 314856 kb
Host smart-ee9e6ba7-ac2b-42a8-b344-3b674b29dd29
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42437627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_rw.42437627
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1926207542
Short name T536
Test name
Test status
Simulation time 30320100 ps
CPU time 31.23 seconds
Started Jun 13 03:19:47 PM PDT 24
Finished Jun 13 03:20:19 PM PDT 24
Peak memory 275876 kb
Host smart-47111b3c-4ab7-4097-a4a1-40d17ed56f34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926207542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1926207542
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2442484296
Short name T1040
Test name
Test status
Simulation time 32104700 ps
CPU time 28.99 seconds
Started Jun 13 03:19:49 PM PDT 24
Finished Jun 13 03:20:19 PM PDT 24
Peak memory 275308 kb
Host smart-f0def16e-cd41-4366-8430-efde6568a4bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442484296 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.2442484296
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.3186383785
Short name T813
Test name
Test status
Simulation time 8380467700 ps
CPU time 854.86 seconds
Started Jun 13 03:19:44 PM PDT 24
Finished Jun 13 03:33:59 PM PDT 24
Peak memory 315044 kb
Host smart-e99a41fd-4b3c-4350-83d5-d5249f67b393
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186383785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.3186383785
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3451773331
Short name T757
Test name
Test status
Simulation time 2919064100 ps
CPU time 76.6 seconds
Started Jun 13 03:19:48 PM PDT 24
Finished Jun 13 03:21:06 PM PDT 24
Peak memory 263608 kb
Host smart-09dbf460-e5a2-4562-b099-88bba12aa231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451773331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3451773331
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2794115497
Short name T542
Test name
Test status
Simulation time 24749300 ps
CPU time 124.54 seconds
Started Jun 13 03:19:33 PM PDT 24
Finished Jun 13 03:21:38 PM PDT 24
Peak memory 276364 kb
Host smart-0fb36574-d1b2-4951-9f81-d486688ff4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794115497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2794115497
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3865875710
Short name T538
Test name
Test status
Simulation time 2684208700 ps
CPU time 180.87 seconds
Started Jun 13 03:19:39 PM PDT 24
Finished Jun 13 03:22:41 PM PDT 24
Peak memory 265784 kb
Host smart-b6ae589a-6d10-4322-ba9a-33a6734ddaca
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865875710 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.3865875710
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.805976920
Short name T1054
Test name
Test status
Simulation time 41233500 ps
CPU time 13.78 seconds
Started Jun 13 03:27:15 PM PDT 24
Finished Jun 13 03:27:30 PM PDT 24
Peak memory 275184 kb
Host smart-2d1ca2da-159a-47f1-83df-f99cc61436df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805976920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.805976920
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.679063133
Short name T940
Test name
Test status
Simulation time 137887100 ps
CPU time 132.66 seconds
Started Jun 13 03:27:17 PM PDT 24
Finished Jun 13 03:29:30 PM PDT 24
Peak memory 265336 kb
Host smart-b46aa125-f09c-4900-913a-44f2e7a25fb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679063133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.679063133
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.61757577
Short name T548
Test name
Test status
Simulation time 13899200 ps
CPU time 13.27 seconds
Started Jun 13 03:27:19 PM PDT 24
Finished Jun 13 03:27:33 PM PDT 24
Peak memory 275148 kb
Host smart-b2f57392-b852-4faf-9c42-bea9355d656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61757577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.61757577
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.13513899
Short name T422
Test name
Test status
Simulation time 40854400 ps
CPU time 136.49 seconds
Started Jun 13 03:27:19 PM PDT 24
Finished Jun 13 03:29:36 PM PDT 24
Peak memory 260452 kb
Host smart-5f04aa54-ac85-46d6-93f3-89e238ba26cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13513899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp
_reset.13513899
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2374906944
Short name T537
Test name
Test status
Simulation time 217628800 ps
CPU time 136.44 seconds
Started Jun 13 03:27:15 PM PDT 24
Finished Jun 13 03:29:31 PM PDT 24
Peak memory 261544 kb
Host smart-fde0f372-4e7a-48b4-a957-4be675770506
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374906944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2374906944
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1892977503
Short name T834
Test name
Test status
Simulation time 49367200 ps
CPU time 13.44 seconds
Started Jun 13 03:27:16 PM PDT 24
Finished Jun 13 03:27:30 PM PDT 24
Peak memory 275236 kb
Host smart-fb533bd3-cdd9-4a1c-bc6f-c0677068893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892977503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1892977503
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.228008893
Short name T947
Test name
Test status
Simulation time 300237400 ps
CPU time 134.4 seconds
Started Jun 13 03:27:15 PM PDT 24
Finished Jun 13 03:29:30 PM PDT 24
Peak memory 265036 kb
Host smart-cf8cb86a-9b12-4a7a-8d20-e52d0aa601db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228008893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.228008893
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.3337309185
Short name T395
Test name
Test status
Simulation time 35865200 ps
CPU time 15.87 seconds
Started Jun 13 03:27:22 PM PDT 24
Finished Jun 13 03:27:39 PM PDT 24
Peak memory 275296 kb
Host smart-5e29a3d9-d2df-4052-a40b-ffea93d3d2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337309185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3337309185
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.2816005889
Short name T995
Test name
Test status
Simulation time 41860100 ps
CPU time 133.04 seconds
Started Jun 13 03:27:15 PM PDT 24
Finished Jun 13 03:29:28 PM PDT 24
Peak memory 260656 kb
Host smart-acc8976d-4167-47e5-b748-6bcd46f8f341
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816005889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.2816005889
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.3344514269
Short name T1035
Test name
Test status
Simulation time 25973400 ps
CPU time 15.77 seconds
Started Jun 13 03:27:20 PM PDT 24
Finished Jun 13 03:27:36 PM PDT 24
Peak memory 284488 kb
Host smart-9c05cca6-4f67-4c32-b710-90d5f750751e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344514269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3344514269
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1847697359
Short name T531
Test name
Test status
Simulation time 210410100 ps
CPU time 131.5 seconds
Started Jun 13 03:27:22 PM PDT 24
Finished Jun 13 03:29:34 PM PDT 24
Peak memory 260588 kb
Host smart-2255897e-2598-439c-91f5-1575f5f669d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847697359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1847697359
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.79152931
Short name T683
Test name
Test status
Simulation time 69430500 ps
CPU time 16.1 seconds
Started Jun 13 03:27:21 PM PDT 24
Finished Jun 13 03:27:38 PM PDT 24
Peak memory 275168 kb
Host smart-0c04b357-1ffd-4745-a16b-a120b5d9b430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79152931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.79152931
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.3568399788
Short name T805
Test name
Test status
Simulation time 76975700 ps
CPU time 109.79 seconds
Started Jun 13 03:27:20 PM PDT 24
Finished Jun 13 03:29:11 PM PDT 24
Peak memory 260432 kb
Host smart-843ca9a0-d963-4e3c-8998-8dbc874b9683
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568399788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.3568399788
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.361121088
Short name T732
Test name
Test status
Simulation time 15048900 ps
CPU time 16.29 seconds
Started Jun 13 03:27:21 PM PDT 24
Finished Jun 13 03:27:38 PM PDT 24
Peak memory 275300 kb
Host smart-e563d34c-b08f-4c72-8c94-ef033d0320bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361121088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.361121088
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.263161782
Short name T1022
Test name
Test status
Simulation time 43862300 ps
CPU time 111.52 seconds
Started Jun 13 03:27:20 PM PDT 24
Finished Jun 13 03:29:12 PM PDT 24
Peak memory 261436 kb
Host smart-3209ac6e-8040-491d-b6ab-7f73b5176306
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263161782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.263161782
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1904684851
Short name T633
Test name
Test status
Simulation time 13371600 ps
CPU time 15.87 seconds
Started Jun 13 03:27:23 PM PDT 24
Finished Jun 13 03:27:40 PM PDT 24
Peak memory 275240 kb
Host smart-e171aba1-5996-4407-a833-930600b6d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904684851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1904684851
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1559324911
Short name T789
Test name
Test status
Simulation time 38817300 ps
CPU time 110.47 seconds
Started Jun 13 03:27:23 PM PDT 24
Finished Jun 13 03:29:14 PM PDT 24
Peak memory 261392 kb
Host smart-a3c5ad57-325d-460d-8152-f6da937e969e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559324911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1559324911
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.1233980912
Short name T804
Test name
Test status
Simulation time 38137300 ps
CPU time 15.87 seconds
Started Jun 13 03:27:22 PM PDT 24
Finished Jun 13 03:27:38 PM PDT 24
Peak memory 284492 kb
Host smart-bc068d9d-eef6-48d5-917b-a70c11f23264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233980912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.1233980912
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.2242209881
Short name T436
Test name
Test status
Simulation time 31847000 ps
CPU time 13.93 seconds
Started Jun 13 03:20:20 PM PDT 24
Finished Jun 13 03:20:35 PM PDT 24
Peak memory 258620 kb
Host smart-057b3800-5eb7-4e46-aeec-14c42987d21a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242209881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2
242209881
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3043511140
Short name T1043
Test name
Test status
Simulation time 43739000 ps
CPU time 15.68 seconds
Started Jun 13 03:20:18 PM PDT 24
Finished Jun 13 03:20:34 PM PDT 24
Peak memory 275156 kb
Host smart-dc8a6aee-d2cd-47f3-b3ab-bc53822aca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043511140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3043511140
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.4066784155
Short name T346
Test name
Test status
Simulation time 11216600 ps
CPU time 21.9 seconds
Started Jun 13 03:20:16 PM PDT 24
Finished Jun 13 03:20:38 PM PDT 24
Peak memory 265912 kb
Host smart-abd2a3ee-98d8-4c07-8e5a-6473bfadd877
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066784155 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.4066784155
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.456400610
Short name T643
Test name
Test status
Simulation time 7740974400 ps
CPU time 2525.95 seconds
Started Jun 13 03:20:02 PM PDT 24
Finished Jun 13 04:02:09 PM PDT 24
Peak memory 264988 kb
Host smart-6b37fc3d-25e0-437a-9da3-c0aabd77c4f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456400610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_erro
r_mp.456400610
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.466586267
Short name T635
Test name
Test status
Simulation time 3263396900 ps
CPU time 840.01 seconds
Started Jun 13 03:20:01 PM PDT 24
Finished Jun 13 03:34:02 PM PDT 24
Peak memory 270820 kb
Host smart-14cc7a5b-cfb6-40be-8de6-bf56902ff138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466586267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.466586267
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2832050794
Short name T596
Test name
Test status
Simulation time 606841600 ps
CPU time 25.66 seconds
Started Jun 13 03:20:01 PM PDT 24
Finished Jun 13 03:20:28 PM PDT 24
Peak memory 263972 kb
Host smart-7461c7ed-89ac-46ca-8b63-a8cfdaa8080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832050794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2832050794
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.351705053
Short name T1092
Test name
Test status
Simulation time 10011554100 ps
CPU time 128.83 seconds
Started Jun 13 03:20:17 PM PDT 24
Finished Jun 13 03:22:26 PM PDT 24
Peak memory 330104 kb
Host smart-984a67f4-3a2d-4f0a-b11a-2de25fee07e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351705053 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.351705053
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.655378731
Short name T815
Test name
Test status
Simulation time 47325200 ps
CPU time 13.95 seconds
Started Jun 13 03:20:19 PM PDT 24
Finished Jun 13 03:20:34 PM PDT 24
Peak memory 265352 kb
Host smart-cfc2691c-2ee3-4651-abda-6149416e9a7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655378731 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.655378731
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2089006619
Short name T1000
Test name
Test status
Simulation time 160171336500 ps
CPU time 1020.81 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:36:57 PM PDT 24
Peak memory 261204 kb
Host smart-b9401ca9-5a9c-400e-8ce7-67905d2e1247
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089006619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.2089006619
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2548774282
Short name T1028
Test name
Test status
Simulation time 5291318300 ps
CPU time 208.33 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:23:25 PM PDT 24
Peak memory 263472 kb
Host smart-09169b05-0f8a-496e-a1ed-e8ee29c70b37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548774282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.2548774282
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.241118182
Short name T853
Test name
Test status
Simulation time 1227407400 ps
CPU time 134.32 seconds
Started Jun 13 03:20:04 PM PDT 24
Finished Jun 13 03:22:19 PM PDT 24
Peak memory 291452 kb
Host smart-ec24af74-31ff-41d0-9487-526a412d1cb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241118182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.241118182
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1990419308
Short name T472
Test name
Test status
Simulation time 11647053800 ps
CPU time 162.6 seconds
Started Jun 13 03:20:13 PM PDT 24
Finished Jun 13 03:22:56 PM PDT 24
Peak memory 293500 kb
Host smart-8d4d3849-c483-4788-a69c-3cf9b84e15a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990419308 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1990419308
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.464012113
Short name T33
Test name
Test status
Simulation time 10570251600 ps
CPU time 81.4 seconds
Started Jun 13 03:20:17 PM PDT 24
Finished Jun 13 03:21:39 PM PDT 24
Peak memory 260364 kb
Host smart-a4010254-9dbb-42f8-a0eb-2d33b7a20c23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464012113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 6.flash_ctrl_intr_wr.464012113
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3971361915
Short name T728
Test name
Test status
Simulation time 97152466000 ps
CPU time 230.71 seconds
Started Jun 13 03:20:13 PM PDT 24
Finished Jun 13 03:24:04 PM PDT 24
Peak memory 260744 kb
Host smart-2417e67a-b8cc-4346-ab59-2f7257ba6cf4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397
1361915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3971361915
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.932448518
Short name T502
Test name
Test status
Simulation time 3377345700 ps
CPU time 65.85 seconds
Started Jun 13 03:20:01 PM PDT 24
Finished Jun 13 03:21:08 PM PDT 24
Peak memory 263588 kb
Host smart-5a684387-c5bc-4c46-9302-74ceb93294b8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932448518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.932448518
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.85389072
Short name T1033
Test name
Test status
Simulation time 16183300 ps
CPU time 13.37 seconds
Started Jun 13 03:20:19 PM PDT 24
Finished Jun 13 03:20:33 PM PDT 24
Peak memory 260348 kb
Host smart-2805e1ee-5bee-4af0-9c58-49326c286b48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85389072 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.85389072
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1815387925
Short name T132
Test name
Test status
Simulation time 11432145400 ps
CPU time 244.75 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:24:00 PM PDT 24
Peak memory 275184 kb
Host smart-887f8160-c163-4e39-9871-a56d9fceff48
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815387925 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.1815387925
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2945278987
Short name T539
Test name
Test status
Simulation time 61563900 ps
CPU time 133.44 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:22:10 PM PDT 24
Peak memory 262888 kb
Host smart-235f1f86-842d-4b00-a213-e49ace93b13c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945278987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2945278987
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3792785382
Short name T858
Test name
Test status
Simulation time 3154531300 ps
CPU time 423.04 seconds
Started Jun 13 03:19:55 PM PDT 24
Finished Jun 13 03:26:59 PM PDT 24
Peak memory 263480 kb
Host smart-1ddca0b2-e866-40c8-a6c8-60ddc0691f03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792785382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3792785382
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.3821530712
Short name T957
Test name
Test status
Simulation time 33363300 ps
CPU time 13.49 seconds
Started Jun 13 03:20:13 PM PDT 24
Finished Jun 13 03:20:27 PM PDT 24
Peak memory 265636 kb
Host smart-2da996bd-0272-403b-9c1a-79098f35c7dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821530712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.3821530712
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.735852915
Short name T128
Test name
Test status
Simulation time 166145700 ps
CPU time 98.61 seconds
Started Jun 13 03:19:54 PM PDT 24
Finished Jun 13 03:21:33 PM PDT 24
Peak memory 269724 kb
Host smart-f3e565ba-82b0-4207-a870-fe88271e61fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735852915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.735852915
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3623771157
Short name T581
Test name
Test status
Simulation time 87844300 ps
CPU time 33.5 seconds
Started Jun 13 03:20:14 PM PDT 24
Finished Jun 13 03:20:48 PM PDT 24
Peak memory 275808 kb
Host smart-cdcef33c-a7b7-420c-923a-f5fcf85c2f64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623771157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3623771157
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3821850509
Short name T191
Test name
Test status
Simulation time 534487000 ps
CPU time 100.88 seconds
Started Jun 13 03:20:06 PM PDT 24
Finished Jun 13 03:21:47 PM PDT 24
Peak memory 297848 kb
Host smart-a2f56ee2-ae0d-4df5-acc5-51124202cd64
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821850509 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.3821850509
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3469905557
Short name T188
Test name
Test status
Simulation time 2679731400 ps
CPU time 167.59 seconds
Started Jun 13 03:20:07 PM PDT 24
Finished Jun 13 03:22:55 PM PDT 24
Peak memory 283560 kb
Host smart-297c40a5-7879-433b-aeee-c2aa45fde3d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3469905557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3469905557
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.132797113
Short name T808
Test name
Test status
Simulation time 2578619000 ps
CPU time 123.01 seconds
Started Jun 13 03:20:06 PM PDT 24
Finished Jun 13 03:22:10 PM PDT 24
Peak memory 295488 kb
Host smart-fb0b799e-225d-4428-a63e-d4b080f30e95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132797113 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.132797113
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.133921871
Short name T529
Test name
Test status
Simulation time 3878088800 ps
CPU time 560.79 seconds
Started Jun 13 03:20:06 PM PDT 24
Finished Jun 13 03:29:28 PM PDT 24
Peak memory 315020 kb
Host smart-b26780cc-8c60-4ad2-807b-ba19b011d984
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133921871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.133921871
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.1897839386
Short name T184
Test name
Test status
Simulation time 16300092300 ps
CPU time 651.29 seconds
Started Jun 13 03:20:05 PM PDT 24
Finished Jun 13 03:30:57 PM PDT 24
Peak memory 340536 kb
Host smart-84ecd9d6-da0a-4cca-9a88-29265b84d756
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897839386 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.1897839386
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3440773799
Short name T319
Test name
Test status
Simulation time 30934100 ps
CPU time 31.99 seconds
Started Jun 13 03:20:11 PM PDT 24
Finished Jun 13 03:20:43 PM PDT 24
Peak memory 275812 kb
Host smart-8054f3d6-5fa4-4c9f-8b20-edae6e5b8cec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440773799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3440773799
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.200378890
Short name T318
Test name
Test status
Simulation time 48732200 ps
CPU time 30.66 seconds
Started Jun 13 03:20:14 PM PDT 24
Finished Jun 13 03:20:45 PM PDT 24
Peak memory 275260 kb
Host smart-d96a7807-a053-4dce-8d77-f7f32bc4d704
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200378890 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.200378890
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.1604472659
Short name T958
Test name
Test status
Simulation time 18556284800 ps
CPU time 799.01 seconds
Started Jun 13 03:20:07 PM PDT 24
Finished Jun 13 03:33:26 PM PDT 24
Peak memory 321064 kb
Host smart-2c9aee67-0866-4b25-b160-9167a10cd7f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604472659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.1604472659
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.870023462
Short name T375
Test name
Test status
Simulation time 6317480800 ps
CPU time 67.73 seconds
Started Jun 13 03:20:13 PM PDT 24
Finished Jun 13 03:21:22 PM PDT 24
Peak memory 264048 kb
Host smart-ee85c9ba-f0d7-4428-90fa-853d4aedaa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870023462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.870023462
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3680051040
Short name T692
Test name
Test status
Simulation time 68282300 ps
CPU time 119.26 seconds
Started Jun 13 03:19:52 PM PDT 24
Finished Jun 13 03:21:52 PM PDT 24
Peak memory 277468 kb
Host smart-2820e24d-33f7-4cee-b803-8219981db5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680051040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3680051040
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.914562002
Short name T1062
Test name
Test status
Simulation time 14884571000 ps
CPU time 254.94 seconds
Started Jun 13 03:20:07 PM PDT 24
Finished Jun 13 03:24:22 PM PDT 24
Peak memory 265584 kb
Host smart-6bd9d3e8-dcea-4db8-9e8d-d72c20dff54e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914562002 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_wo.914562002
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3188812761
Short name T92
Test name
Test status
Simulation time 235995000 ps
CPU time 16 seconds
Started Jun 13 03:27:20 PM PDT 24
Finished Jun 13 03:27:37 PM PDT 24
Peak memory 275260 kb
Host smart-0f558c4d-d06f-4c24-a39f-ee8355669916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188812761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3188812761
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.1791710084
Short name T166
Test name
Test status
Simulation time 44469700 ps
CPU time 135.07 seconds
Started Jun 13 03:27:23 PM PDT 24
Finished Jun 13 03:29:39 PM PDT 24
Peak memory 260296 kb
Host smart-806419f9-7c7e-4d54-935a-78c6d5f43bbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791710084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.1791710084
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1491827206
Short name T942
Test name
Test status
Simulation time 28416200 ps
CPU time 13.35 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:27:41 PM PDT 24
Peak memory 284616 kb
Host smart-a119a79c-c019-4af5-8831-c8d1b4d16323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491827206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1491827206
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3290348974
Short name T421
Test name
Test status
Simulation time 40683700 ps
CPU time 132.11 seconds
Started Jun 13 03:27:21 PM PDT 24
Finished Jun 13 03:29:34 PM PDT 24
Peak memory 260332 kb
Host smart-4fa562c7-6ef3-47e9-86d8-48d4f1b37dd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290348974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3290348974
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2749353120
Short name T597
Test name
Test status
Simulation time 14807600 ps
CPU time 15.74 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:27:43 PM PDT 24
Peak memory 275124 kb
Host smart-70824401-6b84-4547-b971-321bffeacd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749353120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2749353120
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.828765018
Short name T817
Test name
Test status
Simulation time 15624400 ps
CPU time 13.27 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:27:41 PM PDT 24
Peak memory 284504 kb
Host smart-0b64be46-704a-4245-adca-9f7b659688a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828765018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.828765018
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.881372025
Short name T659
Test name
Test status
Simulation time 201746100 ps
CPU time 132.75 seconds
Started Jun 13 03:27:29 PM PDT 24
Finished Jun 13 03:29:43 PM PDT 24
Peak memory 264664 kb
Host smart-2f351006-5aec-4512-99b0-1184501808b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881372025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.881372025
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2356603145
Short name T590
Test name
Test status
Simulation time 26552200 ps
CPU time 15.86 seconds
Started Jun 13 03:27:28 PM PDT 24
Finished Jun 13 03:27:44 PM PDT 24
Peak memory 275420 kb
Host smart-09f83d71-18bb-4431-aff1-29ca55e0ba65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356603145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2356603145
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.4292849788
Short name T770
Test name
Test status
Simulation time 40349700 ps
CPU time 108.89 seconds
Started Jun 13 03:27:24 PM PDT 24
Finished Jun 13 03:29:13 PM PDT 24
Peak memory 260476 kb
Host smart-b6ec9dc0-a069-4023-8dd9-c5a1204aa817
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292849788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.4292849788
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.250053633
Short name T753
Test name
Test status
Simulation time 77341900 ps
CPU time 15.49 seconds
Started Jun 13 03:27:30 PM PDT 24
Finished Jun 13 03:27:46 PM PDT 24
Peak memory 275152 kb
Host smart-3bb64afb-8ae8-41d3-84db-feb796854d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250053633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.250053633
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3304624849
Short name T641
Test name
Test status
Simulation time 144233400 ps
CPU time 134.6 seconds
Started Jun 13 03:27:25 PM PDT 24
Finished Jun 13 03:29:41 PM PDT 24
Peak memory 260752 kb
Host smart-02f57bb5-4673-4826-8d27-c4962990a613
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304624849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3304624849
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.3418439170
Short name T1096
Test name
Test status
Simulation time 24756900 ps
CPU time 15.8 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:27:43 PM PDT 24
Peak memory 275092 kb
Host smart-8c837098-378b-4bd0-9aee-351a62ea9ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418439170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3418439170
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.612857747
Short name T1077
Test name
Test status
Simulation time 34887800 ps
CPU time 131.96 seconds
Started Jun 13 03:27:24 PM PDT 24
Finished Jun 13 03:29:36 PM PDT 24
Peak memory 265804 kb
Host smart-5e7e440c-ce17-458e-8125-73d982bb5c75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612857747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.612857747
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1477845159
Short name T387
Test name
Test status
Simulation time 15561600 ps
CPU time 15.82 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:27:43 PM PDT 24
Peak memory 275212 kb
Host smart-cae3fd30-6b53-4754-8d92-f5c088957e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477845159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1477845159
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.1835814070
Short name T843
Test name
Test status
Simulation time 38871400 ps
CPU time 132.04 seconds
Started Jun 13 03:27:29 PM PDT 24
Finished Jun 13 03:29:42 PM PDT 24
Peak memory 261428 kb
Host smart-2f6c4bb9-5d64-4cc1-8a4f-0818ef37f06f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835814070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.1835814070
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.508813422
Short name T922
Test name
Test status
Simulation time 37549000 ps
CPU time 16.07 seconds
Started Jun 13 03:27:30 PM PDT 24
Finished Jun 13 03:27:47 PM PDT 24
Peak memory 284492 kb
Host smart-13d6567a-52aa-4ebd-96f4-95953373858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508813422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.508813422
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3347812237
Short name T962
Test name
Test status
Simulation time 99911700 ps
CPU time 132.39 seconds
Started Jun 13 03:27:25 PM PDT 24
Finished Jun 13 03:29:38 PM PDT 24
Peak memory 265548 kb
Host smart-64e3877a-6c36-44f6-b588-4a0fccf9b194
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347812237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3347812237
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3894812941
Short name T621
Test name
Test status
Simulation time 36652400 ps
CPU time 16.1 seconds
Started Jun 13 03:27:32 PM PDT 24
Finished Jun 13 03:27:49 PM PDT 24
Peak memory 275236 kb
Host smart-cfdad911-af38-4468-83b9-1620c630e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894812941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3894812941
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2410202500
Short name T494
Test name
Test status
Simulation time 82111300 ps
CPU time 110.86 seconds
Started Jun 13 03:27:27 PM PDT 24
Finished Jun 13 03:29:18 PM PDT 24
Peak memory 261480 kb
Host smart-75dbe317-bd26-473e-8c82-f7b0c7d27410
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410202500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2410202500
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.197583067
Short name T1029
Test name
Test status
Simulation time 79435400 ps
CPU time 13.6 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:20:51 PM PDT 24
Peak memory 258668 kb
Host smart-3307e07b-82c9-42ee-997e-94479f07cf35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197583067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.197583067
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2655136148
Short name T798
Test name
Test status
Simulation time 24768700 ps
CPU time 15.63 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:20:54 PM PDT 24
Peak memory 275184 kb
Host smart-b9f46a5a-1c98-4022-b309-4f1b1ad5e811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655136148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2655136148
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2727293495
Short name T908
Test name
Test status
Simulation time 27880000 ps
CPU time 22.12 seconds
Started Jun 13 03:20:39 PM PDT 24
Finished Jun 13 03:21:01 PM PDT 24
Peak memory 266000 kb
Host smart-a9be1dd7-37b3-4701-b353-e2ffb043832a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727293495 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2727293495
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3469375748
Short name T736
Test name
Test status
Simulation time 65057954000 ps
CPU time 2459.42 seconds
Started Jun 13 03:20:26 PM PDT 24
Finished Jun 13 04:01:26 PM PDT 24
Peak memory 263100 kb
Host smart-195cc687-ddbb-45a7-ab95-b839d2f2efe0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469375748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3469375748
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3208752293
Short name T870
Test name
Test status
Simulation time 18097297600 ps
CPU time 976.02 seconds
Started Jun 13 03:20:24 PM PDT 24
Finished Jun 13 03:36:41 PM PDT 24
Peak memory 272996 kb
Host smart-d6f6ac99-986f-4040-8830-993baa4a46eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208752293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3208752293
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.2223680737
Short name T49
Test name
Test status
Simulation time 655057200 ps
CPU time 26.91 seconds
Started Jun 13 03:20:25 PM PDT 24
Finished Jun 13 03:20:53 PM PDT 24
Peak memory 262864 kb
Host smart-41aed758-73ef-4d95-bde2-08c8e4fc97d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223680737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.2223680737
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.655455234
Short name T272
Test name
Test status
Simulation time 10013291800 ps
CPU time 97.27 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:22:16 PM PDT 24
Peak memory 297908 kb
Host smart-feae9fea-4750-4fc2-a96b-c3c53244c7ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655455234 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.655455234
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2236826601
Short name T269
Test name
Test status
Simulation time 15815900 ps
CPU time 13.43 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:20:52 PM PDT 24
Peak memory 265948 kb
Host smart-9449ba57-3c6b-431a-b807-6862d8f50d8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236826601 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2236826601
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1771362440
Short name T565
Test name
Test status
Simulation time 2065307500 ps
CPU time 73.23 seconds
Started Jun 13 03:20:21 PM PDT 24
Finished Jun 13 03:21:34 PM PDT 24
Peak memory 263536 kb
Host smart-44783187-edf0-4a7f-8520-21ae7333716f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771362440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1771362440
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.459985739
Short name T524
Test name
Test status
Simulation time 25887762300 ps
CPU time 287.29 seconds
Started Jun 13 03:20:34 PM PDT 24
Finished Jun 13 03:25:22 PM PDT 24
Peak memory 291356 kb
Host smart-2386d9a3-440a-4858-85c6-a8dcd09cea1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459985739 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.459985739
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3827984850
Short name T939
Test name
Test status
Simulation time 2214691900 ps
CPU time 62.21 seconds
Started Jun 13 03:20:32 PM PDT 24
Finished Jun 13 03:21:35 PM PDT 24
Peak memory 260768 kb
Host smart-076224e0-7b51-4032-8891-708e939a748d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827984850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3827984850
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3687749177
Short name T402
Test name
Test status
Simulation time 42884323300 ps
CPU time 181.68 seconds
Started Jun 13 03:20:32 PM PDT 24
Finished Jun 13 03:23:34 PM PDT 24
Peak memory 260676 kb
Host smart-e41c3a13-0d96-4e35-a05a-2e1efce7ab3d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368
7749177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3687749177
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.3502558054
Short name T383
Test name
Test status
Simulation time 7655961400 ps
CPU time 67.38 seconds
Started Jun 13 03:20:32 PM PDT 24
Finished Jun 13 03:21:40 PM PDT 24
Peak memory 260952 kb
Host smart-7d352a51-cb57-4a5d-8996-f5ac985c5c10
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502558054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3502558054
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.1149858667
Short name T617
Test name
Test status
Simulation time 4850724000 ps
CPU time 128.32 seconds
Started Jun 13 03:20:24 PM PDT 24
Finished Jun 13 03:22:33 PM PDT 24
Peak memory 265536 kb
Host smart-292f3eb5-8747-4dbf-aa2e-eaa9922020f6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149858667 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.1149858667
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.807242069
Short name T169
Test name
Test status
Simulation time 149112900 ps
CPU time 108.99 seconds
Started Jun 13 03:20:29 PM PDT 24
Finished Jun 13 03:22:18 PM PDT 24
Peak memory 261500 kb
Host smart-c52c0d6e-c04f-4905-9a29-5716f39fe328
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807242069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.807242069
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1593465724
Short name T480
Test name
Test status
Simulation time 3485047500 ps
CPU time 245.78 seconds
Started Jun 13 03:20:22 PM PDT 24
Finished Jun 13 03:24:28 PM PDT 24
Peak memory 263292 kb
Host smart-e78f51bb-fce1-4300-a713-79eef772b5f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593465724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1593465724
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3110467607
Short name T1032
Test name
Test status
Simulation time 23623800 ps
CPU time 13.7 seconds
Started Jun 13 03:20:34 PM PDT 24
Finished Jun 13 03:20:49 PM PDT 24
Peak memory 259692 kb
Host smart-84b7edb0-1388-4d5d-b797-4d7c07141041
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110467607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3110467607
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.436974046
Short name T479
Test name
Test status
Simulation time 119406400 ps
CPU time 779.32 seconds
Started Jun 13 03:20:18 PM PDT 24
Finished Jun 13 03:33:18 PM PDT 24
Peak memory 285876 kb
Host smart-02ffbd40-e103-4f77-aaa3-c2f16299e23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436974046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.436974046
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.957228335
Short name T944
Test name
Test status
Simulation time 362064600 ps
CPU time 33.78 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:21:11 PM PDT 24
Peak memory 270156 kb
Host smart-22554fc2-fbc3-4d70-bbdd-63cf519e8bef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957228335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_re_evict.957228335
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.971384511
Short name T610
Test name
Test status
Simulation time 2509569400 ps
CPU time 131.32 seconds
Started Jun 13 03:20:27 PM PDT 24
Finished Jun 13 03:22:39 PM PDT 24
Peak memory 297628 kb
Host smart-2dd0ec61-6e2b-4215-b157-858625704fa2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971384511 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.flash_ctrl_ro.971384511
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.314339999
Short name T919
Test name
Test status
Simulation time 600737800 ps
CPU time 130.17 seconds
Started Jun 13 03:20:34 PM PDT 24
Finished Jun 13 03:22:45 PM PDT 24
Peak memory 283388 kb
Host smart-60d04879-5a7b-42e2-afd7-a5cab441741d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
314339999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.314339999
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.1428155468
Short name T554
Test name
Test status
Simulation time 1878923400 ps
CPU time 122.25 seconds
Started Jun 13 03:20:31 PM PDT 24
Finished Jun 13 03:22:35 PM PDT 24
Peak memory 282328 kb
Host smart-13f3a1ec-5166-4edd-9030-727652c71764
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428155468 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.1428155468
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.2556312833
Short name T938
Test name
Test status
Simulation time 8480689700 ps
CPU time 638.65 seconds
Started Jun 13 03:20:28 PM PDT 24
Finished Jun 13 03:31:07 PM PDT 24
Peak memory 314888 kb
Host smart-17fb3f01-43af-4e2d-86e7-b744d33f489a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556312833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.2556312833
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2011914949
Short name T686
Test name
Test status
Simulation time 220058600 ps
CPU time 31.08 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:21:09 PM PDT 24
Peak memory 275864 kb
Host smart-095815ac-11e0-4843-82e0-8e628b5d482f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011914949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2011914949
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3143083002
Short name T809
Test name
Test status
Simulation time 77860700 ps
CPU time 30.87 seconds
Started Jun 13 03:20:39 PM PDT 24
Finished Jun 13 03:21:10 PM PDT 24
Peak memory 268332 kb
Host smart-552920a4-2039-438a-9e70-9e4d1466c53f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143083002 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.3143083002
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.2198217101
Short name T359
Test name
Test status
Simulation time 2366400100 ps
CPU time 65.77 seconds
Started Jun 13 03:20:37 PM PDT 24
Finished Jun 13 03:21:43 PM PDT 24
Peak memory 264064 kb
Host smart-c9788869-f4ef-47e8-860b-75f72eb5c218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198217101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2198217101
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.1336183901
Short name T1070
Test name
Test status
Simulation time 42115900 ps
CPU time 168.16 seconds
Started Jun 13 03:20:19 PM PDT 24
Finished Jun 13 03:23:07 PM PDT 24
Peak memory 277636 kb
Host smart-2f2ff530-d157-4116-af84-838ab9a84493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336183901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1336183901
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3955753424
Short name T1021
Test name
Test status
Simulation time 5780121700 ps
CPU time 168.68 seconds
Started Jun 13 03:20:28 PM PDT 24
Finished Jun 13 03:23:17 PM PDT 24
Peak memory 265768 kb
Host smart-7af07ca8-fde6-467e-b56f-421131373265
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955753424 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3955753424
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1002544175
Short name T106
Test name
Test status
Simulation time 45221000 ps
CPU time 16.17 seconds
Started Jun 13 03:27:31 PM PDT 24
Finished Jun 13 03:27:47 PM PDT 24
Peak memory 275160 kb
Host smart-f05c6b18-11ec-4c29-8093-66b9ffb4b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002544175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1002544175
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1233029937
Short name T696
Test name
Test status
Simulation time 37799100 ps
CPU time 135.24 seconds
Started Jun 13 03:27:35 PM PDT 24
Finished Jun 13 03:29:51 PM PDT 24
Peak memory 260328 kb
Host smart-cad0951c-67a2-4ad7-82e7-dfda9b07a7da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233029937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1233029937
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2091149425
Short name T713
Test name
Test status
Simulation time 19860300 ps
CPU time 15.93 seconds
Started Jun 13 03:27:34 PM PDT 24
Finished Jun 13 03:27:51 PM PDT 24
Peak memory 275228 kb
Host smart-3e14fb2f-951c-4ef7-90f9-e92169482490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091149425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2091149425
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.998484522
Short name T167
Test name
Test status
Simulation time 136354700 ps
CPU time 133.54 seconds
Started Jun 13 03:27:32 PM PDT 24
Finished Jun 13 03:29:46 PM PDT 24
Peak memory 260236 kb
Host smart-28b4cdfd-e6d9-4b57-b92c-13769f811e58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998484522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.998484522
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2728996665
Short name T463
Test name
Test status
Simulation time 53456500 ps
CPU time 16.27 seconds
Started Jun 13 03:27:30 PM PDT 24
Finished Jun 13 03:27:47 PM PDT 24
Peak memory 275148 kb
Host smart-b83c06b9-ced4-4514-a620-73c3be7d4dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728996665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2728996665
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.1787189145
Short name T802
Test name
Test status
Simulation time 140999200 ps
CPU time 134.02 seconds
Started Jun 13 03:27:34 PM PDT 24
Finished Jun 13 03:29:50 PM PDT 24
Peak memory 260424 kb
Host smart-047aed87-fda6-4e9c-8efa-3ea0f2d96e23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787189145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.1787189145
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.2256083056
Short name T244
Test name
Test status
Simulation time 80182900 ps
CPU time 15.63 seconds
Started Jun 13 03:27:36 PM PDT 24
Finished Jun 13 03:27:53 PM PDT 24
Peak memory 275260 kb
Host smart-cef22e93-52dc-4ffa-9ba8-15c061032440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256083056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2256083056
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3145587337
Short name T901
Test name
Test status
Simulation time 159763500 ps
CPU time 108.88 seconds
Started Jun 13 03:27:36 PM PDT 24
Finished Jun 13 03:29:27 PM PDT 24
Peak memory 260640 kb
Host smart-ad6e6a90-d2aa-4de4-af8c-645bdee4c742
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145587337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3145587337
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.822450817
Short name T652
Test name
Test status
Simulation time 46352900 ps
CPU time 15.92 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:27:54 PM PDT 24
Peak memory 275036 kb
Host smart-d27c89dc-67b7-48f2-af7d-396214d77752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822450817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.822450817
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2265981720
Short name T350
Test name
Test status
Simulation time 38951000 ps
CPU time 133.86 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:29:53 PM PDT 24
Peak memory 265016 kb
Host smart-25091254-5684-40ce-8f2e-195ba099b36c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265981720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2265981720
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.1760314559
Short name T749
Test name
Test status
Simulation time 82990700 ps
CPU time 15.69 seconds
Started Jun 13 03:27:36 PM PDT 24
Finished Jun 13 03:27:52 PM PDT 24
Peak memory 275220 kb
Host smart-8ee66aed-f6b5-43b2-bcd1-c104f816074d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760314559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1760314559
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.1624336563
Short name T1019
Test name
Test status
Simulation time 201192100 ps
CPU time 131.22 seconds
Started Jun 13 03:27:36 PM PDT 24
Finished Jun 13 03:29:49 PM PDT 24
Peak memory 265304 kb
Host smart-9cdc6abf-6e82-45ca-ab51-41460dfe1d70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624336563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.1624336563
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.970799294
Short name T93
Test name
Test status
Simulation time 22518200 ps
CPU time 15.94 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:27:54 PM PDT 24
Peak memory 275244 kb
Host smart-7956875d-c2e7-4302-87a4-8b398ee30026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970799294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.970799294
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3296499267
Short name T739
Test name
Test status
Simulation time 129615200 ps
CPU time 133.94 seconds
Started Jun 13 03:27:38 PM PDT 24
Finished Jun 13 03:29:53 PM PDT 24
Peak memory 261256 kb
Host smart-a2b7fa85-ba46-4b53-a14f-62570748fae6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296499267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3296499267
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.1744845413
Short name T1069
Test name
Test status
Simulation time 73595900 ps
CPU time 15.65 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:27:54 PM PDT 24
Peak memory 275140 kb
Host smart-3954a243-2c61-4f10-94f9-0aa686083606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744845413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.1744845413
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1226826986
Short name T168
Test name
Test status
Simulation time 34609700 ps
CPU time 132.37 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:29:51 PM PDT 24
Peak memory 265088 kb
Host smart-cbb1bad7-a9a0-44b4-b584-818f336947ea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226826986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1226826986
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.2365328513
Short name T493
Test name
Test status
Simulation time 16647100 ps
CPU time 15.89 seconds
Started Jun 13 03:27:37 PM PDT 24
Finished Jun 13 03:27:55 PM PDT 24
Peak memory 275100 kb
Host smart-07a047f5-d7df-4e3e-b67c-fab9cb2247ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365328513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2365328513
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.1004329694
Short name T466
Test name
Test status
Simulation time 24971700 ps
CPU time 15.5 seconds
Started Jun 13 03:27:38 PM PDT 24
Finished Jun 13 03:27:55 PM PDT 24
Peak memory 275312 kb
Host smart-9b81440f-7b7e-428a-b2ab-1a1f55b04f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004329694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1004329694
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.1032127431
Short name T101
Test name
Test status
Simulation time 219884100 ps
CPU time 131.72 seconds
Started Jun 13 03:27:42 PM PDT 24
Finished Jun 13 03:29:54 PM PDT 24
Peak memory 260784 kb
Host smart-802a5a2f-3091-45ec-bb23-2a0c920e6fea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032127431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.1032127431
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.205514200
Short name T706
Test name
Test status
Simulation time 68967700 ps
CPU time 13.94 seconds
Started Jun 13 03:21:07 PM PDT 24
Finished Jun 13 03:21:22 PM PDT 24
Peak memory 265580 kb
Host smart-b3f692dd-295c-4670-ba3f-14c680679b6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205514200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.205514200
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.3803845077
Short name T19
Test name
Test status
Simulation time 14830500 ps
CPU time 13.32 seconds
Started Jun 13 03:21:02 PM PDT 24
Finished Jun 13 03:21:16 PM PDT 24
Peak memory 284552 kb
Host smart-2ceaf174-274d-441d-ac67-0590668dcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803845077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3803845077
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1774825965
Short name T845
Test name
Test status
Simulation time 38683100 ps
CPU time 21.67 seconds
Started Jun 13 03:21:01 PM PDT 24
Finished Jun 13 03:21:23 PM PDT 24
Peak memory 265328 kb
Host smart-72fac269-a6d3-48b1-83c7-781ff93a743b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774825965 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1774825965
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3441643914
Short name T541
Test name
Test status
Simulation time 16798220900 ps
CPU time 2239 seconds
Started Jun 13 03:20:44 PM PDT 24
Finished Jun 13 03:58:04 PM PDT 24
Peak memory 264692 kb
Host smart-6bd1a5f2-3e97-4eb3-b621-662e1b6f74b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441643914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.3441643914
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.633680822
Short name T685
Test name
Test status
Simulation time 14681457000 ps
CPU time 1078.08 seconds
Started Jun 13 03:20:45 PM PDT 24
Finished Jun 13 03:38:44 PM PDT 24
Peak memory 272828 kb
Host smart-f55acf6a-aad8-4a7f-b12b-427674ae8a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633680822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.633680822
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.3175353624
Short name T575
Test name
Test status
Simulation time 142771100 ps
CPU time 25.57 seconds
Started Jun 13 03:20:44 PM PDT 24
Finished Jun 13 03:21:10 PM PDT 24
Peak memory 263964 kb
Host smart-fb9d2c15-a6d2-4f86-9c94-ee98372b5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175353624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.3175353624
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1423635132
Short name T1014
Test name
Test status
Simulation time 10067721800 ps
CPU time 62.66 seconds
Started Jun 13 03:21:07 PM PDT 24
Finished Jun 13 03:22:10 PM PDT 24
Peak memory 265804 kb
Host smart-9c17ab50-aa03-4a14-a68a-ea98e6c7c2e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423635132 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1423635132
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1531958264
Short name T669
Test name
Test status
Simulation time 61356800 ps
CPU time 13.2 seconds
Started Jun 13 03:20:58 PM PDT 24
Finished Jun 13 03:21:12 PM PDT 24
Peak memory 265788 kb
Host smart-2685e9cc-8d01-41cd-bde3-e0edc68d4de0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531958264 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1531958264
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2072751325
Short name T103
Test name
Test status
Simulation time 540455111600 ps
CPU time 1205.83 seconds
Started Jun 13 03:20:44 PM PDT 24
Finished Jun 13 03:40:51 PM PDT 24
Peak memory 264532 kb
Host smart-edaa8909-65de-4de7-8b81-89acb97a971b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072751325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2072751325
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1708110015
Short name T429
Test name
Test status
Simulation time 3862224200 ps
CPU time 116.14 seconds
Started Jun 13 03:20:43 PM PDT 24
Finished Jun 13 03:22:40 PM PDT 24
Peak memory 263536 kb
Host smart-9b33f87e-00ec-4ded-bb1e-6a338929688a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708110015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1708110015
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2946942526
Short name T1078
Test name
Test status
Simulation time 12154602600 ps
CPU time 256.2 seconds
Started Jun 13 03:20:56 PM PDT 24
Finished Jun 13 03:25:13 PM PDT 24
Peak memory 285200 kb
Host smart-1e6a300b-804e-4d71-9355-f7b14dba6d48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946942526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2946942526
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1580177969
Short name T861
Test name
Test status
Simulation time 27955642500 ps
CPU time 293.17 seconds
Started Jun 13 03:20:55 PM PDT 24
Finished Jun 13 03:25:48 PM PDT 24
Peak memory 285268 kb
Host smart-6004ed9e-d1b1-4074-bbc3-255507f82891
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580177969 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.1580177969
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.681411574
Short name T563
Test name
Test status
Simulation time 10876065300 ps
CPU time 81.85 seconds
Started Jun 13 03:20:55 PM PDT 24
Finished Jun 13 03:22:18 PM PDT 24
Peak memory 265588 kb
Host smart-78da8611-667a-4b79-bc57-b00cb2277558
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681411574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.681411574
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2082033288
Short name T558
Test name
Test status
Simulation time 20438239900 ps
CPU time 172.08 seconds
Started Jun 13 03:20:55 PM PDT 24
Finished Jun 13 03:23:48 PM PDT 24
Peak memory 265584 kb
Host smart-13c95ed0-72b1-4a26-9705-699addff1147
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208
2033288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2082033288
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.761327938
Short name T127
Test name
Test status
Simulation time 3334878800 ps
CPU time 63.3 seconds
Started Jun 13 03:20:45 PM PDT 24
Finished Jun 13 03:21:49 PM PDT 24
Peak memory 263492 kb
Host smart-1c40353d-bb71-4688-bf89-52c890c84eb8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761327938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.761327938
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1921188680
Short name T275
Test name
Test status
Simulation time 30823100 ps
CPU time 13.39 seconds
Started Jun 13 03:21:00 PM PDT 24
Finished Jun 13 03:21:14 PM PDT 24
Peak memory 265552 kb
Host smart-74bd53e1-c820-48fe-8c65-910c3ad824f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921188680 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.1921188680
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.775982935
Short name T140
Test name
Test status
Simulation time 3774117400 ps
CPU time 177.94 seconds
Started Jun 13 03:20:46 PM PDT 24
Finished Jun 13 03:23:44 PM PDT 24
Peak memory 265508 kb
Host smart-01c62172-0e3e-46f2-b2f6-63f2f2bd33bb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775982935 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_mp_regions.775982935
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3549205893
Short name T550
Test name
Test status
Simulation time 28745300 ps
CPU time 65.87 seconds
Started Jun 13 03:20:43 PM PDT 24
Finished Jun 13 03:21:50 PM PDT 24
Peak memory 263352 kb
Host smart-f66b08eb-b971-4219-ab73-525ce1f8ad08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549205893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3549205893
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.64287197
Short name T700
Test name
Test status
Simulation time 21660500 ps
CPU time 13.99 seconds
Started Jun 13 03:20:57 PM PDT 24
Finished Jun 13 03:21:11 PM PDT 24
Peak memory 265780 kb
Host smart-5fc76d01-be5b-4eae-be9c-329b32de447a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64287197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset
.64287197
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.160391843
Short name T934
Test name
Test status
Simulation time 179710600 ps
CPU time 449.65 seconds
Started Jun 13 03:20:44 PM PDT 24
Finished Jun 13 03:28:15 PM PDT 24
Peak memory 281272 kb
Host smart-41712822-ca38-49dc-a8d4-cf49067303ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160391843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.160391843
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.4294664284
Short name T110
Test name
Test status
Simulation time 562681900 ps
CPU time 36.24 seconds
Started Jun 13 03:20:54 PM PDT 24
Finished Jun 13 03:21:31 PM PDT 24
Peak memory 275804 kb
Host smart-19fe778f-bd66-42f1-8f73-e5dec8e2114d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294664284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.4294664284
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.505942179
Short name T439
Test name
Test status
Simulation time 2300892800 ps
CPU time 153.61 seconds
Started Jun 13 03:20:45 PM PDT 24
Finished Jun 13 03:23:19 PM PDT 24
Peak memory 290540 kb
Host smart-f36c139f-0880-4e76-83e6-4b24887e501f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505942179 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.505942179
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2358603406
Short name T716
Test name
Test status
Simulation time 5644192700 ps
CPU time 173.58 seconds
Started Jun 13 03:20:50 PM PDT 24
Finished Jun 13 03:23:44 PM PDT 24
Peak memory 283452 kb
Host smart-80e25860-b786-4f61-8a22-5d08a8475b34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2358603406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2358603406
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1876476236
Short name T863
Test name
Test status
Simulation time 2435328200 ps
CPU time 152.23 seconds
Started Jun 13 03:20:51 PM PDT 24
Finished Jun 13 03:23:24 PM PDT 24
Peak memory 295636 kb
Host smart-63f3ec2d-b907-465e-8ae1-60efb44225cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876476236 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1876476236
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.2238438839
Short name T986
Test name
Test status
Simulation time 3671115800 ps
CPU time 510.7 seconds
Started Jun 13 03:20:49 PM PDT 24
Finished Jun 13 03:29:20 PM PDT 24
Peak memory 314912 kb
Host smart-4643f68f-e10d-4341-bf39-263260445073
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238438839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.2238438839
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.3932369169
Short name T1090
Test name
Test status
Simulation time 8537867400 ps
CPU time 653.51 seconds
Started Jun 13 03:20:49 PM PDT 24
Finished Jun 13 03:31:43 PM PDT 24
Peak memory 313432 kb
Host smart-67fb519e-be49-4607-a553-8bdc608cdac0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932369169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.3932369169
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.2476735472
Short name T366
Test name
Test status
Simulation time 368954600 ps
CPU time 54.64 seconds
Started Jun 13 03:21:01 PM PDT 24
Finished Jun 13 03:21:57 PM PDT 24
Peak memory 264036 kb
Host smart-4b509341-e8f6-4e32-ad29-5c9e865778e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476735472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2476735472
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3030852410
Short name T453
Test name
Test status
Simulation time 21361900 ps
CPU time 142.52 seconds
Started Jun 13 03:20:38 PM PDT 24
Finished Jun 13 03:23:01 PM PDT 24
Peak memory 278312 kb
Host smart-209e3557-ae03-4f54-bc2b-3bdf598a4920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030852410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3030852410
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.3315419777
Short name T634
Test name
Test status
Simulation time 3068109600 ps
CPU time 192.61 seconds
Started Jun 13 03:20:42 PM PDT 24
Finished Jun 13 03:23:55 PM PDT 24
Peak memory 265576 kb
Host smart-e440af04-ea55-4223-8d3a-ef931c260a02
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315419777 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.3315419777
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.1408874723
Short name T231
Test name
Test status
Simulation time 36702000 ps
CPU time 13.91 seconds
Started Jun 13 03:21:24 PM PDT 24
Finished Jun 13 03:21:38 PM PDT 24
Peak memory 265736 kb
Host smart-24184125-4f3c-4426-861f-1c3307a0172c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408874723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1
408874723
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.3658774303
Short name T603
Test name
Test status
Simulation time 27799200 ps
CPU time 16.1 seconds
Started Jun 13 03:21:24 PM PDT 24
Finished Jun 13 03:21:42 PM PDT 24
Peak memory 275376 kb
Host smart-3ed472c6-8e25-42dc-8365-1b24cc406be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658774303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3658774303
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.3175809798
Short name T67
Test name
Test status
Simulation time 30483000 ps
CPU time 20.41 seconds
Started Jun 13 03:21:26 PM PDT 24
Finished Jun 13 03:21:47 PM PDT 24
Peak memory 274128 kb
Host smart-a8ed56d6-905d-41d0-b75a-6ecd8b29f6dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175809798 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.3175809798
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.699022152
Short name T210
Test name
Test status
Simulation time 5652098700 ps
CPU time 2716.39 seconds
Started Jun 13 03:21:13 PM PDT 24
Finished Jun 13 04:06:30 PM PDT 24
Peak memory 265220 kb
Host smart-9e8f361e-efa1-48e1-a2d1-b61eec44e4d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699022152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_erro
r_mp.699022152
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3768100283
Short name T704
Test name
Test status
Simulation time 811631900 ps
CPU time 839.27 seconds
Started Jun 13 03:21:13 PM PDT 24
Finished Jun 13 03:35:13 PM PDT 24
Peak memory 270664 kb
Host smart-63a44864-b28c-4706-a658-3cea99502459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768100283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3768100283
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.2906923782
Short name T676
Test name
Test status
Simulation time 557352300 ps
CPU time 25.55 seconds
Started Jun 13 03:21:14 PM PDT 24
Finished Jun 13 03:21:40 PM PDT 24
Peak memory 263972 kb
Host smart-983eb84b-6fc4-49cf-8755-f10bb1180261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906923782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.2906923782
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.178935687
Short name T1066
Test name
Test status
Simulation time 10019569900 ps
CPU time 166.5 seconds
Started Jun 13 03:21:25 PM PDT 24
Finished Jun 13 03:24:13 PM PDT 24
Peak memory 280836 kb
Host smart-16c558d2-c24f-4225-8a2c-31eb41fdb741
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178935687 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.178935687
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3783866386
Short name T1093
Test name
Test status
Simulation time 24735900 ps
CPU time 13.47 seconds
Started Jun 13 03:21:27 PM PDT 24
Finished Jun 13 03:21:42 PM PDT 24
Peak memory 265436 kb
Host smart-8b147f7e-4c6d-494f-903d-4bc5ecedb52a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783866386 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3783866386
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2210900166
Short name T159
Test name
Test status
Simulation time 180178176400 ps
CPU time 925.34 seconds
Started Jun 13 03:21:06 PM PDT 24
Finished Jun 13 03:36:32 PM PDT 24
Peak memory 264672 kb
Host smart-c4b32e08-8abf-46fe-8641-59c8ceda5555
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210900166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2210900166
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1306170884
Short name T388
Test name
Test status
Simulation time 8035953200 ps
CPU time 89.89 seconds
Started Jun 13 03:21:07 PM PDT 24
Finished Jun 13 03:22:38 PM PDT 24
Peak memory 263488 kb
Host smart-1e43bdf4-f61d-40a6-92cd-b1eb4b06144f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306170884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1306170884
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.136693143
Short name T760
Test name
Test status
Simulation time 4012615400 ps
CPU time 175.25 seconds
Started Jun 13 03:21:18 PM PDT 24
Finished Jun 13 03:24:15 PM PDT 24
Peak memory 294512 kb
Host smart-d2d52b1c-25da-4f1f-a1e9-9f5cfc4fb344
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136693143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_intr_rd.136693143
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.82675429
Short name T312
Test name
Test status
Simulation time 7857957200 ps
CPU time 144.61 seconds
Started Jun 13 03:21:19 PM PDT 24
Finished Jun 13 03:23:44 PM PDT 24
Peak memory 292336 kb
Host smart-7a6552ed-0d27-4b54-9a59-7db31696bd69
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82675429 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.82675429
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3700509360
Short name T495
Test name
Test status
Simulation time 2353580100 ps
CPU time 72.07 seconds
Started Jun 13 03:21:19 PM PDT 24
Finished Jun 13 03:22:32 PM PDT 24
Peak memory 265468 kb
Host smart-4fbd8580-940c-4c14-99f8-01fd79e89b81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700509360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3700509360
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3281842663
Short name T878
Test name
Test status
Simulation time 83870463700 ps
CPU time 237.65 seconds
Started Jun 13 03:21:18 PM PDT 24
Finished Jun 13 03:25:16 PM PDT 24
Peak memory 265516 kb
Host smart-16a7541a-f790-422c-8279-4fb81314e821
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328
1842663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3281842663
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.3093929149
Short name T118
Test name
Test status
Simulation time 9496934400 ps
CPU time 72.84 seconds
Started Jun 13 03:21:13 PM PDT 24
Finished Jun 13 03:22:26 PM PDT 24
Peak memory 263948 kb
Host smart-15b3865c-d435-4687-bfa4-9c10fb1bdf3b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093929149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3093929149
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1381371487
Short name T107
Test name
Test status
Simulation time 17798600 ps
CPU time 13.8 seconds
Started Jun 13 03:22:30 PM PDT 24
Finished Jun 13 03:22:44 PM PDT 24
Peak memory 265280 kb
Host smart-8dc8c0d7-9afb-4b5a-a46c-fb4798ecd95b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381371487 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1381371487
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3471260087
Short name T133
Test name
Test status
Simulation time 26058347300 ps
CPU time 283.97 seconds
Started Jun 13 03:21:07 PM PDT 24
Finished Jun 13 03:25:52 PM PDT 24
Peak memory 275124 kb
Host smart-923dd1f1-fab8-46ff-8ac6-8b8fc6473474
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471260087 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3471260087
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.223049310
Short name T535
Test name
Test status
Simulation time 39982700 ps
CPU time 131.95 seconds
Started Jun 13 03:21:07 PM PDT 24
Finished Jun 13 03:23:20 PM PDT 24
Peak memory 264524 kb
Host smart-113eb3e5-2c92-4926-a698-da233e0948ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223049310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.223049310
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.4003301203
Short name T654
Test name
Test status
Simulation time 89805400 ps
CPU time 150.65 seconds
Started Jun 13 03:21:06 PM PDT 24
Finished Jun 13 03:23:38 PM PDT 24
Peak memory 263580 kb
Host smart-08abf2cd-abfc-452a-be10-8d0f38adb8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003301203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.4003301203
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.2508805922
Short name T677
Test name
Test status
Simulation time 61142400 ps
CPU time 13.45 seconds
Started Jun 13 03:21:20 PM PDT 24
Finished Jun 13 03:21:35 PM PDT 24
Peak memory 265552 kb
Host smart-ad866bfe-2234-4cc6-b2ef-99bab9f5e057
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508805922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.2508805922
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2363519484
Short name T1010
Test name
Test status
Simulation time 315337500 ps
CPU time 708.66 seconds
Started Jun 13 03:21:08 PM PDT 24
Finished Jun 13 03:32:57 PM PDT 24
Peak memory 286076 kb
Host smart-fc07ffb8-447b-4442-b793-cddbf9e5d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363519484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2363519484
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.1362898891
Short name T717
Test name
Test status
Simulation time 123807000 ps
CPU time 34.01 seconds
Started Jun 13 03:21:25 PM PDT 24
Finished Jun 13 03:22:00 PM PDT 24
Peak memory 275836 kb
Host smart-df031c9d-a971-436f-9171-2a20944500d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362898891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.1362898891
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.2121169493
Short name T499
Test name
Test status
Simulation time 462598500 ps
CPU time 120.94 seconds
Started Jun 13 03:21:13 PM PDT 24
Finished Jun 13 03:23:14 PM PDT 24
Peak memory 282188 kb
Host smart-8736143b-a47f-4106-8d60-0ca90192b96b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121169493 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.2121169493
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.4259618836
Short name T228
Test name
Test status
Simulation time 3762883900 ps
CPU time 129.46 seconds
Started Jun 13 03:21:12 PM PDT 24
Finished Jun 13 03:23:22 PM PDT 24
Peak memory 282356 kb
Host smart-ccdee7e0-e75f-40dc-a0c1-e55dbfdf49ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4259618836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.4259618836
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3131942057
Short name T742
Test name
Test status
Simulation time 1586900000 ps
CPU time 154.17 seconds
Started Jun 13 03:21:14 PM PDT 24
Finished Jun 13 03:23:49 PM PDT 24
Peak memory 282356 kb
Host smart-61c1ce41-730a-4b49-b96c-659d8079f84a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131942057 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3131942057
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.1989705782
Short name T649
Test name
Test status
Simulation time 3992226200 ps
CPU time 590.28 seconds
Started Jun 13 03:21:13 PM PDT 24
Finished Jun 13 03:31:04 PM PDT 24
Peak memory 311192 kb
Host smart-e9b0763f-96f1-48ad-8887-3772d2a8c251
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989705782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.1989705782
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.1521565049
Short name T190
Test name
Test status
Simulation time 12610689100 ps
CPU time 717.21 seconds
Started Jun 13 03:21:20 PM PDT 24
Finished Jun 13 03:33:18 PM PDT 24
Peak memory 338168 kb
Host smart-74c9c439-5817-4c52-b3f3-366d55c94146
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521565049 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.1521565049
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.1019663168
Short name T431
Test name
Test status
Simulation time 45560700 ps
CPU time 31.63 seconds
Started Jun 13 03:21:19 PM PDT 24
Finished Jun 13 03:21:52 PM PDT 24
Peak memory 275796 kb
Host smart-f687f81e-322d-4654-a5e1-74118dfda19b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019663168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.1019663168
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3381931724
Short name T1027
Test name
Test status
Simulation time 39704700 ps
CPU time 30.53 seconds
Started Jun 13 03:21:26 PM PDT 24
Finished Jun 13 03:21:57 PM PDT 24
Peak memory 275372 kb
Host smart-0e0430bc-6653-43d3-865e-7a924e372180
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381931724 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3381931724
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.1737815014
Short name T124
Test name
Test status
Simulation time 8639228600 ps
CPU time 627.21 seconds
Started Jun 13 03:21:11 PM PDT 24
Finished Jun 13 03:31:39 PM PDT 24
Peak memory 313144 kb
Host smart-9bd99a2b-88fa-4e73-871b-c33e39889335
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737815014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.1737815014
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.3142914342
Short name T376
Test name
Test status
Simulation time 1409596700 ps
CPU time 66.1 seconds
Started Jun 13 03:21:26 PM PDT 24
Finished Jun 13 03:22:33 PM PDT 24
Peak memory 264136 kb
Host smart-d84eba9e-dfd1-4761-ac52-ca45cbaeefe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142914342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3142914342
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.815159353
Short name T896
Test name
Test status
Simulation time 23116000 ps
CPU time 123.95 seconds
Started Jun 13 03:21:08 PM PDT 24
Finished Jun 13 03:23:13 PM PDT 24
Peak memory 277760 kb
Host smart-77031e95-8b48-40d9-90a9-6be4eb1e0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815159353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.815159353
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2184258958
Short name T644
Test name
Test status
Simulation time 3139843500 ps
CPU time 256.19 seconds
Started Jun 13 03:21:15 PM PDT 24
Finished Jun 13 03:25:32 PM PDT 24
Peak memory 260424 kb
Host smart-97e93f65-4f3b-4b54-9fca-c44fdb9b195b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184258958 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2184258958
Directory /workspace/9.flash_ctrl_wo/latest
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