Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	280852	1		T1	2		T2	1		T3	2
all_values[1]	280852	1		T1	2		T2	1		T3	2
all_values[2]	280852	1		T1	2		T2	1		T3	2
all_values[3]	280852	1		T1	2		T2	1		T3	2
all_values[4]	280852	1		T1	2		T2	1		T3	2
all_values[5]	280852	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	568001	1		T1	12		T2	6		T3	12
auto[1]	1117111	1		T4	36616		T20	6000		T31	18852

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	821943	1		T1	7		T2	4		T3	7
auto[1]	863169	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	280692	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	160	1		T271	1		T272	2		T324	6
all_values[1]	auto[0]	auto[1]	280690	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	162	1		T324	5		T326	7		T325	5
all_values[2]	auto[0]	auto[0]	1597	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	58	1		T324	2		T326	1		T325	3
all_values[2]	auto[1]	auto[0]	279145	1		T4	9154		T20	1500		T31	4713
all_values[2]	auto[1]	auto[1]	52	1		T272	1		T326	1		T338	1
all_values[3]	auto[0]	auto[0]	1608	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	58	1		T271	1		T272	1		T324	1
all_values[3]	auto[1]	auto[0]	77463	1		T4	241		T20	1500		T31	1571
all_values[3]	auto[1]	auto[1]	201723	1		T4	8913		T31	3142		T32	1751
all_values[4]	auto[0]	auto[0]	1125	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	523	1		T1	1		T3	1		T5	1
all_values[4]	auto[1]	auto[0]	180352	1		T4	7381		T20	1		T31	3142
all_values[4]	auto[1]	auto[1]	98852	1		T4	1773		T20	1499		T31	1571
all_values[5]	auto[0]	auto[0]	1520	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	130	1		T33	1		T34	4		T35	1
all_values[5]	auto[1]	auto[0]	279133	1		T4	9154		T20	1500		T31	4713
all_values[5]	auto[1]	auto[1]	69	1		T271	1		T324	2		T326	2