Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	234415	1		T1	2		T3	278		T4	920
auto[FlashEraseBank]	266027	1		T1	2		T4	853		T19	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	250916	1		T3	10		T4	1773		T19	17
auto[FlashOpProgram]	230420	1		T1	3		T3	256		T19	4
auto[FlashOpErase]	15106	1		T1	1		T3	12		T5	1
auto[FlashOpInvalid]	4000	1		T137	200		T142	200		T122	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	250916	1		T3	10		T4	1773		T19	17
op[FlashOpProgram]	230420	1		T1	3		T3	256		T19	4
op[FlashOpErase]	15106	1		T1	1		T3	12		T5	1
read_erase_read	566	1		T3	1		T27	1		T51	2
read_prog_read	838	1		T19	2		T7	9		T22	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	361867	1		T1	4		T4	1773		T5	1
auto[FlashPartInfo]	135311	1		T3	278		T19	11		T7	552
auto[FlashPartInfo1]	737	1		T7	3		T40	1		T33	4
auto[FlashPartInfo2]	2527	1		T19	1		T7	14		T20	5

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	180776	1		T4	1773		T19	6		T7	940
auto[FlashPartData]	auto[FlashOpProgram]	173542	1		T1	3		T19	3		T7	1576
auto[FlashPartData]	auto[FlashOpErase]	3619	1		T1	1		T5	1		T8	3
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T137	198		T142	198		T122	196
auto[FlashPartInfo]	auto[FlashOpRead]	67908	1		T3	10		T19	10		T7	320
auto[FlashPartInfo]	auto[FlashOpProgram]	55880	1		T3	256		T19	1		T7	232
auto[FlashPartInfo]	auto[FlashOpErase]	11461	1		T3	12		T26	3		T27	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T137	2		T122	2		T389	6
auto[FlashPartInfo1]	auto[FlashOpRead]	557	1		T7	3		T40	1		T33	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T142	1		T122	1		T144	32
auto[FlashPartInfo1]	auto[FlashOpErase]	8	1		T136	1		T142	1		T122	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T142	2		T122	2		T150	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1675	1		T19	1		T7	6		T22	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	832	1		T7	8		T20	5		T121	5
auto[FlashPartInfo2]	auto[FlashOpErase]	18	1		T63	1		T138	1		T139	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	2	1		T390	2		-	-		-	-