Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29580	1		T51	20		T61	20		T74	604
auto[1]	42	1		T207	1		T391	1		T392	6
auto[2]	63	1		T75	4		T227	7		T213	1
auto[3]	236	1		T22	1		T100	1		T209	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7482	1		T51	5		T61	5		T74	151
evic_idx[1]	7496	1		T22	1		T51	5		T61	5
evic_idx[2]	7477	1		T51	5		T61	5		T74	151
evic_idx[3]	7466	1		T51	5		T61	5		T74	151

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29054	1		T74	604		T91	772		T97	372
evic_op[2]	303	1		T22	1		T100	1		T207	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7199	1		T74	151		T91	193		T97	93
evic_idx[0]	evic_op[1]	auto[1]	9	1		T392	2		T393	1		T394	3
evic_idx[0]	evic_op[1]	auto[2]	10	1		T227	2		T395	1		T250	1
evic_idx[0]	evic_op[1]	auto[3]	49	1		T227	1		T138	1		T140	1
evic_idx[0]	evic_op[2]	auto[0]	59	1		T116	4		T54	4		T231	1
evic_idx[0]	evic_op[2]	auto[1]	5	1		T207	1		T391	1		T396	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T397	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T398	1		T251	1		T399	1
evic_idx[1]	evic_op[1]	auto[0]	7203	1		T74	151		T91	193		T97	93
evic_idx[1]	evic_op[1]	auto[1]	7	1		T392	2		T393	1		T394	2
evic_idx[1]	evic_op[1]	auto[2]	8	1		T227	1		T395	1		T250	1
evic_idx[1]	evic_op[1]	auto[3]	57	1		T227	1		T140	1		T400	4
evic_idx[1]	evic_op[2]	auto[0]	59	1		T116	4		T54	4		T222	2
evic_idx[1]	evic_op[2]	auto[1]	2	1		T401	1		T402	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T291	1		T401	1		T397	1
evic_idx[1]	evic_op[2]	auto[3]	15	1		T22	1		T209	1		T210	1
evic_idx[2]	evic_op[1]	auto[0]	7203	1		T74	151		T91	193		T97	93
evic_idx[2]	evic_op[1]	auto[1]	9	1		T392	1		T393	1		T394	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T227	2		T395	1		T250	1
evic_idx[2]	evic_op[1]	auto[3]	43	1		T138	1		T400	2		T395	1
evic_idx[2]	evic_op[2]	auto[0]	60	1		T116	4		T54	4		T284	7
evic_idx[2]	evic_op[2]	auto[1]	2	1		T403	1		T404	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T401	1		T405	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T100	1		T406	1		T407	1
evic_idx[3]	evic_op[1]	auto[0]	7198	1		T74	151		T91	193		T97	93
evic_idx[3]	evic_op[1]	auto[1]	6	1		T392	1		T393	1		T394	2
evic_idx[3]	evic_op[1]	auto[2]	6	1		T227	2		T408	3		T409	1
evic_idx[3]	evic_op[1]	auto[3]	40	1		T138	2		T400	3		T395	1
evic_idx[3]	evic_op[2]	auto[0]	59	1		T116	4		T54	4		T284	7
evic_idx[3]	evic_op[2]	auto[1]	2	1		T410	1		T411	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T213	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	13	1		T36	1		T213	1		T412	1