Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7476	1		T328	929		T329	1545		T330	2705
rd_lvl[2]	36548	1		T204	1476		T328	255		T329	683
rd_lvl[3]	17061	1		T4	1388		T204	603		T329	304
rd_lvl[4]	29867	1		T4	6239		T204	116		T329	205
rd_lvl[5]	15367	1		T4	1061		T204	313		T329	23
rd_lvl[6]	23497	1		T31	2569		T204	370		T329	3
rd_lvl[7]	8052	1		T31	313		T329	1		T331	919
rd_lvl[8]	13938	1		T287	2		T332	45		T333	294
rd_lvl[9]	5711	1		T204	1		T329	1		T334	195
rd_lvl[10]	7701	1		T203	1428		T329	1		T287	1
rd_lvl[11]	3851	1		T32	615		T203	355		T329	68
rd_lvl[12]	9493	1		T32	1136		T204	51		T329	1
rd_lvl[13]	3412	1		T204	51		T335	459		T336	577
rd_lvl[14]	4696	1		T28	321		T329	68		T337	268
rd_lvl[15]	2224	1		T28	152		T29	179		T30	227