Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	280852	1		T1	2		T2	1		T3	2
all_pins[1]	280852	1		T1	2		T2	1		T3	2
all_pins[2]	280852	1		T1	2		T2	1		T3	2
all_pins[3]	280852	1		T1	2		T2	1		T3	2
all_pins[4]	280852	1		T1	2		T2	1		T3	2
all_pins[5]	280852	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1382405	1		T1	12		T2	6		T3	12
values[0x1]	302707	1		T4	10500		T20	1499		T31	4453
transitions[0x0=>0x1]	270671	1		T4	8957		T20	1499		T31	4453
transitions[0x1=>0x0]	270657	1		T4	8957		T20	1499		T31	4453

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280692	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	160	1		T271	1		T272	2		T324	6
all_pins[0]	transitions[0x0=>0x1]	80	1		T271	1		T272	2		T324	1
all_pins[0]	transitions[0x1=>0x0]	82	1		T326	6		T325	1		T338	4
all_pins[1]	values[0x0]	280690	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	162	1		T324	5		T326	7		T325	5
all_pins[1]	transitions[0x0=>0x1]	129	1		T324	5		T326	6		T325	5
all_pins[1]	transitions[0x1=>0x0]	3265	1		T28	71		T29	300		T30	1144
all_pins[2]	values[0x0]	277554	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	3298	1		T28	71		T29	300		T30	1144
all_pins[2]	transitions[0x0=>0x1]	41	1		T338	1		T339	1		T340	2
all_pins[2]	transitions[0x1=>0x0]	189337	1		T4	8688		T31	2882		T32	1751
all_pins[3]	values[0x0]	88258	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	192594	1		T4	8688		T31	2882		T32	1751
all_pins[3]	transitions[0x0=>0x1]	163982	1		T4	7145		T31	2882		T32	1751
all_pins[3]	transitions[0x1=>0x0]	77812	1		T4	269		T20	1499		T31	1571
all_pins[4]	values[0x0]	174428	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	106424	1		T4	1812		T20	1499		T31	1571
all_pins[4]	transitions[0x0=>0x1]	106405	1		T4	1812		T20	1499		T31	1571
all_pins[4]	transitions[0x1=>0x0]	50	1		T271	1		T324	1		T325	1
all_pins[5]	values[0x0]	280783	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	69	1		T271	1		T324	2		T326	2
all_pins[5]	transitions[0x0=>0x1]	34	1		T324	2		T326	1		T325	1
all_pins[5]	transitions[0x1=>0x0]	111	1		T271	1		T272	1		T324	5