Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

---

Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	99	0	99	100.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_interval	99	0	99	100.00	100	1	1	0

Summary for Variable read_interval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	99	0	99	100.00

User Defined Bins for read_interval

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5484135	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
duration[1]	415395	1		T4	1560		T7	9131		T31	1685
duration[2]	1038844	1		T3	26		T4	1812		T19	10
duration[3]	121279	1		T3	11		T4	1066		T7	1194
duration[4]	1435672	1		T2	25		T3	81		T4	8527
duration[5]	66469	1		T3	24		T4	410		T7	967
duration[6]	448011	1		T2	25		T3	50		T4	11143
duration[7]	54261	1		T3	54		T4	459		T7	390
duration[8]	24526	1		T2	25		T3	39		T4	182
duration[9]	31237	1		T3	52		T4	329		T7	174
duration[10]	17838	1		T2	24		T3	63		T4	105
duration[11]	18628	1		T3	72		T4	176		T7	71
duration[12]	17064	1		T3	81		T4	142		T7	119
duration[13]	11726	1		T3	108		T4	104		T7	56
duration[14]	12067	1		T3	97		T4	98		T7	44
duration[15]	9543	1		T3	86		T4	56		T7	31
duration[16]	9243	1		T3	74		T4	52		T7	32
duration[17]	10353	1		T3	73		T4	40		T7	73
duration[18]	7764	1		T3	72		T4	35		T7	27
duration[19]	9728	1		T3	61		T4	17		T7	99
duration[20]	8490	1		T3	57		T4	14		T7	39
duration[21]	8000	1		T3	65		T4	23		T19	2
duration[22]	8500	1		T3	69		T4	15		T7	59
duration[23]	5784	1		T3	53		T4	6		T7	7
duration[24]	6767	1		T3	56		T4	145		T19	1
duration[25]	5407	1		T3	52		T4	6		T7	2
duration[26]	6483	1		T3	52		T4	272		T19	1
duration[27]	3110	1		T3	66		T4	9		T7	41
duration[28]	3332	1		T3	76		T4	6		T7	3
duration[29]	4246	1		T3	56		T4	566		T19	1
duration[30]	4692	1		T3	61		T7	34		T31	9
duration[31]	2013	1		T3	58		T4	4		T7	1
duration[32]	2255	1		T3	53		T4	4		T7	17
duration[33]	4128	1		T3	45		T4	1		T19	1
duration[34]	2710	1		T3	36		T4	2		T19	1
duration[35]	1778	1		T3	19		T4	1		T7	2
duration[36]	1746	1		T3	26		T4	2		T7	32
duration[37]	1761	1		T3	24		T31	5		T27	11
duration[38]	626	1		T3	10		T7	1		T31	2
duration[39]	1788	1		T3	4		T7	36		T31	1
duration[40]	1297	1		T3	4		T27	14		T33	26
duration[41]	3344	1		T3	6		T31	1		T27	9
duration[42]	26930	1		T3	3		T7	1		T31	1
duration[43]	255	1		T3	2		T27	10		T91	2
duration[44]	193	1		T3	1		T27	8		T119	1
duration[45]	197	1		T4	1		T7	1		T31	1
duration[46]	1305	1		T3	1		T7	1		T31	1
duration[47]	180	1		T7	2		T31	1		T27	4
duration[48]	1481	1		T7	1		T31	1		T27	8
duration[49]	220	1		T7	3		T27	7		T97	1
duration[50]	165826	1		T6	4129		T7	11		T32	3995
duration[51]	261854	1		T6	2661		T7	32		T32	9677
duration[52]	20478	1		T6	1008		T7	49		T31	1
duration[53]	213084	1		T6	131		T19	1		T7	18
duration[54]	11523	1		T7	120		T32	69		T203	67
duration[55]	8237	1		T7	173		T32	13		T27	4
duration[56]	1355	1		T7	38		T32	16		T97	3
duration[57]	5682	1		T7	39		T32	21		T27	2
duration[58]	3723	1		T19	1		T7	119		T31	1
duration[59]	1523	1		T7	69		T31	2		T32	6
duration[60]	2569	1		T7	52		T32	9		T100	1
duration[61]	2090	1		T7	43		T32	8		T203	5
duration[62]	1271	1		T7	44		T32	8		T97	1
duration[63]	2640	1		T7	35		T32	5		T91	1
duration[64]	2793	1		T7	31		T22	1		T32	7
duration[65]	1335	1		T6	1		T7	21		T32	1
duration[66]	3875	1		T7	15		T32	1		T203	2
duration[67]	1320	1		T7	11		T97	3		T203	4
duration[68]	3350	1		T7	6		T32	4		T97	2
duration[69]	921	1		T7	4		T33	1		T97	1
duration[70]	2861	1		T7	11		T32	1		T203	1
duration[71]	608	1		T7	5		T203	1		T57	6
duration[72]	3396	1		T7	11		T32	165		T97	1
duration[73]	436	1		T7	3		T26	1		T97	1
duration[74]	3043	1		T7	2		T32	754		T100	1
duration[75]	299	1		T7	5		T32	3		T97	3
duration[76]	2786	1		T7	3		T32	1		T203	673
duration[77]	236	1		T7	4		T32	5		T97	2
duration[78]	2431	1		T7	2		T32	7		T97	2
duration[79]	203	1		T7	2		T32	7		T97	1
duration[80]	2457	1		T7	2		T97	1		T203	6
duration[81]	205	1		T7	1		T32	6		T23	1
duration[82]	168	1		T32	4		T97	1		T203	3
duration[83]	133	1		T32	4		T97	1		T203	7
duration[84]	147	1		T32	4		T97	2		T203	3
duration[85]	123	1		T7	1		T32	2		T97	1
duration[86]	100	1		T32	4		T97	2		T203	2
duration[87]	120	1		T7	1		T32	2		T134	1
duration[88]	93	1		T32	5		T97	1		T203	5
duration[89]	95	1		T32	4		T91	1		T97	2
duration[90]	102	1		T97	1		T203	1		T134	2
duration[91]	74	1		T32	2		T97	1		T203	2
duration[92]	76	1		T32	4		T203	2		T41	1
duration[93]	124	1		T40	1		T32	2		T33	1
duration[94]	148	1		T19	1		T22	1		T23	1
duration[95]	77	1		T32	5		T97	1		T57	1
duration[96]	83	1		T7	1		T32	2		T97	2
duration[97]	63	1		T32	2		T203	3		T90	1
duration[98]	79	1		T32	2		T97	2		T203	2
duration[99]	72	1		T32	2		T91	1		T97	2