Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T271	4		T272	4		T324	7
all_values[1]	278	1		T271	4		T272	4		T324	7
all_values[2]	278	1		T271	4		T272	4		T324	7
all_values[3]	278	1		T271	4		T272	4		T324	7
all_values[4]	278	1		T271	4		T272	4		T324	7
all_values[5]	278	1		T271	4		T272	4		T324	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	924	1		T271	16		T272	15		T324	26
auto[1]	744	1		T271	8		T272	9		T324	16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	544	1		T271	13		T272	10		T324	12
auto[1]	1124	1		T271	11		T272	14		T324	30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	989	1		T271	16		T272	16		T324	23
auto[1]	679	1		T271	8		T272	8		T324	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	94	1		T271	2		T272	2		T324	2
all_values[0]	auto[0]	auto[1]	auto[1]	74	1		T272	1		T324	2		T325	3
all_values[0]	auto[1]	auto[0]	auto[1]	62	1		T271	1		T272	1		T324	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T271	1		T324	2		T326	2
all_values[1]	auto[0]	auto[0]	auto[1]	71	1		T271	1		T272	3		T326	1
all_values[1]	auto[0]	auto[1]	auto[1]	84	1		T324	2		T326	4		T325	2
all_values[1]	auto[1]	auto[0]	auto[1]	81	1		T271	3		T272	1		T324	4
all_values[1]	auto[1]	auto[1]	auto[1]	42	1		T324	1		T326	2		T325	1
all_values[2]	auto[0]	auto[0]	auto[0]	87	1		T271	3		T272	2		T324	4
all_values[2]	auto[0]	auto[1]	auto[0]	81	1		T271	1		T272	1		T324	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T272	1		T324	1		T326	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T324	1		T326	1		T325	1
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T271	2		T272	2		T324	4
all_values[3]	auto[0]	auto[1]	auto[0]	76	1		T271	1		T324	1		T326	2
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T271	1		T272	1		T324	2
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T272	1		T326	2		T325	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T271	1		T326	2		T325	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T324	1		T325	1		T327	1
all_values[4]	auto[0]	auto[1]	auto[0]	44	1		T271	2		T272	2		T326	1
all_values[4]	auto[0]	auto[1]	auto[1]	37	1		T324	2		T326	1		T325	1
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T271	1		T324	2		T326	1
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T272	2		T324	2		T326	2
all_values[5]	auto[0]	auto[0]	auto[0]	67	1		T272	2		T324	2		T325	2
all_values[5]	auto[0]	auto[0]	auto[1]	29	1		T324	1		T326	1		T327	1
all_values[5]	auto[0]	auto[1]	auto[0]	50	1		T271	3		T272	1		T326	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T324	1		T326	2		T325	2
all_values[5]	auto[1]	auto[0]	auto[1]	66	1		T271	1		T324	2		T326	1
all_values[5]	auto[1]	auto[1]	auto[1]	41	1		T272	1		T324	1		T326	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal