Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	215667	1		T1	2		T2	694		T3	2
all_values[1]	215667	1		T1	2		T2	694		T3	2
all_values[2]	215667	1		T1	2		T2	694		T3	2
all_values[3]	215667	1		T1	2		T2	694		T3	2
all_values[4]	215667	1		T1	2		T2	694		T3	2
all_values[5]	215667	1		T1	2		T2	694		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	437724	1		T1	12		T2	1392		T3	12
auto[1]	856278	1		T2	2772		T6	640		T28	5848

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	631274	1		T1	7		T2	2032		T3	7
auto[1]	662728	1		T1	5		T2	2132		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	215518	1		T1	2		T2	694		T3	2
all_values[0]	auto[1]	auto[1]	149	1		T273	5		T274	1		T275	5
all_values[1]	auto[0]	auto[1]	215556	1		T1	2		T2	694		T3	2
all_values[1]	auto[1]	auto[1]	111	1		T273	7		T274	2		T275	2
all_values[2]	auto[0]	auto[0]	1611	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	63	1		T273	2		T274	1		T275	2
all_values[2]	auto[1]	auto[0]	213945	1		T2	693		T6	160		T28	1462
all_values[2]	auto[1]	auto[1]	48	1		T273	1		T274	1		T342	1
all_values[3]	auto[0]	auto[0]	1616	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	40	1		T273	2		T274	1		T275	1
all_values[3]	auto[1]	auto[0]	81462	1		T2	34		T6	80		T28	1462
all_values[3]	auto[1]	auto[1]	132549	1		T2	659		T6	80		T34	216
all_values[4]	auto[0]	auto[0]	1143	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	508	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	116025	1		T2	608		T6	80		T28	1
all_values[4]	auto[1]	auto[1]	97991	1		T2	85		T6	80		T28	1461
all_values[5]	auto[0]	auto[0]	1538	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	131	1		T5	1		T35	1		T36	1
all_values[5]	auto[1]	auto[0]	213934	1		T2	693		T6	160		T28	1462
all_values[5]	auto[1]	auto[1]	64	1		T273	2		T274	1		T344	2