Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240791	1		T1	100		T2	41		T3	947
auto[FlashEraseBank]	259667	1		T1	949		T2	44		T3	638

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	247381	1		T1	349		T2	85		T4	14
auto[FlashOpProgram]	232558	1		T1	647		T3	1585		T4	256
auto[FlashOpErase]	16519	1		T1	53		T4	8		T17	266
auto[FlashOpInvalid]	4000	1		T141	200		T142	200		T306	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	247381	1		T1	349		T2	85		T4	14
op[FlashOpProgram]	232558	1		T1	647		T3	1585		T4	256
op[FlashOpErase]	16519	1		T1	53		T4	8		T17	266
read_erase_read	594	1		T1	4		T4	2		T37	4
read_prog_read	812	1		T1	3		T21	1		T25	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	357878	1		T1	94		T3	1316		T5	809
auto[FlashPartInfo]	138703	1		T1	955		T3	261		T4	278
auto[FlashPartInfo1]	883	1		T2	42		T5	2		T12	1
auto[FlashPartInfo2]	2994	1		T2	43		T3	8		T5	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	175220	1		T1	26		T5	809		T21	3
auto[FlashPartData]	auto[FlashOpProgram]	175157	1		T1	36		T3	1316		T20	2
auto[FlashPartData]	auto[FlashOpErase]	3571	1		T1	32		T20	2		T37	7
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T141	194		T142	198		T306	198
auto[FlashPartInfo]	auto[FlashOpRead]	69374	1		T1	323		T4	14		T5	294
auto[FlashPartInfo]	auto[FlashOpProgram]	56355	1		T1	611		T3	261		T4	256
auto[FlashPartInfo]	auto[FlashOpErase]	12914	1		T1	21		T4	8		T17	266
auto[FlashPartInfo]	auto[FlashOpInvalid]	60	1		T141	6		T142	2		T306	2
auto[FlashPartInfo1]	auto[FlashOpRead]	720	1		T2	42		T5	2		T35	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	160	1		T145	32		T148	32		T123	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T12	1		T151	1		T129	1
auto[FlashPartInfo2]	auto[FlashOpRead]	2067	1		T2	43		T5	6		T6	80
auto[FlashPartInfo2]	auto[FlashOpProgram]	886	1		T3	8		T59	4		T35	2
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T132	1		T134	1		T40	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T357	2		T358	2		T359	2