Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32460	1		T1	8		T17	500		T18	112
auto[1]	18	1		T21	1		T360	1		T361	1
auto[2]	77	1		T362	1		T211	1		T363	1
auto[3]	239	1		T25	1		T27	10		T62	10

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8201	1		T1	2		T17	125		T18	28
evic_idx[1]	8184	1		T1	2		T17	125		T18	28
evic_idx[2]	8199	1		T1	2		T17	125		T18	28
evic_idx[3]	8210	1		T1	2		T17	125		T18	28

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31937	1		T17	500		T18	112		T84	736
evic_op[2]	320	1		T21	1		T25	1		T22	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7924	1		T17	125		T18	28		T84	184
evic_idx[0]	evic_op[1]	auto[1]	2	1		T364	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	8	1		T365	1		T334	5		T366	2
evic_idx[0]	evic_op[1]	auto[3]	51	1		T27	2		T62	3		T292	3
evic_idx[0]	evic_op[2]	auto[0]	66	1		T224	1		T60	4		T367	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T361	1		T368	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T369	1		T370	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T371	1		T211	1		T372	1
evic_idx[1]	evic_op[1]	auto[0]	7922	1		T17	125		T18	28		T84	184
evic_idx[1]	evic_op[1]	auto[1]	3	1		T364	2		T373	1		-	-
evic_idx[1]	evic_op[1]	auto[2]	8	1		T365	1		T334	4		T374	1
evic_idx[1]	evic_op[1]	auto[3]	43	1		T27	3		T62	1		T292	1
evic_idx[1]	evic_op[2]	auto[0]	65	1		T22	1		T45	1		T60	4
evic_idx[1]	evic_op[2]	auto[2]	3	1		T211	1		T363	1		T375	1
evic_idx[1]	evic_op[2]	auto[3]	6	1		T376	1		T293	1		T377	1
evic_idx[2]	evic_op[1]	auto[0]	7920	1		T17	125		T18	28		T84	184
evic_idx[2]	evic_op[1]	auto[1]	3	1		T364	2		T373	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	10	1		T290	1		T364	1		T365	1
evic_idx[2]	evic_op[1]	auto[3]	51	1		T27	2		T62	3		T292	2
evic_idx[2]	evic_op[2]	auto[0]	64	1		T60	4		T367	4		T147	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T21	1		T360	1		T363	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T362	1		T375	1		T378	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T256	1		T379	1		T380	1
evic_idx[3]	evic_op[1]	auto[0]	7926	1		T17	125		T18	28		T84	184
evic_idx[3]	evic_op[1]	auto[1]	2	1		T364	1		T373	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	12	1		T290	1		T364	1		T365	1
evic_idx[3]	evic_op[1]	auto[3]	52	1		T27	3		T62	3		T292	3
evic_idx[3]	evic_op[2]	auto[0]	64	1		T60	4		T231	1		T367	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T219	1		T369	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T220	1		T381	1		T378	1
evic_idx[3]	evic_op[2]	auto[3]	15	1		T25	1		T26	1		T382	1