Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	2754	1		T350	2754		-	-		-	-
rd_lvl[2]	2987	1		T2	578		T350	2409		-	-
rd_lvl[3]	7710	1		T2	34		T351	932		T352	290
rd_lvl[4]	20570	1		T2	3		T351	1052		T353	2096
rd_lvl[5]	11672	1		T2	2		T34	173		T58	754
rd_lvl[6]	9490	1		T2	1		T34	42		T58	2715
rd_lvl[7]	7762	1		T34	1		T58	1159		T208	1026
rd_lvl[8]	18962	1		T208	910		T209	1639		T203	1
rd_lvl[9]	6768	1		T208	184		T209	1487		T203	94
rd_lvl[10]	8250	1		T2	1		T208	37		T203	96
rd_lvl[11]	3242	1		T297	466		T354	627		T355	69
rd_lvl[12]	8513	1		T2	4		T6	69		T225	1175
rd_lvl[13]	2222	1		T2	2		T6	10		T225	384
rd_lvl[14]	9782	1		T32	1427		T255	1827		T295	202
rd_lvl[15]	4005	1		T6	1		T356	86		T295	232