Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	215667	1		T1	2		T2	694		T3	2
all_pins[1]	215667	1		T1	2		T2	694		T3	2
all_pins[2]	215667	1		T1	2		T2	694		T3	2
all_pins[3]	215667	1		T1	2		T2	694		T3	2
all_pins[4]	215667	1		T1	2		T2	694		T3	2
all_pins[5]	215667	1		T1	2		T2	694		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1058869	1		T1	12		T2	3454		T3	12
values[0x1]	235133	1		T2	710		T6	160		T28	1461
transitions[0x0=>0x1]	209173	1		T2	659		T6	160		T28	1461
transitions[0x1=>0x0]	209155	1		T2	659		T6	160		T28	1461

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	215518	1		T1	2		T2	694		T3	2
all_pins[0]	values[0x1]	149	1		T273	5		T274	1		T275	5
all_pins[0]	transitions[0x0=>0x1]	99	1		T275	3		T342	1		T344	4
all_pins[0]	transitions[0x1=>0x0]	61	1		T273	2		T274	1		T347	1
all_pins[1]	values[0x0]	215556	1		T1	2		T2	694		T3	2
all_pins[1]	values[0x1]	111	1		T273	7		T274	2		T275	2
all_pins[1]	transitions[0x0=>0x1]	91	1		T273	6		T274	1		T275	2
all_pins[1]	transitions[0x1=>0x0]	2727	1		T295	110		T383	561		T384	236
all_pins[2]	values[0x0]	212920	1		T1	2		T2	694		T3	2
all_pins[2]	values[0x1]	2747	1		T295	110		T383	561		T384	236
all_pins[2]	transitions[0x0=>0x1]	35	1		T273	1		T274	1		T342	1
all_pins[2]	transitions[0x1=>0x0]	124783	1		T2	625		T6	80		T34	216
all_pins[3]	values[0x0]	88172	1		T1	2		T2	69		T3	2
all_pins[3]	values[0x1]	127495	1		T2	625		T6	80		T34	216
all_pins[3]	transitions[0x0=>0x1]	104367	1		T2	574		T6	80		T34	205
all_pins[3]	transitions[0x1=>0x0]	81439	1		T2	34		T6	80		T28	1461
all_pins[4]	values[0x0]	111100	1		T1	2		T2	609		T3	2
all_pins[4]	values[0x1]	104567	1		T2	85		T6	80		T28	1461
all_pins[4]	transitions[0x0=>0x1]	104551	1		T2	85		T6	80		T28	1461
all_pins[4]	transitions[0x1=>0x0]	48	1		T273	2		T274	1		T344	2
all_pins[5]	values[0x0]	215603	1		T1	2		T2	694		T3	2
all_pins[5]	values[0x1]	64	1		T273	2		T274	1		T344	2
all_pins[5]	transitions[0x0=>0x1]	30	1		T273	1		T274	1		T344	1
all_pins[5]	transitions[0x1=>0x0]	97	1		T273	3		T274	1		T275	5