Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1		T273	7		T274	4		T275	7
all_values[1]	263	1		T273	7		T274	4		T275	7
all_values[2]	263	1		T273	7		T274	4		T275	7
all_values[3]	263	1		T273	7		T274	4		T275	7
all_values[4]	263	1		T273	7		T274	4		T275	7
all_values[5]	263	1		T273	7		T274	4		T275	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	877	1		T273	23		T274	10		T275	25
auto[1]	701	1		T273	19		T274	14		T275	17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	552	1		T273	17		T274	8		T275	13
auto[1]	1026	1		T273	25		T274	16		T275	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	963	1		T273	28		T274	17		T275	24
auto[1]	615	1		T273	14		T274	7		T275	18

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	92	1		T273	1		T274	3		T275	2
all_values[0]	auto[0]	auto[1]	auto[1]	74	1		T273	3		T274	1		T275	2
all_values[0]	auto[1]	auto[0]	auto[1]	51	1		T273	1		T275	1		T342	1
all_values[0]	auto[1]	auto[1]	auto[1]	46	1		T273	2		T275	2		T342	1
all_values[1]	auto[0]	auto[0]	auto[1]	102	1		T273	1		T274	1		T275	3
all_values[1]	auto[0]	auto[1]	auto[1]	52	1		T273	5		T274	2		T275	1
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T274	1		T275	2		T342	2
all_values[1]	auto[1]	auto[1]	auto[1]	38	1		T273	1		T275	1		T343	1
all_values[2]	auto[0]	auto[0]	auto[0]	84	1		T273	4		T275	4		T342	1
all_values[2]	auto[0]	auto[1]	auto[0]	68	1		T274	2		T275	1		T342	2
all_values[2]	auto[1]	auto[0]	auto[1]	69	1		T273	2		T274	1		T275	2
all_values[2]	auto[1]	auto[1]	auto[1]	42	1		T273	1		T274	1		T342	1
all_values[3]	auto[0]	auto[0]	auto[0]	79	1		T273	1		T275	1		T344	1
all_values[3]	auto[0]	auto[1]	auto[0]	87	1		T273	4		T274	2		T275	2
all_values[3]	auto[1]	auto[0]	auto[1]	51	1		T273	2		T274	1		T275	1
all_values[3]	auto[1]	auto[1]	auto[1]	46	1		T274	1		T275	3		T344	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T273	4		T275	2		T342	1
all_values[4]	auto[0]	auto[0]	auto[1]	18	1		T344	1		T345	1		T346	1
all_values[4]	auto[0]	auto[1]	auto[0]	58	1		T273	2		T274	4		T275	1
all_values[4]	auto[0]	auto[1]	auto[1]	23	1		T275	1		T347	1		T345	1
all_values[4]	auto[1]	auto[0]	auto[1]	51	1		T273	1		T342	1		T344	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T275	3		T342	1		T344	1
all_values[5]	auto[0]	auto[0]	auto[0]	68	1		T273	2		T275	2		T342	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T274	1		T275	2		T347	1
all_values[5]	auto[0]	auto[1]	auto[0]	50	1		T342	2		T348	2		T349	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1		T273	1		T274	1		T344	1
all_values[5]	auto[1]	auto[0]	auto[1]	56	1		T273	4		T274	2		T275	3
all_values[5]	auto[1]	auto[1]	auto[1]	39	1		T342	1		T345	1		T348	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal