| T1077 |
/workspace/coverage/default/52.flash_ctrl_connect.1994464563 |
|
|
Jun 22 06:56:43 PM PDT 24 |
Jun 22 06:57:00 PM PDT 24 |
16578400 ps |
| T1078 |
/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.4072210211 |
|
|
Jun 22 06:53:38 PM PDT 24 |
Jun 22 06:53:56 PM PDT 24 |
26348400 ps |
| T1079 |
/workspace/coverage/default/2.flash_ctrl_rand_ops.2610345327 |
|
|
Jun 22 06:43:20 PM PDT 24 |
Jun 22 06:44:18 PM PDT 24 |
278516200 ps |
| T1080 |
/workspace/coverage/default/23.flash_ctrl_disable.216520570 |
|
|
Jun 22 06:54:04 PM PDT 24 |
Jun 22 06:54:28 PM PDT 24 |
35383700 ps |
| T1081 |
/workspace/coverage/default/6.flash_ctrl_fetch_code.2156867716 |
|
|
Jun 22 06:47:07 PM PDT 24 |
Jun 22 06:47:31 PM PDT 24 |
513271700 ps |
| T434 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.3506968921 |
|
|
Jun 22 06:42:45 PM PDT 24 |
Jun 22 06:44:08 PM PDT 24 |
13647755200 ps |
| T1082 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.2348866801 |
|
|
Jun 22 06:50:57 PM PDT 24 |
Jun 22 06:56:05 PM PDT 24 |
79263931500 ps |
| T1083 |
/workspace/coverage/default/7.flash_ctrl_error_mp.4207731748 |
|
|
Jun 22 06:47:36 PM PDT 24 |
Jun 22 07:24:54 PM PDT 24 |
8604675900 ps |
| T96 |
/workspace/coverage/default/2.flash_ctrl_wr_intg.2058509926 |
|
|
Jun 22 06:44:10 PM PDT 24 |
Jun 22 06:44:26 PM PDT 24 |
95583900 ps |
| T329 |
/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3461917197 |
|
|
Jun 22 06:53:37 PM PDT 24 |
Jun 22 06:55:34 PM PDT 24 |
9516052100 ps |
| T1084 |
/workspace/coverage/default/74.flash_ctrl_otp_reset.2859235320 |
|
|
Jun 22 06:57:03 PM PDT 24 |
Jun 22 06:59:15 PM PDT 24 |
150023500 ps |
| T1085 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3748340512 |
|
|
Jun 22 06:55:52 PM PDT 24 |
Jun 22 06:58:04 PM PDT 24 |
6776494800 ps |
| T1086 |
/workspace/coverage/default/18.flash_ctrl_rw.3044281560 |
|
|
Jun 22 06:53:14 PM PDT 24 |
Jun 22 07:04:47 PM PDT 24 |
4173983100 ps |
| T1087 |
/workspace/coverage/default/36.flash_ctrl_disable.4273141372 |
|
|
Jun 22 06:55:42 PM PDT 24 |
Jun 22 06:56:05 PM PDT 24 |
15619900 ps |
| T1088 |
/workspace/coverage/default/8.flash_ctrl_prog_reset.3324636913 |
|
|
Jun 22 06:48:15 PM PDT 24 |
Jun 22 06:50:40 PM PDT 24 |
3496107600 ps |
| T1089 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4259110354 |
|
|
Jun 22 06:52:23 PM PDT 24 |
Jun 22 06:54:17 PM PDT 24 |
9135185300 ps |
| T1090 |
/workspace/coverage/default/10.flash_ctrl_ro.1707720386 |
|
|
Jun 22 06:49:11 PM PDT 24 |
Jun 22 06:51:46 PM PDT 24 |
846383700 ps |
| T1091 |
/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.987767647 |
|
|
Jun 22 06:50:22 PM PDT 24 |
Jun 22 06:52:15 PM PDT 24 |
15206800 ps |
| T1092 |
/workspace/coverage/default/49.flash_ctrl_disable.3785945041 |
|
|
Jun 22 06:56:43 PM PDT 24 |
Jun 22 06:57:06 PM PDT 24 |
50582400 ps |
| T1093 |
/workspace/coverage/default/6.flash_ctrl_intr_wr.1171383483 |
|
|
Jun 22 06:47:13 PM PDT 24 |
Jun 22 06:48:25 PM PDT 24 |
15475847300 ps |
| T1094 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.4127721134 |
|
|
Jun 22 06:52:22 PM PDT 24 |
Jun 22 07:06:39 PM PDT 24 |
40118060500 ps |
| T1095 |
/workspace/coverage/default/74.flash_ctrl_connect.2997988334 |
|
|
Jun 22 06:57:05 PM PDT 24 |
Jun 22 06:57:22 PM PDT 24 |
46996200 ps |
| T1096 |
/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4089171499 |
|
|
Jun 22 06:52:51 PM PDT 24 |
Jun 22 06:54:34 PM PDT 24 |
10020318600 ps |
| T1097 |
/workspace/coverage/default/15.flash_ctrl_ro.1907511940 |
|
|
Jun 22 06:51:35 PM PDT 24 |
Jun 22 06:54:55 PM PDT 24 |
550105200 ps |
| T1098 |
/workspace/coverage/default/13.flash_ctrl_wo.3947085103 |
|
|
Jun 22 06:50:42 PM PDT 24 |
Jun 22 06:55:06 PM PDT 24 |
1925849300 ps |
| T1099 |
/workspace/coverage/default/7.flash_ctrl_otp_reset.1950228811 |
|
|
Jun 22 06:47:30 PM PDT 24 |
Jun 22 06:49:40 PM PDT 24 |
147213900 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_prog_reset.794168661 |
|
|
Jun 22 06:44:02 PM PDT 24 |
Jun 22 06:44:16 PM PDT 24 |
39879700 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_intr_wr.762065354 |
|
|
Jun 22 06:41:04 PM PDT 24 |
Jun 22 06:42:23 PM PDT 24 |
9606025400 ps |
| T1102 |
/workspace/coverage/default/43.flash_ctrl_alert_test.2256299440 |
|
|
Jun 22 06:56:21 PM PDT 24 |
Jun 22 06:56:35 PM PDT 24 |
37263300 ps |
| T1103 |
/workspace/coverage/default/73.flash_ctrl_connect.156213347 |
|
|
Jun 22 06:57:04 PM PDT 24 |
Jun 22 06:57:20 PM PDT 24 |
107391100 ps |
| T1104 |
/workspace/coverage/default/68.flash_ctrl_connect.4064794288 |
|
|
Jun 22 06:57:06 PM PDT 24 |
Jun 22 06:57:23 PM PDT 24 |
29265500 ps |
| T1105 |
/workspace/coverage/default/7.flash_ctrl_ro.650661547 |
|
|
Jun 22 06:47:39 PM PDT 24 |
Jun 22 06:49:30 PM PDT 24 |
913382400 ps |
| T1106 |
/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2924385007 |
|
|
Jun 22 06:49:34 PM PDT 24 |
Jun 22 06:54:49 PM PDT 24 |
34747386000 ps |
| T1107 |
/workspace/coverage/default/44.flash_ctrl_alert_test.722088788 |
|
|
Jun 22 06:56:31 PM PDT 24 |
Jun 22 06:56:46 PM PDT 24 |
168640100 ps |
| T1108 |
/workspace/coverage/default/22.flash_ctrl_intr_rd.472806149 |
|
|
Jun 22 06:53:52 PM PDT 24 |
Jun 22 06:56:29 PM PDT 24 |
729314300 ps |
| T1109 |
/workspace/coverage/default/12.flash_ctrl_rw.1917135267 |
|
|
Jun 22 06:50:13 PM PDT 24 |
Jun 22 07:01:54 PM PDT 24 |
3808522400 ps |
| T1110 |
/workspace/coverage/default/16.flash_ctrl_phy_arb.694775756 |
|
|
Jun 22 06:51:47 PM PDT 24 |
Jun 22 06:55:20 PM PDT 24 |
36947900 ps |
| T1111 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.1491280600 |
|
|
Jun 22 06:56:06 PM PDT 24 |
Jun 22 06:57:18 PM PDT 24 |
7573225300 ps |
| T1112 |
/workspace/coverage/default/17.flash_ctrl_intr_rd.2308663032 |
|
|
Jun 22 06:52:38 PM PDT 24 |
Jun 22 06:57:03 PM PDT 24 |
7143029200 ps |
| T1113 |
/workspace/coverage/default/3.flash_ctrl_serr_address.1996037459 |
|
|
Jun 22 06:44:45 PM PDT 24 |
Jun 22 06:46:20 PM PDT 24 |
813481800 ps |
| T101 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3235379757 |
|
|
Jun 22 04:40:54 PM PDT 24 |
Jun 22 04:41:11 PM PDT 24 |
136765000 ps |
| T273 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2384356943 |
|
|
Jun 22 04:41:04 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
16487900 ps |
| T274 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4184263232 |
|
|
Jun 22 04:41:05 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
25688900 ps |
| T275 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3147536731 |
|
|
Jun 22 04:40:42 PM PDT 24 |
Jun 22 04:40:56 PM PDT 24 |
30677100 ps |
| T1114 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1651138744 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:02 PM PDT 24 |
22622800 ps |
| T64 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.110752742 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:53:33 PM PDT 24 |
668179900 ps |
| T1115 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3374044484 |
|
|
Jun 22 04:40:24 PM PDT 24 |
Jun 22 04:40:40 PM PDT 24 |
15494400 ps |
| T342 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.469000812 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:10 PM PDT 24 |
51048100 ps |
| T245 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3875981162 |
|
|
Jun 22 04:40:49 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
54295900 ps |
| T344 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1893543849 |
|
|
Jun 22 04:41:13 PM PDT 24 |
Jun 22 04:41:27 PM PDT 24 |
26622600 ps |
| T347 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2349751696 |
|
|
Jun 22 04:40:24 PM PDT 24 |
Jun 22 04:40:41 PM PDT 24 |
67506500 ps |
| T65 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3825583961 |
|
|
Jun 22 04:40:59 PM PDT 24 |
Jun 22 04:41:18 PM PDT 24 |
85445400 ps |
| T345 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1259904204 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
32093700 ps |
| T66 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.17736625 |
|
|
Jun 22 04:40:40 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
33722700 ps |
| T102 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3249274786 |
|
|
Jun 22 04:40:47 PM PDT 24 |
Jun 22 04:47:16 PM PDT 24 |
1553736600 ps |
| T1116 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2106986734 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:02 PM PDT 24 |
13079000 ps |
| T348 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1431364456 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:02 PM PDT 24 |
22531900 ps |
| T103 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2938942424 |
|
|
Jun 22 04:40:23 PM PDT 24 |
Jun 22 04:53:14 PM PDT 24 |
3746416600 ps |
| T1117 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1292115692 |
|
|
Jun 22 04:40:47 PM PDT 24 |
Jun 22 04:41:01 PM PDT 24 |
21076200 ps |
| T341 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4007721890 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
2247793700 ps |
| T349 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.513462920 |
|
|
Jun 22 04:41:11 PM PDT 24 |
Jun 22 04:41:25 PM PDT 24 |
13856700 ps |
| T260 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1374487849 |
|
|
Jun 22 04:41:01 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
76452900 ps |
| T1118 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1737503525 |
|
|
Jun 22 04:40:58 PM PDT 24 |
Jun 22 04:41:15 PM PDT 24 |
10994100 ps |
| T261 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.886965228 |
|
|
Jun 22 04:40:59 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
46509300 ps |
| T1119 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.426052691 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
51340100 ps |
| T229 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1186877661 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:56:00 PM PDT 24 |
875993100 ps |
| T227 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2229875087 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
103833300 ps |
| T346 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2061273012 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:40:58 PM PDT 24 |
16793900 ps |
| T228 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.439155884 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
38024400 ps |
| T262 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1410728140 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
97320800 ps |
| T1120 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.853874543 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
28665800 ps |
| T343 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1145326042 |
|
|
Jun 22 04:41:10 PM PDT 24 |
Jun 22 04:41:24 PM PDT 24 |
19304500 ps |
| T1121 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1847234285 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:20 PM PDT 24 |
24583700 ps |
| T1122 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2748968492 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
18275800 ps |
| T237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.309238086 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
103190500 ps |
| T1123 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.848705234 |
|
|
Jun 22 04:41:01 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
49025000 ps |
| T1124 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2771099078 |
|
|
Jun 22 04:41:04 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
29143400 ps |
| T311 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2702252758 |
|
|
Jun 22 04:40:27 PM PDT 24 |
Jun 22 04:41:44 PM PDT 24 |
9181718700 ps |
| T1125 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1382251495 |
|
|
Jun 22 04:40:58 PM PDT 24 |
Jun 22 04:41:15 PM PDT 24 |
18649500 ps |
| T238 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2882889919 |
|
|
Jun 22 04:40:49 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
27483500 ps |
| T1126 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3904050712 |
|
|
Jun 22 04:41:05 PM PDT 24 |
Jun 22 04:41:20 PM PDT 24 |
18166000 ps |
| T239 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3858748485 |
|
|
Jun 22 04:40:57 PM PDT 24 |
Jun 22 04:41:15 PM PDT 24 |
31096700 ps |
| T1127 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3294639436 |
|
|
Jun 22 04:40:42 PM PDT 24 |
Jun 22 04:40:56 PM PDT 24 |
16534800 ps |
| T263 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.841113091 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
306551200 ps |
| T1128 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2801664275 |
|
|
Jun 22 04:40:41 PM PDT 24 |
Jun 22 04:41:28 PM PDT 24 |
593592400 ps |
| T1129 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4103000321 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
131761600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.796316025 |
|
|
Jun 22 04:41:15 PM PDT 24 |
Jun 22 04:41:30 PM PDT 24 |
27133300 ps |
| T1131 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2803117584 |
|
|
Jun 22 04:40:55 PM PDT 24 |
Jun 22 04:41:09 PM PDT 24 |
29614600 ps |
| T1132 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2278021490 |
|
|
Jun 22 04:41:13 PM PDT 24 |
Jun 22 04:41:28 PM PDT 24 |
80222900 ps |
| T1133 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3478417135 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:41:01 PM PDT 24 |
98763000 ps |
| T312 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1870108634 |
|
|
Jun 22 04:40:55 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
430373500 ps |
| T1134 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.130775407 |
|
|
Jun 22 04:41:09 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
48868500 ps |
| T1135 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3109416671 |
|
|
Jun 22 04:40:47 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
45372400 ps |
| T240 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3197229643 |
|
|
Jun 22 04:40:52 PM PDT 24 |
Jun 22 04:48:41 PM PDT 24 |
367030900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3266464817 |
|
|
Jun 22 04:40:50 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
25379000 ps |
| T313 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4116580787 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
122125700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3958732355 |
|
|
Jun 22 04:40:27 PM PDT 24 |
Jun 22 04:40:45 PM PDT 24 |
14604800 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2563807929 |
|
|
Jun 22 04:40:36 PM PDT 24 |
Jun 22 04:40:51 PM PDT 24 |
29713500 ps |
| T241 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.520934499 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
75040900 ps |
| T1138 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3375719880 |
|
|
Jun 22 04:41:07 PM PDT 24 |
Jun 22 04:41:22 PM PDT 24 |
43609100 ps |
| T1139 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2408696506 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
254748900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3315494932 |
|
|
Jun 22 04:40:25 PM PDT 24 |
Jun 22 04:41:08 PM PDT 24 |
110752300 ps |
| T314 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2533463097 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:06 PM PDT 24 |
151601300 ps |
| T1141 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1997342827 |
|
|
Jun 22 04:40:22 PM PDT 24 |
Jun 22 04:40:37 PM PDT 24 |
47933800 ps |
| T315 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2405102460 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
202067000 ps |
| T1142 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.700599435 |
|
|
Jun 22 04:40:28 PM PDT 24 |
Jun 22 04:40:48 PM PDT 24 |
17892200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3414903149 |
|
|
Jun 22 04:40:24 PM PDT 24 |
Jun 22 04:40:43 PM PDT 24 |
16445400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1800220606 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
22338900 ps |
| T242 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4281438749 |
|
|
Jun 22 04:41:01 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
44447800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2997663346 |
|
|
Jun 22 04:41:13 PM PDT 24 |
Jun 22 04:41:27 PM PDT 24 |
29611100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.993700739 |
|
|
Jun 22 04:40:25 PM PDT 24 |
Jun 22 04:40:47 PM PDT 24 |
57060700 ps |
| T284 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1130110108 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:55:55 PM PDT 24 |
2633882600 ps |
| T1147 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1365845308 |
|
|
Jun 22 04:40:54 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
28044800 ps |
| T243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.364315671 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:11 PM PDT 24 |
54665100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2847264855 |
|
|
Jun 22 04:40:27 PM PDT 24 |
Jun 22 04:40:45 PM PDT 24 |
15399300 ps |
| T1149 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3520492394 |
|
|
Jun 22 04:41:12 PM PDT 24 |
Jun 22 04:41:26 PM PDT 24 |
14570100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2293586924 |
|
|
Jun 22 04:40:35 PM PDT 24 |
Jun 22 04:40:49 PM PDT 24 |
13012900 ps |
| T1151 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3067390211 |
|
|
Jun 22 04:40:57 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
47642900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.794369239 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:10 PM PDT 24 |
37730900 ps |
| T1153 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3188000186 |
|
|
Jun 22 04:40:50 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
52730600 ps |
| T1154 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3750259158 |
|
|
Jun 22 04:40:50 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
13629500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2010682354 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
736298600 ps |
| T316 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1279144859 |
|
|
Jun 22 04:40:42 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
795186400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4062036613 |
|
|
Jun 22 04:41:04 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
16969900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1917799104 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
25927200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1597232667 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:42:09 PM PDT 24 |
8421080900 ps |
| T1159 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2838460301 |
|
|
Jun 22 04:41:09 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
16338800 ps |
| T247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1696912989 |
|
|
Jun 22 04:40:29 PM PDT 24 |
Jun 22 04:40:50 PM PDT 24 |
18277800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.569785637 |
|
|
Jun 22 04:41:10 PM PDT 24 |
Jun 22 04:41:24 PM PDT 24 |
17607700 ps |
| T317 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1155760816 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:41:13 PM PDT 24 |
408406600 ps |
| T270 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1557178458 |
|
|
Jun 22 04:40:37 PM PDT 24 |
Jun 22 04:40:57 PM PDT 24 |
50675900 ps |
| T280 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1426582682 |
|
|
Jun 22 04:40:49 PM PDT 24 |
Jun 22 04:56:04 PM PDT 24 |
1338375900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2623919925 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
17623700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1887387536 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:18 PM PDT 24 |
18858800 ps |
| T318 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1537902427 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:41:01 PM PDT 24 |
70051100 ps |
| T1163 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1536886183 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:09 PM PDT 24 |
16448400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1685865458 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:41:45 PM PDT 24 |
6448252900 ps |
| T271 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2235160466 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
52114000 ps |
| T272 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1276064340 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
223162700 ps |
| T1165 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3743480338 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:00 PM PDT 24 |
55095600 ps |
| T393 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1433139346 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:48:16 PM PDT 24 |
747432000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2264051762 |
|
|
Jun 22 04:41:10 PM PDT 24 |
Jun 22 04:41:24 PM PDT 24 |
50753100 ps |
| T386 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.338306002 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:47:29 PM PDT 24 |
859008300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1318395841 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
14132300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2754031098 |
|
|
Jun 22 04:41:04 PM PDT 24 |
Jun 22 04:41:36 PM PDT 24 |
325603900 ps |
| T1169 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.635545608 |
|
|
Jun 22 04:41:08 PM PDT 24 |
Jun 22 04:41:24 PM PDT 24 |
40967300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3462489551 |
|
|
Jun 22 04:40:55 PM PDT 24 |
Jun 22 04:41:09 PM PDT 24 |
13903300 ps |
| T1171 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1496041761 |
|
|
Jun 22 04:40:29 PM PDT 24 |
Jun 22 04:40:54 PM PDT 24 |
653945400 ps |
| T1172 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4060517897 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:15 PM PDT 24 |
240669600 ps |
| T278 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.320473300 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:41:10 PM PDT 24 |
52031800 ps |
| T276 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2854011497 |
|
|
Jun 22 04:40:59 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
66908400 ps |
| T279 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.375802915 |
|
|
Jun 22 04:40:58 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
50304700 ps |
| T319 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4208088190 |
|
|
Jun 22 04:40:45 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
150736900 ps |
| T320 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2377396688 |
|
|
Jun 22 04:40:33 PM PDT 24 |
Jun 22 04:40:52 PM PDT 24 |
86408900 ps |
| T389 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2247249973 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:48:14 PM PDT 24 |
1565667900 ps |
| T321 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4182866552 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
343665600 ps |
| T385 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.4059064821 |
|
|
Jun 22 04:40:24 PM PDT 24 |
Jun 22 04:40:44 PM PDT 24 |
55830700 ps |
| T1173 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2448733981 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
21944700 ps |
| T1174 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3367521985 |
|
|
Jun 22 04:40:58 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
41070500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.457094453 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
213727100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3830638973 |
|
|
Jun 22 04:40:35 PM PDT 24 |
Jun 22 04:40:50 PM PDT 24 |
47605700 ps |
| T283 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.424832116 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
228972300 ps |
| T1177 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2119323635 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
37730100 ps |
| T1178 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.14069501 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
156084800 ps |
| T1179 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3607639114 |
|
|
Jun 22 04:41:08 PM PDT 24 |
Jun 22 04:41:22 PM PDT 24 |
115491400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.825616629 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
46722100 ps |
| T322 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.605273336 |
|
|
Jun 22 04:40:57 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
115805000 ps |
| T1181 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1836686199 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
215211100 ps |
| T1182 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2306099053 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:02 PM PDT 24 |
80900200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1977272495 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:00 PM PDT 24 |
13970200 ps |
| T1184 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3351769505 |
|
|
Jun 22 04:40:41 PM PDT 24 |
Jun 22 04:40:58 PM PDT 24 |
12629400 ps |
| T1185 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3364971524 |
|
|
Jun 22 04:40:36 PM PDT 24 |
Jun 22 04:40:51 PM PDT 24 |
15257400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3565054834 |
|
|
Jun 22 04:40:41 PM PDT 24 |
Jun 22 04:40:58 PM PDT 24 |
39109300 ps |
| T1187 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.4272286792 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
186131900 ps |
| T1188 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1668590205 |
|
|
Jun 22 04:40:55 PM PDT 24 |
Jun 22 04:41:11 PM PDT 24 |
12745700 ps |
| T1189 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2725876126 |
|
|
Jun 22 04:40:49 PM PDT 24 |
Jun 22 04:41:06 PM PDT 24 |
21160800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1611736246 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
159791400 ps |
| T1191 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.350594604 |
|
|
Jun 22 04:41:05 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
16151400 ps |
| T1192 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.431421544 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
131412300 ps |
| T282 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.283579776 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
65777200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2778255513 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:10 PM PDT 24 |
35039100 ps |
| T392 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.625137782 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:48:45 PM PDT 24 |
187917800 ps |
| T1194 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2753576731 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:11 PM PDT 24 |
41419800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.4046036709 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:41:08 PM PDT 24 |
34916500 ps |
| T1196 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1039001895 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
52429400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2283871736 |
|
|
Jun 22 04:40:52 PM PDT 24 |
Jun 22 04:41:10 PM PDT 24 |
44137300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.922592595 |
|
|
Jun 22 04:41:05 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
17824000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1887739304 |
|
|
Jun 22 04:40:25 PM PDT 24 |
Jun 22 04:41:15 PM PDT 24 |
2219228300 ps |
| T1200 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1151022585 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
44820700 ps |
| T1201 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.181294593 |
|
|
Jun 22 04:40:27 PM PDT 24 |
Jun 22 04:40:47 PM PDT 24 |
248346100 ps |
| T281 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1866755457 |
|
|
Jun 22 04:40:45 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
65292200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2522162205 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:20 PM PDT 24 |
110186200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1563713518 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:17 PM PDT 24 |
14662500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1255310172 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
587878200 ps |
| T1205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1457184031 |
|
|
Jun 22 04:40:43 PM PDT 24 |
Jun 22 04:41:00 PM PDT 24 |
60521600 ps |
| T1206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3541483896 |
|
|
Jun 22 04:40:27 PM PDT 24 |
Jun 22 04:40:49 PM PDT 24 |
63734500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2697067553 |
|
|
Jun 22 04:40:40 PM PDT 24 |
Jun 22 04:40:57 PM PDT 24 |
39926400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.836748817 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:13 PM PDT 24 |
39949300 ps |
| T388 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4161270959 |
|
|
Jun 22 04:41:01 PM PDT 24 |
Jun 22 04:56:09 PM PDT 24 |
355799100 ps |
| T1209 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3595448938 |
|
|
Jun 22 04:40:52 PM PDT 24 |
Jun 22 04:41:07 PM PDT 24 |
130091200 ps |
| T387 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2692865369 |
|
|
Jun 22 04:40:54 PM PDT 24 |
Jun 22 04:56:00 PM PDT 24 |
717033900 ps |
| T1210 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1699466026 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
51242900 ps |
| T1211 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3785291891 |
|
|
Jun 22 04:41:08 PM PDT 24 |
Jun 22 04:41:26 PM PDT 24 |
61286900 ps |
| T1212 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.810300868 |
|
|
Jun 22 04:41:07 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
137663500 ps |
| T286 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4199179164 |
|
|
Jun 22 04:40:54 PM PDT 24 |
Jun 22 04:41:13 PM PDT 24 |
50581400 ps |
| T1213 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1865283044 |
|
|
Jun 22 04:40:44 PM PDT 24 |
Jun 22 04:41:04 PM PDT 24 |
69626900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3569095760 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:14 PM PDT 24 |
50154400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1691647228 |
|
|
Jun 22 04:41:07 PM PDT 24 |
Jun 22 04:41:22 PM PDT 24 |
15240500 ps |
| T248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2261468155 |
|
|
Jun 22 04:40:34 PM PDT 24 |
Jun 22 04:40:48 PM PDT 24 |
52212200 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.328578551 |
|
|
Jun 22 04:41:03 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
103295600 ps |
| T1217 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3222512685 |
|
|
Jun 22 04:40:57 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
184272200 ps |
| T1218 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1491775361 |
|
|
Jun 22 04:40:59 PM PDT 24 |
Jun 22 04:41:16 PM PDT 24 |
251805800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.386951190 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:29 PM PDT 24 |
1274062800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1946688365 |
|
|
Jun 22 04:41:06 PM PDT 24 |
Jun 22 04:41:20 PM PDT 24 |
14047500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2065089057 |
|
|
Jun 22 04:40:46 PM PDT 24 |
Jun 22 04:41:26 PM PDT 24 |
1336475300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.530683841 |
|
|
Jun 22 04:40:34 PM PDT 24 |
Jun 22 04:40:48 PM PDT 24 |
12721700 ps |
| T1223 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4100406603 |
|
|
Jun 22 04:41:04 PM PDT 24 |
Jun 22 04:41:23 PM PDT 24 |
143960700 ps |
| T277 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4206861219 |
|
|
Jun 22 04:40:59 PM PDT 24 |
Jun 22 04:56:17 PM PDT 24 |
2755761100 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.623100263 |
|
|
Jun 22 04:40:36 PM PDT 24 |
Jun 22 04:40:51 PM PDT 24 |
59401500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.531068694 |
|
|
Jun 22 04:40:47 PM PDT 24 |
Jun 22 04:41:07 PM PDT 24 |
220829700 ps |
| T1226 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2036839561 |
|
|
Jun 22 04:40:47 PM PDT 24 |
Jun 22 04:48:34 PM PDT 24 |
380026800 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1322482655 |
|
|
Jun 22 04:40:36 PM PDT 24 |
Jun 22 04:40:52 PM PDT 24 |
41829100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3472111378 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
19144900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3466399902 |
|
|
Jun 22 04:41:16 PM PDT 24 |
Jun 22 04:41:34 PM PDT 24 |
57326100 ps |
| T391 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3519335241 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:56:11 PM PDT 24 |
1006475500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4147480106 |
|
|
Jun 22 04:41:01 PM PDT 24 |
Jun 22 04:41:18 PM PDT 24 |
25919400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1724901169 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:41:09 PM PDT 24 |
730719000 ps |
| T1232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1225859018 |
|
|
Jun 22 04:41:00 PM PDT 24 |
Jun 22 04:41:20 PM PDT 24 |
221767800 ps |
| T1233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2879020671 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:40:47 PM PDT 24 |
20765500 ps |
| T1234 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4057153281 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:24 PM PDT 24 |
170612300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3365804006 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
20777500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1134330420 |
|
|
Jun 22 04:40:26 PM PDT 24 |
Jun 22 04:41:28 PM PDT 24 |
1728995300 ps |
| T1237 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4008309598 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:31 PM PDT 24 |
2206344400 ps |
| T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.114396177 |
|
|
Jun 22 04:40:28 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
99180900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3821690274 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
104405700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1026021855 |
|
|
Jun 22 04:40:48 PM PDT 24 |
Jun 22 04:41:03 PM PDT 24 |
387748100 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1537826464 |
|
|
Jun 22 04:40:23 PM PDT 24 |
Jun 22 04:40:39 PM PDT 24 |
36607800 ps |
| T1241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3758719390 |
|
|
Jun 22 04:40:49 PM PDT 24 |
Jun 22 04:41:08 PM PDT 24 |
516193600 ps |
| T1242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2136135008 |
|
|
Jun 22 04:41:02 PM PDT 24 |
Jun 22 04:41:19 PM PDT 24 |
11342100 ps |
| T1243 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2630354726 |
|
|
Jun 22 04:40:37 PM PDT 24 |
Jun 22 04:40:52 PM PDT 24 |
34843500 ps |
| T1244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4042383029 |
|
|
Jun 22 04:40:32 PM PDT 24 |
Jun 22 04:41:28 PM PDT 24 |
4934539300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1912320785 |
|
|
Jun 22 04:40:54 PM PDT 24 |
Jun 22 04:41:08 PM PDT 24 |
16868800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2172944397 |
|
|
Jun 22 04:41:07 PM PDT 24 |
Jun 22 04:41:21 PM PDT 24 |
53702300 ps |
| T390 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2525499725 |
|
|
Jun 22 04:40:51 PM PDT 24 |
Jun 22 04:56:04 PM PDT 24 |
709992500 ps |
| T1247 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3590264054 |
|
|
Jun 22 04:40:50 PM PDT 24 |
Jun 22 04:41:05 PM PDT 24 |
18135500 ps |
| T1248 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.734432062 |
|
|
Jun 22 04:40:56 PM PDT 24 |
Jun 22 04:56:13 PM PDT 24 |
1436949600 ps |
| T1249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.368105848 |
|
|
Jun 22 04:40:28 PM PDT 24 |
Jun 22 04:41:12 PM PDT 24 |
416142400 ps |
| T1250 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1508850633 |
|
|
Jun 22 04:40:53 PM PDT 24 |
Jun 22 04:41:09 PM PDT 24 |
30123600 ps |
| T287 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3876449113 |
|
|
Jun 22 04:40:58 PM PDT 24 |
Jun 22 04:56:12 PM PDT 24 |
902724300 ps |
| T1251 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.705795125 |
|
|
Jun 22 04:41:11 PM PDT 24 |
Jun 22 04:41:25 PM PDT 24 |
65340900 ps |