Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	319280	1		T1	2		T2	2		T15	1
all_values[1]	319280	1		T1	2		T2	2		T15	1
all_values[2]	319280	1		T1	2		T2	2		T15	1
all_values[3]	319280	1		T1	2		T2	2		T15	1
all_values[4]	319280	1		T1	2		T2	2		T15	1
all_values[5]	319280	1		T1	2		T2	2		T15	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	644897	1		T1	12		T2	12		T15	6
auto[1]	1270783	1		T5	4608		T25	78976		T31	620

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	941101	1		T1	7		T2	7		T15	4
auto[1]	974579	1		T1	5		T2	5		T15	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	319128	1		T1	2		T2	2		T15	1
all_values[0]	auto[1]	auto[1]	152	1		T276	4		T277	4		T278	6
all_values[1]	auto[0]	auto[1]	319129	1		T1	2		T2	2		T15	1
all_values[1]	auto[1]	auto[1]	151	1		T276	3		T277	1		T278	2
all_values[2]	auto[0]	auto[0]	1622	1		T1	2		T2	2		T15	1
all_values[2]	auto[0]	auto[1]	50	1		T276	3		T328	1		T329	2
all_values[2]	auto[1]	auto[0]	317561	1		T5	1152		T25	19744		T31	155
all_values[2]	auto[1]	auto[1]	47	1		T276	1		T278	3		T328	2
all_values[3]	auto[0]	auto[0]	1603	1		T1	2		T2	2		T15	1
all_values[3]	auto[0]	auto[1]	51	1		T276	3		T278	2		T328	2
all_values[3]	auto[1]	auto[0]	91361	1		T5	576		T31	77		T133	978
all_values[3]	auto[1]	auto[1]	226265	1		T5	576		T25	19744		T31	78
all_values[4]	auto[0]	auto[0]	1132	1		T1	1		T2	1		T15	1
all_values[4]	auto[0]	auto[1]	523	1		T1	1		T2	1		T7	1
all_values[4]	auto[1]	auto[0]	208745	1		T5	576		T25	18968		T31	77
all_values[4]	auto[1]	auto[1]	108880	1		T5	576		T25	776		T31	78
all_values[5]	auto[0]	auto[0]	1527	1		T1	2		T2	2		T15	1
all_values[5]	auto[0]	auto[1]	132	1		T33	1		T20	3		T34	1
all_values[5]	auto[1]	auto[0]	317550	1		T5	1152		T25	19744		T31	155
all_values[5]	auto[1]	auto[1]	71	1		T276	1		T278	3		T328	4