Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	237764	1		T1	309		T2	3		T7	309
auto[FlashEraseBank]	267169	1		T2	2		T4	3		T5	270

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	257566	1		T1	8		T2	1		T7	9
auto[FlashOpProgram]	227852	1		T1	288		T2	4		T7	288
auto[FlashOpErase]	15515	1		T1	13		T7	12		T38	100
auto[FlashOpInvalid]	4000	1		T38	200		T140	200		T110	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	257566	1		T1	8		T2	1		T7	9
op[FlashOpProgram]	227852	1		T1	288		T2	4		T7	288
op[FlashOpErase]	15515	1		T1	13		T7	12		T38	100
read_erase_read	535	1		T1	1		T7	2		T4	1
read_prog_read	771	1		T4	1		T6	5		T22	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	369215	1		T2	5		T11	1		T38	600
auto[FlashPartInfo]	131790	1		T1	309		T7	309		T5	576
auto[FlashPartInfo1]	838	1		T25	15		T163	2		T127	4
auto[FlashPartInfo2]	3090	1		T11	2		T6	6		T25	31

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190124	1		T2	1		T11	1		T38	200
auto[FlashPartData]	auto[FlashOpProgram]	171567	1		T2	4		T38	100		T4	6
auto[FlashPartData]	auto[FlashOpErase]	3618	1		T38	100		T4	3		T24	5
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T38	200		T140	198		T110	192
auto[FlashPartInfo]	auto[FlashOpRead]	64616	1		T1	8		T7	9		T5	576
auto[FlashPartInfo]	auto[FlashOpProgram]	55220	1		T1	288		T7	288		T6	49
auto[FlashPartInfo]	auto[FlashOpErase]	11872	1		T1	13		T7	12		T24	13
auto[FlashPartInfo]	auto[FlashOpInvalid]	82	1		T140	2		T110	6		T142	14
auto[FlashPartInfo1]	auto[FlashOpRead]	657	1		T25	15		T163	2		T127	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T110	1		T141	1		T57	32
auto[FlashPartInfo1]	auto[FlashOpErase]	8	1		T110	1		T114	1		T116	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T110	2		T116	2		T118	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2169	1		T6	5		T25	31		T34	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	900	1		T11	2		T6	1		T52	5
auto[FlashPartInfo2]	auto[FlashOpErase]	17	1		T139	1		T128	2		T130	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T399	2		T400	2		-	-