Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30538	1		T38	400		T4	4		T30	4
auto[1]	71	1		T24	1		T72	4		T126	1
auto[2]	61	1		T127	1		T368	1		T130	2
auto[3]	229	1		T24	5		T23	1		T26	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7727	1		T38	100		T4	1		T24	1
evic_idx[1]	7737	1		T38	100		T4	1		T24	3
evic_idx[2]	7716	1		T38	100		T4	1		T30	1
evic_idx[3]	7719	1		T38	100		T4	1		T24	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29941	1		T38	400		T24	6		T30	4
evic_op[2]	322	1		T49	28		T23	1		T26	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7418	1		T38	100		T30	1		T69	173
evic_idx[0]	evic_op[1]	auto[1]	10	1		T130	1		T401	1		T402	1
evic_idx[0]	evic_op[1]	auto[2]	7	1		T403	2		T401	3		T404	2
evic_idx[0]	evic_op[1]	auto[3]	53	1		T24	1		T139	6		T128	4
evic_idx[0]	evic_op[2]	auto[0]	63	1		T49	7		T388	1		T230	7
evic_idx[0]	evic_op[2]	auto[1]	6	1		T72	1		T261	1		T405	1
evic_idx[0]	evic_op[2]	auto[2]	2	1		T368	1		T405	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T108	1		T287	1		T406	1
evic_idx[1]	evic_op[1]	auto[0]	7418	1		T38	100		T30	1		T69	173
evic_idx[1]	evic_op[1]	auto[1]	15	1		T130	2		T407	3		T401	1
evic_idx[1]	evic_op[1]	auto[2]	9	1		T403	2		T401	5		T404	2
evic_idx[1]	evic_op[1]	auto[3]	55	1		T24	3		T139	4		T128	4
evic_idx[1]	evic_op[2]	auto[0]	63	1		T49	7		T388	1		T230	7
evic_idx[1]	evic_op[2]	auto[1]	6	1		T72	1		T129	1		T261	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T127	1		T408	1		T409	1
evic_idx[1]	evic_op[2]	auto[3]	9	1		T108	1		T410	1		T411	1
evic_idx[2]	evic_op[1]	auto[0]	7417	1		T38	100		T30	1		T69	173
evic_idx[2]	evic_op[1]	auto[1]	12	1		T130	3		T407	2		T401	1
evic_idx[2]	evic_op[1]	auto[2]	8	1		T130	1		T403	3		T401	3
evic_idx[2]	evic_op[1]	auto[3]	41	1		T139	5		T128	1		T412	3
evic_idx[2]	evic_op[2]	auto[0]	62	1		T49	7		T388	1		T230	7
evic_idx[2]	evic_op[2]	auto[1]	7	1		T72	1		T126	1		T129	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T408	1		T157	2		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T366	1		T413	1		T291	1
evic_idx[3]	evic_op[1]	auto[0]	7418	1		T38	100		T30	1		T69	173
evic_idx[3]	evic_op[1]	auto[1]	11	1		T24	1		T130	3		T407	1
evic_idx[3]	evic_op[1]	auto[2]	8	1		T130	1		T403	4		T401	2
evic_idx[3]	evic_op[1]	auto[3]	41	1		T24	1		T139	5		T128	4
evic_idx[3]	evic_op[2]	auto[0]	63	1		T49	7		T388	1		T138	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T72	1		T414	1		T261	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T415	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T23	1		T26	1		T35	1