Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	25710	1		T25	8139		T258	1407		T332	1453
rd_lvl[2]	44546	1		T25	4229		T80	11280		T333	2651
rd_lvl[3]	10032	1		T25	1		T80	344		T333	2159
rd_lvl[4]	16360	1		T25	1		T288	1175		T333	1226
rd_lvl[5]	12163	1		T288	395		T123	2433		T80	1
rd_lvl[6]	13932	1		T123	2271		T333	3084		T334	410
rd_lvl[7]	9549	1		T25	1		T288	176		T335	460
rd_lvl[8]	15928	1		T25	2		T136	1929		T288	1
rd_lvl[9]	7645	1		T25	1		T136	1419		T335	8
rd_lvl[10]	8655	1		T336	1002		T337	1323		T338	231
rd_lvl[11]	5836	1		T5	300		T25	1		T237	548
rd_lvl[12]	12791	1		T5	213		T237	1167		T288	176
rd_lvl[13]	3695	1		T5	1		T133	362		T205	328
rd_lvl[14]	6595	1		T5	62		T25	2		T133	616
rd_lvl[15]	4457	1		T31	61		T32	11		T339	1