Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	319280	1		T1	2		T2	2		T15	1
all_pins[1]	319280	1		T1	2		T2	2		T15	1
all_pins[2]	319280	1		T1	2		T2	2		T15	1
all_pins[3]	319280	1		T1	2		T2	2		T15	1
all_pins[4]	319280	1		T1	2		T2	2		T15	1
all_pins[5]	319280	1		T1	2		T2	2		T15	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1597030	1		T1	12		T2	12		T15	6
values[0x1]	318650	1		T5	1152		T25	13565		T31	189
transitions[0x0=>0x1]	291886	1		T5	1152		T25	12377		T31	155
transitions[0x1=>0x0]	291870	1		T5	1152		T25	12377		T31	155

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	319128	1		T1	2		T2	2		T15	1
all_pins[0]	values[0x1]	152	1		T276	4		T277	4		T278	6
all_pins[0]	transitions[0x0=>0x1]	88	1		T276	3		T277	3		T278	5
all_pins[0]	transitions[0x1=>0x0]	87	1		T276	2		T278	1		T331	3
all_pins[1]	values[0x0]	319129	1		T1	2		T2	2		T15	1
all_pins[1]	values[0x1]	151	1		T276	3		T277	1		T278	2
all_pins[1]	transitions[0x0=>0x1]	134	1		T276	3		T277	1		T278	1
all_pins[1]	transitions[0x1=>0x0]	2290	1		T31	17		T32	5		T341	16
all_pins[2]	values[0x0]	316973	1		T1	2		T2	2		T15	1
all_pins[2]	values[0x1]	2307	1		T31	17		T32	5		T341	16
all_pins[2]	transitions[0x0=>0x1]	40	1		T276	1		T278	3		T328	2
all_pins[2]	transitions[0x1=>0x0]	197937	1		T5	576		T25	12377		T31	61
all_pins[3]	values[0x0]	119076	1		T1	2		T2	2		T15	1
all_pins[3]	values[0x1]	200204	1		T5	576		T25	12377		T31	78
all_pins[3]	transitions[0x0=>0x1]	175836	1		T5	576		T25	11189		T31	61
all_pins[3]	transitions[0x1=>0x0]	91397	1		T5	576		T31	77		T133	978
all_pins[4]	values[0x0]	203515	1		T1	2		T2	2		T15	1
all_pins[4]	values[0x1]	115765	1		T5	576		T25	1188		T31	94
all_pins[4]	transitions[0x0=>0x1]	115753	1		T5	576		T25	1188		T31	94
all_pins[4]	transitions[0x1=>0x0]	59	1		T276	1		T278	2		T328	4
all_pins[5]	values[0x0]	319209	1		T1	2		T2	2		T15	1
all_pins[5]	values[0x1]	71	1		T276	1		T278	3		T328	4
all_pins[5]	transitions[0x0=>0x1]	35	1		T278	1		T328	2		T329	1
all_pins[5]	transitions[0x1=>0x0]	100	1		T276	3		T277	3		T278	4