Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T276	7		T277	4		T278	7
all_values[1]	281	1		T276	7		T277	4		T278	7
all_values[2]	281	1		T276	7		T277	4		T278	7
all_values[3]	281	1		T276	7		T277	4		T278	7
all_values[4]	281	1		T276	7		T277	4		T278	7
all_values[5]	281	1		T276	7		T277	4		T278	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	916	1		T276	22		T277	13		T278	18
auto[1]	770	1		T276	20		T277	11		T278	24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	582	1		T276	11		T277	14		T278	10
auto[1]	1104	1		T276	31		T277	10		T278	32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1031	1		T276	24		T277	22		T278	22
auto[1]	655	1		T276	18		T277	2		T278	20

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	92	1		T276	1		T277	1		T328	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1		T276	1		T277	3		T278	3
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T276	3		T278	2		T328	1
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T276	2		T278	2		T328	2
all_values[1]	auto[0]	auto[0]	auto[1]	94	1		T276	2		T277	2		T278	2
all_values[1]	auto[0]	auto[1]	auto[1]	81	1		T276	4		T277	1		T278	2
all_values[1]	auto[1]	auto[0]	auto[1]	62	1		T277	1		T278	2		T328	4
all_values[1]	auto[1]	auto[1]	auto[1]	44	1		T276	1		T278	1		T329	1
all_values[2]	auto[0]	auto[0]	auto[0]	101	1		T276	3		T277	3		T278	2
all_values[2]	auto[0]	auto[1]	auto[0]	83	1		T277	1		T278	2		T328	2
all_values[2]	auto[1]	auto[0]	auto[1]	63	1		T276	3		T278	1		T328	1
all_values[2]	auto[1]	auto[1]	auto[1]	34	1		T276	1		T278	2		T328	2
all_values[3]	auto[0]	auto[0]	auto[0]	93	1		T276	3		T277	1		T278	3
all_values[3]	auto[0]	auto[1]	auto[0]	88	1		T276	1		T277	3		T278	1
all_values[3]	auto[1]	auto[0]	auto[1]	53	1		T276	2		T278	1		T328	2
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T276	1		T278	2		T329	1
all_values[4]	auto[0]	auto[0]	auto[0]	47	1		T277	1		T278	1		T329	2
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T276	2		T328	2		T330	1
all_values[4]	auto[0]	auto[1]	auto[0]	59	1		T276	1		T277	1		T329	1
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T276	1		T277	1		T278	2
all_values[4]	auto[1]	auto[0]	auto[1]	67	1		T276	2		T278	1		T328	3
all_values[4]	auto[1]	auto[1]	auto[1]	58	1		T276	1		T277	1		T278	3
all_values[5]	auto[0]	auto[0]	auto[0]	68	1		T277	4		T329	1		T331	2
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T276	1		T278	1		T328	2
all_values[5]	auto[0]	auto[1]	auto[0]	43	1		T276	3		T278	1		T329	1
all_values[5]	auto[0]	auto[1]	auto[1]	34	1		T276	1		T278	2		T328	2
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T278	2		T328	1		T331	2
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T276	2		T278	1		T328	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal