| T1066 |
/workspace/coverage/default/4.flash_ctrl_full_mem_access.3763427632 |
|
|
Jun 23 06:32:10 PM PDT 24 |
Jun 23 07:20:23 PM PDT 24 |
79506742300 ps |
| T1067 |
/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.4281251317 |
|
|
Jun 23 06:37:48 PM PDT 24 |
Jun 23 06:40:10 PM PDT 24 |
11795613800 ps |
| T1068 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.1978386126 |
|
|
Jun 23 06:35:41 PM PDT 24 |
Jun 23 06:35:55 PM PDT 24 |
18414600 ps |
| T1069 |
/workspace/coverage/default/0.flash_ctrl_disable.1819282270 |
|
|
Jun 23 06:30:42 PM PDT 24 |
Jun 23 06:31:04 PM PDT 24 |
17482900 ps |
| T1070 |
/workspace/coverage/default/1.flash_ctrl_re_evict.1845133646 |
|
|
Jun 23 06:31:03 PM PDT 24 |
Jun 23 06:31:35 PM PDT 24 |
79394100 ps |
| T1071 |
/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1698078036 |
|
|
Jun 23 06:33:04 PM PDT 24 |
Jun 23 06:38:05 PM PDT 24 |
38541725000 ps |
| T1072 |
/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2258786878 |
|
|
Jun 23 06:33:36 PM PDT 24 |
Jun 23 06:33:50 PM PDT 24 |
32664700 ps |
| T1073 |
/workspace/coverage/default/9.flash_ctrl_otp_reset.3071634120 |
|
|
Jun 23 06:33:41 PM PDT 24 |
Jun 23 06:35:32 PM PDT 24 |
41904600 ps |
| T1074 |
/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4217644311 |
|
|
Jun 23 06:37:23 PM PDT 24 |
Jun 23 06:39:15 PM PDT 24 |
4484320200 ps |
| T1075 |
/workspace/coverage/default/5.flash_ctrl_ro_serr.134549049 |
|
|
Jun 23 06:32:44 PM PDT 24 |
Jun 23 06:34:52 PM PDT 24 |
2168604800 ps |
| T1076 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.2912559618 |
|
|
Jun 23 06:31:03 PM PDT 24 |
Jun 23 06:32:28 PM PDT 24 |
3482591600 ps |
| T1077 |
/workspace/coverage/default/15.flash_ctrl_smoke.109342084 |
|
|
Jun 23 06:35:12 PM PDT 24 |
Jun 23 06:37:14 PM PDT 24 |
27160700 ps |
| T1078 |
/workspace/coverage/default/22.flash_ctrl_connect.951119633 |
|
|
Jun 23 06:36:27 PM PDT 24 |
Jun 23 06:36:40 PM PDT 24 |
22457700 ps |
| T236 |
/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.276584586 |
|
|
Jun 23 06:32:30 PM PDT 24 |
Jun 23 06:32:44 PM PDT 24 |
15759300 ps |
| T1079 |
/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.1004495148 |
|
|
Jun 23 06:35:33 PM PDT 24 |
Jun 23 06:37:26 PM PDT 24 |
2693051300 ps |
| T1080 |
/workspace/coverage/default/4.flash_ctrl_host_dir_rd.1998854112 |
|
|
Jun 23 06:32:04 PM PDT 24 |
Jun 23 06:32:52 PM PDT 24 |
71906900 ps |
| T1081 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.1835316091 |
|
|
Jun 23 06:38:31 PM PDT 24 |
Jun 23 06:40:44 PM PDT 24 |
73501500 ps |
| T1082 |
/workspace/coverage/default/16.flash_ctrl_mp_regions.1375118541 |
|
|
Jun 23 06:35:26 PM PDT 24 |
Jun 23 06:37:41 PM PDT 24 |
8976110700 ps |
| T1083 |
/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.2039010991 |
|
|
Jun 23 06:36:49 PM PDT 24 |
Jun 23 06:37:17 PM PDT 24 |
26595400 ps |
| T1084 |
/workspace/coverage/default/40.flash_ctrl_smoke.1124437436 |
|
|
Jun 23 06:37:53 PM PDT 24 |
Jun 23 06:40:21 PM PDT 24 |
46901000 ps |
| T1085 |
/workspace/coverage/default/7.flash_ctrl_re_evict.3704300213 |
|
|
Jun 23 06:33:21 PM PDT 24 |
Jun 23 06:33:54 PM PDT 24 |
71527800 ps |
| T1086 |
/workspace/coverage/default/1.flash_ctrl_alert_test.833786421 |
|
|
Jun 23 06:31:09 PM PDT 24 |
Jun 23 06:31:23 PM PDT 24 |
117484600 ps |
| T1087 |
/workspace/coverage/default/3.flash_ctrl_sec_info_access.2039082416 |
|
|
Jun 23 06:31:56 PM PDT 24 |
Jun 23 06:33:10 PM PDT 24 |
3432677200 ps |
| T1088 |
/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1501378655 |
|
|
Jun 23 06:33:04 PM PDT 24 |
Jun 23 06:33:54 PM PDT 24 |
10065785100 ps |
| T1089 |
/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.317751001 |
|
|
Jun 23 06:33:16 PM PDT 24 |
Jun 23 06:36:52 PM PDT 24 |
78413312800 ps |
| T1090 |
/workspace/coverage/default/27.flash_ctrl_prog_reset.2743847252 |
|
|
Jun 23 06:36:57 PM PDT 24 |
Jun 23 06:37:12 PM PDT 24 |
30354000 ps |
| T1091 |
/workspace/coverage/default/0.flash_ctrl_derr_detect.12953396 |
|
|
Jun 23 06:30:35 PM PDT 24 |
Jun 23 06:32:20 PM PDT 24 |
120189300 ps |
| T1092 |
/workspace/coverage/default/7.flash_ctrl_otp_reset.2455053665 |
|
|
Jun 23 06:33:10 PM PDT 24 |
Jun 23 06:35:21 PM PDT 24 |
77176900 ps |
| T1093 |
/workspace/coverage/default/33.flash_ctrl_intr_rd.3550572348 |
|
|
Jun 23 06:37:26 PM PDT 24 |
Jun 23 06:39:48 PM PDT 24 |
895090000 ps |
| T1094 |
/workspace/coverage/default/18.flash_ctrl_smoke.2227743632 |
|
|
Jun 23 06:35:45 PM PDT 24 |
Jun 23 06:38:31 PM PDT 24 |
53437100 ps |
| T1095 |
/workspace/coverage/default/0.flash_ctrl_erase_suspend.2162195278 |
|
|
Jun 23 06:30:26 PM PDT 24 |
Jun 23 06:41:41 PM PDT 24 |
4757960000 ps |
| T1096 |
/workspace/coverage/default/6.flash_ctrl_connect.2701941703 |
|
|
Jun 23 06:33:11 PM PDT 24 |
Jun 23 06:33:27 PM PDT 24 |
112224700 ps |
| T1097 |
/workspace/coverage/default/49.flash_ctrl_otp_reset.3481022403 |
|
|
Jun 23 06:38:21 PM PDT 24 |
Jun 23 06:40:12 PM PDT 24 |
73684600 ps |
| T1098 |
/workspace/coverage/default/11.flash_ctrl_alert_test.1265354350 |
|
|
Jun 23 06:34:26 PM PDT 24 |
Jun 23 06:34:40 PM PDT 24 |
250740700 ps |
| T173 |
/workspace/coverage/default/0.flash_ctrl_mid_op_rst.3583549496 |
|
|
Jun 23 06:30:31 PM PDT 24 |
Jun 23 06:31:44 PM PDT 24 |
11760964600 ps |
| T264 |
/workspace/coverage/default/4.flash_ctrl_integrity.4179324246 |
|
|
Jun 23 06:32:23 PM PDT 24 |
Jun 23 06:44:43 PM PDT 24 |
4318674000 ps |
| T1099 |
/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3560561032 |
|
|
Jun 23 06:37:14 PM PDT 24 |
Jun 23 06:40:07 PM PDT 24 |
25323667200 ps |
| T1100 |
/workspace/coverage/default/9.flash_ctrl_rw_evict.3083437093 |
|
|
Jun 23 06:33:47 PM PDT 24 |
Jun 23 06:34:17 PM PDT 24 |
68845600 ps |
| T1101 |
/workspace/coverage/default/3.flash_ctrl_rand_ops.812184923 |
|
|
Jun 23 06:31:34 PM PDT 24 |
Jun 23 06:54:42 PM PDT 24 |
4559250000 ps |
| T1102 |
/workspace/coverage/default/42.flash_ctrl_connect.1602652163 |
|
|
Jun 23 06:38:01 PM PDT 24 |
Jun 23 06:38:15 PM PDT 24 |
49675300 ps |
| T1103 |
/workspace/coverage/default/0.flash_ctrl_rd_ooo.3877417574 |
|
|
Jun 23 06:30:44 PM PDT 24 |
Jun 23 06:31:29 PM PDT 24 |
156646800 ps |
| T1104 |
/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1817474127 |
|
|
Jun 23 06:31:26 PM PDT 24 |
Jun 23 06:36:20 PM PDT 24 |
189963344500 ps |
| T1105 |
/workspace/coverage/default/7.flash_ctrl_connect.306136104 |
|
|
Jun 23 06:33:21 PM PDT 24 |
Jun 23 06:33:35 PM PDT 24 |
13637200 ps |
| T276 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1469446123 |
|
|
Jun 23 07:12:15 PM PDT 24 |
Jun 23 07:12:29 PM PDT 24 |
47397000 ps |
| T1106 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1948550658 |
|
|
Jun 23 07:11:29 PM PDT 24 |
Jun 23 07:11:43 PM PDT 24 |
35496800 ps |
| T1107 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3395143519 |
|
|
Jun 23 07:11:33 PM PDT 24 |
Jun 23 07:11:50 PM PDT 24 |
23888200 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2412958662 |
|
|
Jun 23 07:10:40 PM PDT 24 |
Jun 23 07:10:56 PM PDT 24 |
67373900 ps |
| T277 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3694500905 |
|
|
Jun 23 07:10:29 PM PDT 24 |
Jun 23 07:10:44 PM PDT 24 |
15746400 ps |
| T278 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.891098050 |
|
|
Jun 23 07:10:54 PM PDT 24 |
Jun 23 07:11:08 PM PDT 24 |
32326600 ps |
| T328 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.366625122 |
|
|
Jun 23 07:12:02 PM PDT 24 |
Jun 23 07:12:16 PM PDT 24 |
25610000 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2100285867 |
|
|
Jun 23 07:10:30 PM PDT 24 |
Jun 23 07:25:38 PM PDT 24 |
13290985800 ps |
| T1108 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.416571683 |
|
|
Jun 23 07:11:52 PM PDT 24 |
Jun 23 07:12:07 PM PDT 24 |
31201700 ps |
| T1109 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3672310687 |
|
|
Jun 23 07:11:28 PM PDT 24 |
Jun 23 07:11:44 PM PDT 24 |
18547700 ps |
| T94 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2210590769 |
|
|
Jun 23 07:11:16 PM PDT 24 |
Jun 23 07:11:35 PM PDT 24 |
101697700 ps |
| T1110 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.625238688 |
|
|
Jun 23 07:10:36 PM PDT 24 |
Jun 23 07:10:52 PM PDT 24 |
11395400 ps |
| T63 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1285609715 |
|
|
Jun 23 07:10:48 PM PDT 24 |
Jun 23 07:18:36 PM PDT 24 |
648792900 ps |
| T231 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.822150040 |
|
|
Jun 23 07:11:29 PM PDT 24 |
Jun 23 07:11:50 PM PDT 24 |
59599200 ps |
| T1111 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1369507407 |
|
|
Jun 23 07:11:18 PM PDT 24 |
Jun 23 07:11:31 PM PDT 24 |
19729600 ps |
| T1112 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1380030499 |
|
|
Jun 23 07:11:58 PM PDT 24 |
Jun 23 07:12:15 PM PDT 24 |
13532000 ps |
| T95 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1773670825 |
|
|
Jun 23 07:10:59 PM PDT 24 |
Jun 23 07:11:19 PM PDT 24 |
469964700 ps |
| T265 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2528785298 |
|
|
Jun 23 07:11:21 PM PDT 24 |
Jun 23 07:11:39 PM PDT 24 |
309684100 ps |
| T232 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2743144496 |
|
|
Jun 23 07:11:44 PM PDT 24 |
Jun 23 07:12:00 PM PDT 24 |
115766200 ps |
| T266 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3330018797 |
|
|
Jun 23 07:11:20 PM PDT 24 |
Jun 23 07:11:39 PM PDT 24 |
102701300 ps |
| T329 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2442041173 |
|
|
Jun 23 07:10:58 PM PDT 24 |
Jun 23 07:11:12 PM PDT 24 |
26079900 ps |
| T233 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3794410877 |
|
|
Jun 23 07:11:25 PM PDT 24 |
Jun 23 07:24:25 PM PDT 24 |
2581274800 ps |
| T1113 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2269197106 |
|
|
Jun 23 07:11:33 PM PDT 24 |
Jun 23 07:11:49 PM PDT 24 |
14239100 ps |
| T243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3212348310 |
|
|
Jun 23 07:11:02 PM PDT 24 |
Jun 23 07:11:23 PM PDT 24 |
113901800 ps |
| T1114 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2964417963 |
|
|
Jun 23 07:10:31 PM PDT 24 |
Jun 23 07:10:47 PM PDT 24 |
34496600 ps |
| T267 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.934677164 |
|
|
Jun 23 07:10:54 PM PDT 24 |
Jun 23 07:11:12 PM PDT 24 |
33508300 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.4272104926 |
|
|
Jun 23 07:10:31 PM PDT 24 |
Jun 23 07:10:48 PM PDT 24 |
96221600 ps |
| T331 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1535352615 |
|
|
Jun 23 07:11:25 PM PDT 24 |
Jun 23 07:11:39 PM PDT 24 |
75439700 ps |
| T245 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1435636015 |
|
|
Jun 23 07:11:29 PM PDT 24 |
Jun 23 07:11:50 PM PDT 24 |
385539000 ps |
| T268 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.691937143 |
|
|
Jun 23 07:11:26 PM PDT 24 |
Jun 23 07:11:45 PM PDT 24 |
32732500 ps |
| T1115 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3155775152 |
|
|
Jun 23 07:12:01 PM PDT 24 |
Jun 23 07:12:15 PM PDT 24 |
175131200 ps |
| T269 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1787975420 |
|
|
Jun 23 07:11:46 PM PDT 24 |
Jun 23 07:12:01 PM PDT 24 |
328875300 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3335275376 |
|
|
Jun 23 07:10:43 PM PDT 24 |
Jun 23 07:11:04 PM PDT 24 |
130805500 ps |
| T247 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4138005376 |
|
|
Jun 23 07:11:34 PM PDT 24 |
Jun 23 07:11:51 PM PDT 24 |
64059600 ps |
| T1116 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.927583541 |
|
|
Jun 23 07:10:59 PM PDT 24 |
Jun 23 07:11:16 PM PDT 24 |
72200700 ps |
| T417 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1992491565 |
|
|
Jun 23 07:10:49 PM PDT 24 |
Jun 23 07:12:15 PM PDT 24 |
2362588800 ps |
| T330 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.603011006 |
|
|
Jun 23 07:11:41 PM PDT 24 |
Jun 23 07:11:55 PM PDT 24 |
16332900 ps |
| T1117 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1415354795 |
|
|
Jun 23 07:10:45 PM PDT 24 |
Jun 23 07:11:04 PM PDT 24 |
412500000 ps |
| T248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.135242600 |
|
|
Jun 23 07:10:41 PM PDT 24 |
Jun 23 07:10:55 PM PDT 24 |
20255000 ps |
| T1118 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1564776494 |
|
|
Jun 23 07:11:37 PM PDT 24 |
Jun 23 07:11:57 PM PDT 24 |
84199400 ps |
| T274 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2657012993 |
|
|
Jun 23 07:11:04 PM PDT 24 |
Jun 23 07:11:25 PM PDT 24 |
115049600 ps |
| T1119 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2610756418 |
|
|
Jun 23 07:11:27 PM PDT 24 |
Jun 23 07:11:43 PM PDT 24 |
121873400 ps |
| T1120 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1954821476 |
|
|
Jun 23 07:12:10 PM PDT 24 |
Jun 23 07:12:24 PM PDT 24 |
31614700 ps |
| T279 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.459086424 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:26:34 PM PDT 24 |
2390249400 ps |
| T1121 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.863438659 |
|
|
Jun 23 07:10:32 PM PDT 24 |
Jun 23 07:10:46 PM PDT 24 |
16696000 ps |
| T280 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1782845168 |
|
|
Jun 23 07:11:22 PM PDT 24 |
Jun 23 07:11:39 PM PDT 24 |
39970800 ps |
| T1122 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2999785676 |
|
|
Jun 23 07:10:57 PM PDT 24 |
Jun 23 07:11:11 PM PDT 24 |
16586500 ps |
| T347 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.401608409 |
|
|
Jun 23 07:11:19 PM PDT 24 |
Jun 23 07:26:17 PM PDT 24 |
1375605400 ps |
| T1123 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.387348375 |
|
|
Jun 23 07:10:39 PM PDT 24 |
Jun 23 07:11:00 PM PDT 24 |
61939600 ps |
| T282 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4041719490 |
|
|
Jun 23 07:11:24 PM PDT 24 |
Jun 23 07:11:43 PM PDT 24 |
187289600 ps |
| T1124 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.4184243520 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:11:00 PM PDT 24 |
24924800 ps |
| T1125 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2863277051 |
|
|
Jun 23 07:10:54 PM PDT 24 |
Jun 23 07:11:10 PM PDT 24 |
29474200 ps |
| T249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.86527528 |
|
|
Jun 23 07:10:34 PM PDT 24 |
Jun 23 07:10:48 PM PDT 24 |
37103800 ps |
| T1126 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2595179229 |
|
|
Jun 23 07:10:31 PM PDT 24 |
Jun 23 07:10:51 PM PDT 24 |
157014100 ps |
| T353 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3660839870 |
|
|
Jun 23 07:10:34 PM PDT 24 |
Jun 23 07:17:07 PM PDT 24 |
432500000 ps |
| T1127 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2828724453 |
|
|
Jun 23 07:11:52 PM PDT 24 |
Jun 23 07:12:06 PM PDT 24 |
44706500 ps |
| T1128 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2322043910 |
|
|
Jun 23 07:12:06 PM PDT 24 |
Jun 23 07:12:21 PM PDT 24 |
25183800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3091162282 |
|
|
Jun 23 07:12:15 PM PDT 24 |
Jun 23 07:12:30 PM PDT 24 |
18338400 ps |
| T1130 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2834020675 |
|
|
Jun 23 07:11:16 PM PDT 24 |
Jun 23 07:11:30 PM PDT 24 |
17716100 ps |
| T1131 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3888077662 |
|
|
Jun 23 07:12:07 PM PDT 24 |
Jun 23 07:12:21 PM PDT 24 |
15297200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2750171995 |
|
|
Jun 23 07:12:19 PM PDT 24 |
Jun 23 07:12:33 PM PDT 24 |
26808000 ps |
| T1133 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2055961930 |
|
|
Jun 23 07:12:15 PM PDT 24 |
Jun 23 07:12:29 PM PDT 24 |
17372200 ps |
| T1134 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1148520424 |
|
|
Jun 23 07:10:55 PM PDT 24 |
Jun 23 07:11:14 PM PDT 24 |
33112000 ps |
| T303 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.756534996 |
|
|
Jun 23 07:10:35 PM PDT 24 |
Jun 23 07:10:54 PM PDT 24 |
197104100 ps |
| T285 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.494680507 |
|
|
Jun 23 07:11:35 PM PDT 24 |
Jun 23 07:24:36 PM PDT 24 |
3554847900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1144684366 |
|
|
Jun 23 07:11:48 PM PDT 24 |
Jun 23 07:12:09 PM PDT 24 |
222163300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2581867891 |
|
|
Jun 23 07:10:49 PM PDT 24 |
Jun 23 07:11:05 PM PDT 24 |
173721700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3609024582 |
|
|
Jun 23 07:12:17 PM PDT 24 |
Jun 23 07:12:31 PM PDT 24 |
39994500 ps |
| T250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1465841957 |
|
|
Jun 23 07:10:50 PM PDT 24 |
Jun 23 07:11:04 PM PDT 24 |
29242900 ps |
| T1138 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3437837911 |
|
|
Jun 23 07:10:35 PM PDT 24 |
Jun 23 07:11:06 PM PDT 24 |
71420200 ps |
| T1139 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3589757721 |
|
|
Jun 23 07:11:12 PM PDT 24 |
Jun 23 07:11:26 PM PDT 24 |
147946500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1621197177 |
|
|
Jun 23 07:10:52 PM PDT 24 |
Jun 23 07:11:06 PM PDT 24 |
14721800 ps |
| T275 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4285367678 |
|
|
Jun 23 07:10:31 PM PDT 24 |
Jun 23 07:10:51 PM PDT 24 |
229819100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.15053734 |
|
|
Jun 23 07:11:57 PM PDT 24 |
Jun 23 07:12:13 PM PDT 24 |
22739100 ps |
| T1142 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1810100303 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:11:45 PM PDT 24 |
21698600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3888405220 |
|
|
Jun 23 07:12:07 PM PDT 24 |
Jun 23 07:12:21 PM PDT 24 |
15566500 ps |
| T1144 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2009419814 |
|
|
Jun 23 07:10:25 PM PDT 24 |
Jun 23 07:11:12 PM PDT 24 |
43336200 ps |
| T304 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1654116389 |
|
|
Jun 23 07:10:28 PM PDT 24 |
Jun 23 07:11:31 PM PDT 24 |
1599448200 ps |
| T1145 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.179320176 |
|
|
Jun 23 07:11:32 PM PDT 24 |
Jun 23 07:11:53 PM PDT 24 |
200782600 ps |
| T1146 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3288734225 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:01 PM PDT 24 |
16365100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3586516219 |
|
|
Jun 23 07:11:29 PM PDT 24 |
Jun 23 07:11:43 PM PDT 24 |
31265100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2219691974 |
|
|
Jun 23 07:10:35 PM PDT 24 |
Jun 23 07:11:11 PM PDT 24 |
807583800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1682936042 |
|
|
Jun 23 07:11:57 PM PDT 24 |
Jun 23 07:12:11 PM PDT 24 |
58702600 ps |
| T281 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1066318152 |
|
|
Jun 23 07:10:21 PM PDT 24 |
Jun 23 07:10:41 PM PDT 24 |
165504500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.351551251 |
|
|
Jun 23 07:10:25 PM PDT 24 |
Jun 23 07:10:39 PM PDT 24 |
12126600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2666842128 |
|
|
Jun 23 07:12:06 PM PDT 24 |
Jun 23 07:12:20 PM PDT 24 |
33374600 ps |
| T305 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2702997771 |
|
|
Jun 23 07:11:12 PM PDT 24 |
Jun 23 07:11:30 PM PDT 24 |
698643700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3562814653 |
|
|
Jun 23 07:12:19 PM PDT 24 |
Jun 23 07:12:33 PM PDT 24 |
48190900 ps |
| T350 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2862430572 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:19:36 PM PDT 24 |
347701400 ps |
| T348 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1060119192 |
|
|
Jun 23 07:11:38 PM PDT 24 |
Jun 23 07:26:45 PM PDT 24 |
870103700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.150800350 |
|
|
Jun 23 07:11:43 PM PDT 24 |
Jun 23 07:11:57 PM PDT 24 |
89052400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2083865234 |
|
|
Jun 23 07:12:14 PM PDT 24 |
Jun 23 07:12:28 PM PDT 24 |
37804300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3527025007 |
|
|
Jun 23 07:10:53 PM PDT 24 |
Jun 23 07:11:11 PM PDT 24 |
35650000 ps |
| T1156 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3607141091 |
|
|
Jun 23 07:12:10 PM PDT 24 |
Jun 23 07:12:24 PM PDT 24 |
47327300 ps |
| T306 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2322998337 |
|
|
Jun 23 07:10:20 PM PDT 24 |
Jun 23 07:18:13 PM PDT 24 |
1768657800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2200363571 |
|
|
Jun 23 07:12:06 PM PDT 24 |
Jun 23 07:12:20 PM PDT 24 |
30030400 ps |
| T308 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2999828270 |
|
|
Jun 23 07:10:39 PM PDT 24 |
Jun 23 07:11:11 PM PDT 24 |
58117000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2162739681 |
|
|
Jun 23 07:12:07 PM PDT 24 |
Jun 23 07:12:21 PM PDT 24 |
15902000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2060202888 |
|
|
Jun 23 07:10:42 PM PDT 24 |
Jun 23 07:18:28 PM PDT 24 |
1397306600 ps |
| T307 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.372600865 |
|
|
Jun 23 07:11:16 PM PDT 24 |
Jun 23 07:26:36 PM PDT 24 |
1283134700 ps |
| T309 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.565436882 |
|
|
Jun 23 07:11:56 PM PDT 24 |
Jun 23 07:12:11 PM PDT 24 |
176533200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3474897870 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:10:59 PM PDT 24 |
16785600 ps |
| T1161 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.807916250 |
|
|
Jun 23 07:10:27 PM PDT 24 |
Jun 23 07:10:43 PM PDT 24 |
33056700 ps |
| T310 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1736887666 |
|
|
Jun 23 07:11:37 PM PDT 24 |
Jun 23 07:11:56 PM PDT 24 |
405600300 ps |
| T283 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1711996852 |
|
|
Jun 23 07:11:56 PM PDT 24 |
Jun 23 07:12:16 PM PDT 24 |
55240100 ps |
| T1162 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3793300879 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:04 PM PDT 24 |
46918500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1245300707 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:11:44 PM PDT 24 |
35560800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1912788140 |
|
|
Jun 23 07:11:51 PM PDT 24 |
Jun 23 07:12:06 PM PDT 24 |
65532400 ps |
| T344 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1810494923 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:26:03 PM PDT 24 |
1928983200 ps |
| T1165 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1034380626 |
|
|
Jun 23 07:11:07 PM PDT 24 |
Jun 23 07:11:24 PM PDT 24 |
14008200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1334085634 |
|
|
Jun 23 07:11:40 PM PDT 24 |
Jun 23 07:11:58 PM PDT 24 |
27989300 ps |
| T251 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2801690259 |
|
|
Jun 23 07:10:45 PM PDT 24 |
Jun 23 07:10:59 PM PDT 24 |
23096400 ps |
| T284 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3110262203 |
|
|
Jun 23 07:11:23 PM PDT 24 |
Jun 23 07:11:40 PM PDT 24 |
72641200 ps |
| T252 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1893774069 |
|
|
Jun 23 07:10:26 PM PDT 24 |
Jun 23 07:10:41 PM PDT 24 |
37162800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3656709450 |
|
|
Jun 23 07:12:09 PM PDT 24 |
Jun 23 07:12:23 PM PDT 24 |
43449200 ps |
| T1168 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1698737432 |
|
|
Jun 23 07:11:38 PM PDT 24 |
Jun 23 07:11:52 PM PDT 24 |
27141000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4116445308 |
|
|
Jun 23 07:10:25 PM PDT 24 |
Jun 23 07:10:42 PM PDT 24 |
39666200 ps |
| T1170 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.363166736 |
|
|
Jun 23 07:11:35 PM PDT 24 |
Jun 23 07:11:53 PM PDT 24 |
68693000 ps |
| T1171 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2463271872 |
|
|
Jun 23 07:12:23 PM PDT 24 |
Jun 23 07:12:37 PM PDT 24 |
54845200 ps |
| T1172 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1949223434 |
|
|
Jun 23 07:12:09 PM PDT 24 |
Jun 23 07:12:24 PM PDT 24 |
15973300 ps |
| T343 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2574619456 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:11:03 PM PDT 24 |
132441300 ps |
| T1173 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3354366336 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:10:59 PM PDT 24 |
16707400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3892670441 |
|
|
Jun 23 07:10:46 PM PDT 24 |
Jun 23 07:11:47 PM PDT 24 |
1383947500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2377411414 |
|
|
Jun 23 07:11:46 PM PDT 24 |
Jun 23 07:12:00 PM PDT 24 |
88834600 ps |
| T286 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.172037242 |
|
|
Jun 23 07:10:52 PM PDT 24 |
Jun 23 07:11:12 PM PDT 24 |
113298900 ps |
| T1176 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1356967987 |
|
|
Jun 23 07:12:00 PM PDT 24 |
Jun 23 07:12:14 PM PDT 24 |
17812000 ps |
| T1177 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2688865891 |
|
|
Jun 23 07:11:35 PM PDT 24 |
Jun 23 07:11:52 PM PDT 24 |
36956700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2827499609 |
|
|
Jun 23 07:10:46 PM PDT 24 |
Jun 23 07:11:00 PM PDT 24 |
31644200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.224593046 |
|
|
Jun 23 07:12:21 PM PDT 24 |
Jun 23 07:12:35 PM PDT 24 |
15932900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1802173854 |
|
|
Jun 23 07:11:43 PM PDT 24 |
Jun 23 07:12:03 PM PDT 24 |
303077700 ps |
| T1181 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2219162198 |
|
|
Jun 23 07:11:46 PM PDT 24 |
Jun 23 07:12:03 PM PDT 24 |
35072100 ps |
| T1182 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1233294336 |
|
|
Jun 23 07:12:00 PM PDT 24 |
Jun 23 07:12:14 PM PDT 24 |
54324700 ps |
| T1183 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.374933377 |
|
|
Jun 23 07:10:52 PM PDT 24 |
Jun 23 07:11:06 PM PDT 24 |
24520000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.789237721 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:10:59 PM PDT 24 |
70691100 ps |
| T1185 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2722491875 |
|
|
Jun 23 07:10:40 PM PDT 24 |
Jun 23 07:11:02 PM PDT 24 |
684304900 ps |
| T1186 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3897441950 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:11:00 PM PDT 24 |
21217900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.876150524 |
|
|
Jun 23 07:10:56 PM PDT 24 |
Jun 23 07:11:13 PM PDT 24 |
31367800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3296544952 |
|
|
Jun 23 07:10:36 PM PDT 24 |
Jun 23 07:10:54 PM PDT 24 |
110482600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.433844809 |
|
|
Jun 23 07:11:19 PM PDT 24 |
Jun 23 07:11:34 PM PDT 24 |
15003100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4235051395 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:02 PM PDT 24 |
95705100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1998836485 |
|
|
Jun 23 07:11:39 PM PDT 24 |
Jun 23 07:11:58 PM PDT 24 |
68535500 ps |
| T1192 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2119520939 |
|
|
Jun 23 07:11:32 PM PDT 24 |
Jun 23 07:11:50 PM PDT 24 |
391265700 ps |
| T1193 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.208886398 |
|
|
Jun 23 07:12:06 PM PDT 24 |
Jun 23 07:12:19 PM PDT 24 |
27975900 ps |
| T1194 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3947274447 |
|
|
Jun 23 07:12:16 PM PDT 24 |
Jun 23 07:12:30 PM PDT 24 |
109150800 ps |
| T1195 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1322086938 |
|
|
Jun 23 07:10:59 PM PDT 24 |
Jun 23 07:11:15 PM PDT 24 |
108240200 ps |
| T1196 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.516487212 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:07 PM PDT 24 |
85709400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.894958683 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:06 PM PDT 24 |
142662500 ps |
| T352 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3771597430 |
|
|
Jun 23 07:11:00 PM PDT 24 |
Jun 23 07:26:10 PM PDT 24 |
803464400 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2348671028 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:12:07 PM PDT 24 |
170993200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4262164781 |
|
|
Jun 23 07:10:49 PM PDT 24 |
Jun 23 07:11:10 PM PDT 24 |
51699200 ps |
| T1200 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1796729182 |
|
|
Jun 23 07:10:27 PM PDT 24 |
Jun 23 07:11:37 PM PDT 24 |
659564800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1545869466 |
|
|
Jun 23 07:11:39 PM PDT 24 |
Jun 23 07:11:55 PM PDT 24 |
17594700 ps |
| T1202 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1597724941 |
|
|
Jun 23 07:10:56 PM PDT 24 |
Jun 23 07:11:30 PM PDT 24 |
65625900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3622687798 |
|
|
Jun 23 07:10:38 PM PDT 24 |
Jun 23 07:11:45 PM PDT 24 |
1297221200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3733433035 |
|
|
Jun 23 07:12:13 PM PDT 24 |
Jun 23 07:12:27 PM PDT 24 |
52667400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.98683609 |
|
|
Jun 23 07:11:35 PM PDT 24 |
Jun 23 07:11:53 PM PDT 24 |
92732500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2613512350 |
|
|
Jun 23 07:10:25 PM PDT 24 |
Jun 23 07:10:39 PM PDT 24 |
51237000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3480262198 |
|
|
Jun 23 07:11:52 PM PDT 24 |
Jun 23 07:12:27 PM PDT 24 |
251643800 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2351268143 |
|
|
Jun 23 07:10:41 PM PDT 24 |
Jun 23 07:11:19 PM PDT 24 |
1296077800 ps |
| T1209 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.916966918 |
|
|
Jun 23 07:10:43 PM PDT 24 |
Jun 23 07:11:18 PM PDT 24 |
891975400 ps |
| T1210 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.389995298 |
|
|
Jun 23 07:11:40 PM PDT 24 |
Jun 23 07:11:57 PM PDT 24 |
45076100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.111446384 |
|
|
Jun 23 07:10:38 PM PDT 24 |
Jun 23 07:10:54 PM PDT 24 |
14432500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.212935202 |
|
|
Jun 23 07:10:38 PM PDT 24 |
Jun 23 07:10:54 PM PDT 24 |
13774600 ps |
| T349 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3859177372 |
|
|
Jun 23 07:11:00 PM PDT 24 |
Jun 23 07:18:46 PM PDT 24 |
371700900 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.892007708 |
|
|
Jun 23 07:11:38 PM PDT 24 |
Jun 23 07:11:54 PM PDT 24 |
24231800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1975622244 |
|
|
Jun 23 07:10:31 PM PDT 24 |
Jun 23 07:10:45 PM PDT 24 |
21962400 ps |
| T311 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1594562720 |
|
|
Jun 23 07:10:58 PM PDT 24 |
Jun 23 07:11:17 PM PDT 24 |
376407700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.376332455 |
|
|
Jun 23 07:11:07 PM PDT 24 |
Jun 23 07:11:21 PM PDT 24 |
24165800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2437515816 |
|
|
Jun 23 07:11:56 PM PDT 24 |
Jun 23 07:12:15 PM PDT 24 |
138032500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.681342835 |
|
|
Jun 23 07:11:41 PM PDT 24 |
Jun 23 07:12:00 PM PDT 24 |
58489900 ps |
| T345 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.437884709 |
|
|
Jun 23 07:11:58 PM PDT 24 |
Jun 23 07:19:39 PM PDT 24 |
646165000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1959944413 |
|
|
Jun 23 07:10:43 PM PDT 24 |
Jun 23 07:11:01 PM PDT 24 |
41958000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.791156988 |
|
|
Jun 23 07:12:01 PM PDT 24 |
Jun 23 07:12:22 PM PDT 24 |
176395400 ps |
| T1220 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1391257983 |
|
|
Jun 23 07:11:11 PM PDT 24 |
Jun 23 07:11:46 PM PDT 24 |
230012400 ps |
| T1221 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3409969706 |
|
|
Jun 23 07:11:51 PM PDT 24 |
Jun 23 07:12:07 PM PDT 24 |
14289800 ps |
| T354 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.235738872 |
|
|
Jun 23 07:11:35 PM PDT 24 |
Jun 23 07:19:23 PM PDT 24 |
1226919600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.503261993 |
|
|
Jun 23 07:10:50 PM PDT 24 |
Jun 23 07:11:04 PM PDT 24 |
54197800 ps |
| T1223 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1527592162 |
|
|
Jun 23 07:10:47 PM PDT 24 |
Jun 23 07:11:17 PM PDT 24 |
310686800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2726503588 |
|
|
Jun 23 07:11:47 PM PDT 24 |
Jun 23 07:12:08 PM PDT 24 |
70835900 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3708408877 |
|
|
Jun 23 07:11:31 PM PDT 24 |
Jun 23 07:11:48 PM PDT 24 |
42008200 ps |
| T1226 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2341887456 |
|
|
Jun 23 07:10:54 PM PDT 24 |
Jun 23 07:11:11 PM PDT 24 |
43574200 ps |
| T1227 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4294767143 |
|
|
Jun 23 07:10:51 PM PDT 24 |
Jun 23 07:11:08 PM PDT 24 |
37566400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1657272026 |
|
|
Jun 23 07:10:41 PM PDT 24 |
Jun 23 07:10:55 PM PDT 24 |
18509800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1437924393 |
|
|
Jun 23 07:12:07 PM PDT 24 |
Jun 23 07:12:21 PM PDT 24 |
16903300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1993313166 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:11:47 PM PDT 24 |
12745000 ps |
| T346 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.890088377 |
|
|
Jun 23 07:10:53 PM PDT 24 |
Jun 23 07:23:34 PM PDT 24 |
2973953700 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.567003815 |
|
|
Jun 23 07:10:41 PM PDT 24 |
Jun 23 07:11:50 PM PDT 24 |
2629969800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1800221276 |
|
|
Jun 23 07:10:50 PM PDT 24 |
Jun 23 07:11:09 PM PDT 24 |
87035100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4156326107 |
|
|
Jun 23 07:11:30 PM PDT 24 |
Jun 23 07:11:45 PM PDT 24 |
45983300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3459256580 |
|
|
Jun 23 07:10:50 PM PDT 24 |
Jun 23 07:11:37 PM PDT 24 |
26937900 ps |
| T1235 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1454731080 |
|
|
Jun 23 07:11:20 PM PDT 24 |
Jun 23 07:11:38 PM PDT 24 |
28066300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3578351756 |
|
|
Jun 23 07:11:46 PM PDT 24 |
Jun 23 07:12:03 PM PDT 24 |
37287800 ps |
| T1237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2642838858 |
|
|
Jun 23 07:11:45 PM PDT 24 |
Jun 23 07:27:01 PM PDT 24 |
686686500 ps |
| T1238 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3991066833 |
|
|
Jun 23 07:11:01 PM PDT 24 |
Jun 23 07:11:16 PM PDT 24 |
34254200 ps |
| T1239 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3535964093 |
|
|
Jun 23 07:10:34 PM PDT 24 |
Jun 23 07:10:55 PM PDT 24 |
65125900 ps |
| T1240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1631263576 |
|
|
Jun 23 07:10:52 PM PDT 24 |
Jun 23 07:11:45 PM PDT 24 |
445085400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3893907961 |
|
|
Jun 23 07:11:51 PM PDT 24 |
Jun 23 07:12:08 PM PDT 24 |
322430400 ps |
| T1242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3687467394 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:11:31 PM PDT 24 |
73805200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2428351132 |
|
|
Jun 23 07:11:12 PM PDT 24 |
Jun 23 07:11:30 PM PDT 24 |
263932000 ps |
| T351 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.218764423 |
|
|
Jun 23 07:11:42 PM PDT 24 |
Jun 23 07:19:24 PM PDT 24 |
460897500 ps |
| T1244 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1415148266 |
|
|
Jun 23 07:12:21 PM PDT 24 |
Jun 23 07:12:35 PM PDT 24 |
56427200 ps |
| T1245 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2869419998 |
|
|
Jun 23 07:11:33 PM PDT 24 |
Jun 23 07:11:46 PM PDT 24 |
13455800 ps |
| T1246 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3637518706 |
|
|
Jun 23 07:11:42 PM PDT 24 |
Jun 23 07:11:55 PM PDT 24 |
19185200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3455910116 |
|
|
Jun 23 07:11:04 PM PDT 24 |
Jun 23 07:11:20 PM PDT 24 |
28987400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1784349482 |
|
|
Jun 23 07:11:49 PM PDT 24 |
Jun 23 07:12:06 PM PDT 24 |
82500400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1130582060 |
|
|
Jun 23 07:10:36 PM PDT 24 |
Jun 23 07:11:21 PM PDT 24 |
1469226500 ps |
| T1250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.237276662 |
|
|
Jun 23 07:10:44 PM PDT 24 |
Jun 23 07:10:59 PM PDT 24 |
30242700 ps |