Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	328632	1		T1	1		T2	2		T3	2
all_values[1]	328632	1		T1	1		T2	2		T3	2
all_values[2]	328632	1		T1	1		T2	2		T3	2
all_values[3]	328632	1		T1	1		T2	2		T3	2
all_values[4]	328632	1		T1	1		T2	2		T3	2
all_values[5]	328632	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	663622	1		T1	6		T2	12		T3	12
auto[1]	1308170	1		T15	2808		T24	632		T31	6076

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966504	1		T1	4		T2	7		T3	7
auto[1]	1005288	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	328472	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	160	1		T227	3		T228	4		T229	3
all_values[1]	auto[0]	auto[1]	328472	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	160	1		T227	6		T228	2		T229	1
all_values[2]	auto[0]	auto[0]	1619	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	61	1		T227	1		T229	1		T325	2
all_values[2]	auto[1]	auto[0]	326901	1		T15	702		T24	158		T31	1519
all_values[2]	auto[1]	auto[1]	51	1		T227	1		T228	1		T229	2
all_values[3]	auto[0]	auto[0]	1590	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	58	1		T227	1		T229	1		T325	1
all_values[3]	auto[1]	auto[0]	86108	1		T15	351		T24	79		T31	453
all_values[3]	auto[1]	auto[1]	240876	1		T15	351		T24	79		T31	1066
all_values[4]	auto[0]	auto[0]	1157	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	510	1		T2	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	220696	1		T15	351		T24	79		T31	986
all_values[4]	auto[1]	auto[1]	106269	1		T15	351		T24	79		T31	533
all_values[5]	auto[0]	auto[0]	1546	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	137	1		T5	1		T20	1		T32	1
all_values[5]	auto[1]	auto[0]	326887	1		T15	702		T24	158		T31	1519
all_values[5]	auto[1]	auto[1]	62	1		T227	1		T326	1		T327	1