Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	233187	1		T1	974		T2	494		T3	1862
auto[FlashEraseBank]	263136	1		T2	505		T3	1725		T4	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	245715	1		T1	492		T2	999		T3	1450
auto[FlashOpProgram]	231886	1		T1	241		T3	2137		T4	2
auto[FlashOpErase]	14722	1		T1	241		T17	6		T18	11
auto[FlashOpInvalid]	4000	1		T58	200		T81	200		T127	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	245715	1		T1	492		T2	999		T3	1450
op[FlashOpProgram]	231886	1		T1	241		T3	2137		T4	2
op[FlashOpErase]	14722	1		T1	241		T17	6		T18	11
read_erase_read	555	1		T18	2		T36	2		T133	20
read_prog_read	864	1		T3	12		T4	1		T20	11

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	357275	1		T2	739		T3	3018		T4	4
auto[FlashPartInfo]	135598	1		T1	974		T2	253		T3	556
auto[FlashPartInfo1]	674	1		T2	4		T3	1		T5	1
auto[FlashPartInfo2]	2776	1		T2	3		T3	12		T5	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	173742	1		T2	739		T3	1127		T4	2
auto[FlashPartData]	auto[FlashOpProgram]	176006	1		T3	1891		T4	2		T20	1788
auto[FlashPartData]	auto[FlashOpErase]	3603	1		T38	1		T58	98		T53	28
auto[FlashPartData]	auto[FlashOpInvalid]	3924	1		T58	196		T81	194		T127	196
auto[FlashPartInfo]	auto[FlashOpRead]	69560	1		T1	492		T2	253		T3	316
auto[FlashPartInfo]	auto[FlashOpProgram]	54886	1		T1	241		T3	240		T17	448
auto[FlashPartInfo]	auto[FlashOpErase]	11092	1		T1	241		T17	6		T18	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	60	1		T58	4		T81	6		T388	4
auto[FlashPartInfo1]	auto[FlashOpRead]	503	1		T2	4		T3	1		T5	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T108	32		T137	1		T284	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T137	1		T120	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T137	2		T120	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1910	1		T2	3		T3	6		T5	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	829	1		T3	6		T20	7		T42	5
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T127	2		T133	1		T128	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T127	4		T389	2		T137	4