Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28471	1		T1	460		T29	4		T38	4
auto[1]	35	1		T22	1		T194	1		T196	8
auto[2]	56	1		T53	4		T70	12		T390	1
auto[3]	258	1		T3	2		T25	1		T33	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7201	1		T1	115		T3	1		T29	1
evic_idx[1]	7215	1		T1	115		T3	1		T29	1
evic_idx[2]	7206	1		T1	115		T29	1		T38	1
evic_idx[3]	7198	1		T1	115		T29	1		T38	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28010	1		T1	460		T38	4		T55	448
evic_op[2]	290	1		T3	2		T29	4		T22	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6938	1		T1	115		T38	1		T55	112
evic_idx[0]	evic_op[1]	auto[1]	8	1		T196	4		T301	1		T391	3
evic_idx[0]	evic_op[1]	auto[2]	5	1		T301	2		T392	1		T393	2
evic_idx[0]	evic_op[1]	auto[3]	53	1		T133	1		T128	5		T134	1
evic_idx[0]	evic_op[2]	auto[0]	52	1		T29	1		T157	7		T249	5
evic_idx[0]	evic_op[2]	auto[1]	1	1		T394	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T395	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T3	1		T390	1		T106	1
evic_idx[1]	evic_op[1]	auto[0]	6941	1		T1	115		T38	1		T55	112
evic_idx[1]	evic_op[1]	auto[1]	4	1		T196	2		T301	1		T391	1
evic_idx[1]	evic_op[1]	auto[2]	4	1		T301	1		T392	2		T393	1
evic_idx[1]	evic_op[1]	auto[3]	53	1		T133	2		T128	3		T134	3
evic_idx[1]	evic_op[2]	auto[0]	57	1		T29	1		T157	7		T396	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T22	1		T194	1		T82	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T395	1		T397	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	19	1		T3	1		T25	1		T185	1
evic_idx[2]	evic_op[1]	auto[0]	6938	1		T1	115		T38	1		T55	112
evic_idx[2]	evic_op[1]	auto[1]	4	1		T196	1		T301	1		T391	1
evic_idx[2]	evic_op[1]	auto[2]	9	1		T196	1		T301	1		T392	4
evic_idx[2]	evic_op[1]	auto[3]	52	1		T133	1		T128	2		T134	4
evic_idx[2]	evic_op[2]	auto[0]	55	1		T29	1		T157	7		T398	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T399	1		T397	1		T400	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T390	1		T401	1		T402	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T33	1		T34	1		T403	1
evic_idx[3]	evic_op[1]	auto[0]	6938	1		T1	115		T38	1		T55	112
evic_idx[3]	evic_op[1]	auto[1]	6	1		T196	1		T301	1		T391	2
evic_idx[3]	evic_op[1]	auto[2]	9	1		T301	2		T392	3		T404	2
evic_idx[3]	evic_op[1]	auto[3]	48	1		T133	1		T128	4		T134	2
evic_idx[3]	evic_op[2]	auto[0]	52	1		T29	1		T157	7		T249	5
evic_idx[3]	evic_op[2]	auto[1]	3	1		T400	1		T394	1		T405	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T406	1		T407	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	10	1		T252	1		T395	1		T408	1