Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	31677	1		T333	1756		T334	14430		T335	15491
rd_lvl[2]	39343	1		T256	2626		T333	977		T334	10626
rd_lvl[3]	15432	1		T256	2093		T333	363		T336	1166
rd_lvl[4]	36614	1		T256	1105		T333	497		T337	1336
rd_lvl[5]	10712	1		T256	1735		T333	275		T337	478
rd_lvl[6]	19452	1		T123	2773		T256	2820		T338	729
rd_lvl[7]	5903	1		T31	442		T123	274		T339	105
rd_lvl[8]	8501	1		T31	368		T339	31		T340	894
rd_lvl[9]	3711	1		T31	176		T339	2		T340	217
rd_lvl[10]	5997	1		T31	79		T333	124		T341	155
rd_lvl[11]	2458	1		T15	253		T304	45		T340	63
rd_lvl[12]	4704	1		T15	60		T304	15		T341	81
rd_lvl[13]	4602	1		T15	1		T199	206		T333	1
rd_lvl[14]	8581	1		T15	37		T24	57		T199	81
rd_lvl[15]	4902	1		T24	20		T30	626		T299	586