Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	328632	1		T1	1		T2	2		T3	2
all_pins[1]	328632	1		T1	1		T2	2		T3	2
all_pins[2]	328632	1		T1	1		T2	2		T3	2
all_pins[3]	328632	1		T1	1		T2	2		T3	2
all_pins[4]	328632	1		T1	1		T2	2		T3	2
all_pins[5]	328632	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1636431	1		T1	6		T2	12		T3	12
values[0x1]	335361	1		T15	702		T24	162		T31	1655
transitions[0x0=>0x1]	295969	1		T15	702		T24	158		T31	1518
transitions[0x1=>0x0]	295956	1		T15	702		T24	158		T31	1518

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	328472	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	160	1		T227	3		T228	4		T229	3
all_pins[0]	transitions[0x0=>0x1]	70	1		T227	1		T228	2		T229	3
all_pins[0]	transitions[0x1=>0x0]	70	1		T227	4		T229	1		T325	1
all_pins[1]	values[0x0]	328472	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	160	1		T227	6		T228	2		T229	1
all_pins[1]	transitions[0x0=>0x1]	137	1		T227	5		T228	2		T325	1
all_pins[1]	transitions[0x1=>0x0]	6475	1		T24	2		T30	1050		T299	999
all_pins[2]	values[0x0]	322134	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	6498	1		T24	2		T30	1050		T299	999
all_pins[2]	transitions[0x0=>0x1]	42	1		T227	1		T228	1		T229	1
all_pins[2]	transitions[0x1=>0x0]	203053	1		T15	351		T24	77		T31	1065
all_pins[3]	values[0x0]	119123	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	209509	1		T15	351		T24	79		T31	1065
all_pins[3]	transitions[0x0=>0x1]	176732	1		T15	351		T24	77		T31	928
all_pins[3]	transitions[0x1=>0x0]	86195	1		T15	351		T24	79		T31	453
all_pins[4]	values[0x0]	209660	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	118972	1		T15	351		T24	81		T31	590
all_pins[4]	transitions[0x0=>0x1]	118959	1		T15	351		T24	81		T31	590
all_pins[4]	transitions[0x1=>0x0]	49	1		T327	1		T329	2		T331	3
all_pins[5]	values[0x0]	328570	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	62	1		T227	1		T326	1		T327	1
all_pins[5]	transitions[0x0=>0x1]	29	1		T227	1		T329	3		T331	1
all_pins[5]	transitions[0x1=>0x0]	114	1		T227	2		T228	3		T229	2