| T1079 |
/workspace/coverage/default/6.flash_ctrl_smoke.1236326866 |
|
|
Jun 25 07:02:12 PM PDT 24 |
Jun 25 07:03:51 PM PDT 24 |
519739900 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4283281412 |
|
|
Jun 25 07:03:19 PM PDT 24 |
Jun 25 07:05:55 PM PDT 24 |
5975229200 ps |
| T1081 |
/workspace/coverage/default/3.flash_ctrl_mp_regions.2776685654 |
|
|
Jun 25 07:00:47 PM PDT 24 |
Jun 25 07:06:49 PM PDT 24 |
95012469400 ps |
| T1082 |
/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3920220267 |
|
|
Jun 25 07:07:59 PM PDT 24 |
Jun 25 07:08:30 PM PDT 24 |
281479600 ps |
| T1083 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.1823090985 |
|
|
Jun 25 07:04:56 PM PDT 24 |
Jun 25 07:05:10 PM PDT 24 |
18481500 ps |
| T1084 |
/workspace/coverage/default/6.flash_ctrl_prog_reset.3025931486 |
|
|
Jun 25 07:02:32 PM PDT 24 |
Jun 25 07:02:47 PM PDT 24 |
31067000 ps |
| T1085 |
/workspace/coverage/default/12.flash_ctrl_otp_reset.3018559729 |
|
|
Jun 25 07:04:30 PM PDT 24 |
Jun 25 07:06:48 PM PDT 24 |
147744000 ps |
| T1086 |
/workspace/coverage/default/22.flash_ctrl_sec_info_access.3029721758 |
|
|
Jun 25 07:07:16 PM PDT 24 |
Jun 25 07:08:45 PM PDT 24 |
843310100 ps |
| T1087 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.4113891199 |
|
|
Jun 25 07:03:49 PM PDT 24 |
Jun 25 07:10:20 PM PDT 24 |
4261315300 ps |
| T1088 |
/workspace/coverage/default/0.flash_ctrl_phy_arb.4068527043 |
|
|
Jun 25 06:59:17 PM PDT 24 |
Jun 25 07:02:49 PM PDT 24 |
2890804300 ps |
| T1089 |
/workspace/coverage/default/8.flash_ctrl_re_evict.3997668888 |
|
|
Jun 25 07:03:20 PM PDT 24 |
Jun 25 07:03:57 PM PDT 24 |
206966900 ps |
| T1090 |
/workspace/coverage/default/5.flash_ctrl_wo.1128387251 |
|
|
Jun 25 07:02:03 PM PDT 24 |
Jun 25 07:05:10 PM PDT 24 |
2011974100 ps |
| T1091 |
/workspace/coverage/default/3.flash_ctrl_ro_serr.2414240778 |
|
|
Jun 25 07:00:52 PM PDT 24 |
Jun 25 07:03:13 PM PDT 24 |
1026397500 ps |
| T279 |
/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2722931272 |
|
|
Jun 25 07:01:56 PM PDT 24 |
Jun 25 07:07:15 PM PDT 24 |
10012881700 ps |
| T1092 |
/workspace/coverage/default/10.flash_ctrl_alert_test.437505923 |
|
|
Jun 25 07:04:14 PM PDT 24 |
Jun 25 07:04:30 PM PDT 24 |
21842700 ps |
| T1093 |
/workspace/coverage/default/35.flash_ctrl_otp_reset.2326159216 |
|
|
Jun 25 07:08:55 PM PDT 24 |
Jun 25 07:11:26 PM PDT 24 |
40790800 ps |
| T1094 |
/workspace/coverage/default/5.flash_ctrl_intr_rd.509238210 |
|
|
Jun 25 07:02:11 PM PDT 24 |
Jun 25 07:04:34 PM PDT 24 |
720614200 ps |
| T1095 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.1329512029 |
|
|
Jun 25 07:10:19 PM PDT 24 |
Jun 25 07:12:34 PM PDT 24 |
37332600 ps |
| T318 |
/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.4053025961 |
|
|
Jun 25 07:02:32 PM PDT 24 |
Jun 25 07:04:10 PM PDT 24 |
10011793700 ps |
| T1096 |
/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.468328918 |
|
|
Jun 25 07:06:08 PM PDT 24 |
Jun 25 07:07:15 PM PDT 24 |
15117700 ps |
| T1097 |
/workspace/coverage/default/0.flash_ctrl_smoke.3813876357 |
|
|
Jun 25 06:59:14 PM PDT 24 |
Jun 25 07:00:33 PM PDT 24 |
89132000 ps |
| T1098 |
/workspace/coverage/default/37.flash_ctrl_connect.3481372208 |
|
|
Jun 25 07:09:07 PM PDT 24 |
Jun 25 07:09:42 PM PDT 24 |
24515700 ps |
| T1099 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.855155177 |
|
|
Jun 25 07:04:24 PM PDT 24 |
Jun 25 07:04:39 PM PDT 24 |
14942300 ps |
| T1100 |
/workspace/coverage/default/8.flash_ctrl_rw_evict.424044833 |
|
|
Jun 25 07:03:20 PM PDT 24 |
Jun 25 07:03:54 PM PDT 24 |
32191600 ps |
| T1101 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.2549235484 |
|
|
Jun 25 07:05:16 PM PDT 24 |
Jun 25 07:09:33 PM PDT 24 |
8461066000 ps |
| T1102 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.231349363 |
|
|
Jun 25 07:01:28 PM PDT 24 |
Jun 25 07:42:17 PM PDT 24 |
635276000 ps |
| T1103 |
/workspace/coverage/default/1.flash_ctrl_otp_reset.989249541 |
|
|
Jun 25 06:59:38 PM PDT 24 |
Jun 25 07:01:54 PM PDT 24 |
39448700 ps |
| T1104 |
/workspace/coverage/default/5.flash_ctrl_invalid_op.764647198 |
|
|
Jun 25 07:02:02 PM PDT 24 |
Jun 25 07:03:06 PM PDT 24 |
1975309800 ps |
| T1105 |
/workspace/coverage/default/6.flash_ctrl_mp_regions.3534579424 |
|
|
Jun 25 07:02:20 PM PDT 24 |
Jun 25 07:06:04 PM PDT 24 |
2156610800 ps |
| T1106 |
/workspace/coverage/default/33.flash_ctrl_rw_evict.2792125339 |
|
|
Jun 25 07:08:50 PM PDT 24 |
Jun 25 07:09:33 PM PDT 24 |
29263800 ps |
| T1107 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.3667984289 |
|
|
Jun 25 06:59:45 PM PDT 24 |
Jun 25 07:01:42 PM PDT 24 |
2101850200 ps |
| T105 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.2690548802 |
|
|
Jun 25 07:01:06 PM PDT 24 |
Jun 25 08:24:24 PM PDT 24 |
7484476400 ps |
| T1108 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.3017474545 |
|
|
Jun 25 06:59:52 PM PDT 24 |
Jun 25 07:00:26 PM PDT 24 |
30959900 ps |
| T1109 |
/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3127305728 |
|
|
Jun 25 07:04:57 PM PDT 24 |
Jun 25 07:05:27 PM PDT 24 |
39570500 ps |
| T1110 |
/workspace/coverage/default/31.flash_ctrl_otp_reset.877114495 |
|
|
Jun 25 07:08:27 PM PDT 24 |
Jun 25 07:10:44 PM PDT 24 |
140386200 ps |
| T1111 |
/workspace/coverage/default/46.flash_ctrl_smoke.1092810208 |
|
|
Jun 25 07:09:57 PM PDT 24 |
Jun 25 07:11:38 PM PDT 24 |
18644600 ps |
| T1112 |
/workspace/coverage/default/15.flash_ctrl_rand_ops.3800016804 |
|
|
Jun 25 07:05:19 PM PDT 24 |
Jun 25 07:25:02 PM PDT 24 |
260255700 ps |
| T1113 |
/workspace/coverage/default/0.flash_ctrl_intr_rd.1405881748 |
|
|
Jun 25 06:59:37 PM PDT 24 |
Jun 25 07:02:30 PM PDT 24 |
2580587000 ps |
| T1114 |
/workspace/coverage/default/64.flash_ctrl_connect.3319362411 |
|
|
Jun 25 07:10:26 PM PDT 24 |
Jun 25 07:10:45 PM PDT 24 |
47745700 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2239633746 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
94527300 ps |
| T1115 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2009590072 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
13098000 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2765212727 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:20 PM PDT 24 |
206434600 ps |
| T60 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3683123095 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:26:44 PM PDT 24 |
702251700 ps |
| T61 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3867218199 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
206520500 ps |
| T203 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1063264392 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:32 PM PDT 24 |
183861700 ps |
| T217 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.262941739 |
|
|
Jun 25 07:20:20 PM PDT 24 |
Jun 25 07:20:43 PM PDT 24 |
55808300 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1261714708 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:27:59 PM PDT 24 |
876988400 ps |
| T227 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3441959424 |
|
|
Jun 25 07:20:52 PM PDT 24 |
Jun 25 07:21:07 PM PDT 24 |
29622000 ps |
| T216 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2198906154 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:26:47 PM PDT 24 |
1682162900 ps |
| T324 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2911274690 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:21:09 PM PDT 24 |
1319450700 ps |
| T225 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2656657903 |
|
|
Jun 25 07:19:22 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
26955600 ps |
| T228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2130625473 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
44384000 ps |
| T229 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2497357937 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
17461900 ps |
| T226 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.453317877 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:30 PM PDT 24 |
134588800 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1956119168 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:32:38 PM PDT 24 |
807473400 ps |
| T257 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.681059968 |
|
|
Jun 25 07:20:07 PM PDT 24 |
Jun 25 07:26:46 PM PDT 24 |
446402300 ps |
| T236 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.377054344 |
|
|
Jun 25 07:20:29 PM PDT 24 |
Jun 25 07:28:18 PM PDT 24 |
332573700 ps |
| T235 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1183903144 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
84023600 ps |
| T270 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3661364938 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:55 PM PDT 24 |
157831800 ps |
| T325 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3601851718 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:26 PM PDT 24 |
16600500 ps |
| T240 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3113680650 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:35:29 PM PDT 24 |
693390900 ps |
| T271 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3234237044 |
|
|
Jun 25 07:20:10 PM PDT 24 |
Jun 25 07:20:28 PM PDT 24 |
46317400 ps |
| T230 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1862775914 |
|
|
Jun 25 07:20:17 PM PDT 24 |
Jun 25 07:20:40 PM PDT 24 |
37265800 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.293718258 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
161031700 ps |
| T1116 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1081870104 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
38436900 ps |
| T326 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1669540757 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:20:55 PM PDT 24 |
23803800 ps |
| T327 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1334805707 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:44 PM PDT 24 |
31829900 ps |
| T1117 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.3092299460 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:15 PM PDT 24 |
29067900 ps |
| T1118 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1521005562 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:46 PM PDT 24 |
15243300 ps |
| T241 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3602688535 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:21:00 PM PDT 24 |
88389200 ps |
| T328 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3297689361 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
56147800 ps |
| T1119 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3556477269 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:33 PM PDT 24 |
23104200 ps |
| T273 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.421866927 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
95545300 ps |
| T274 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1286509334 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
123131100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.246551172 |
|
|
Jun 25 07:20:16 PM PDT 24 |
Jun 25 07:20:36 PM PDT 24 |
23990500 ps |
| T329 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2094330551 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:23 PM PDT 24 |
15574100 ps |
| T234 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.478714157 |
|
|
Jun 25 07:20:07 PM PDT 24 |
Jun 25 07:32:54 PM PDT 24 |
393497000 ps |
| T1121 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1951577261 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:44 PM PDT 24 |
25771500 ps |
| T1122 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.967895046 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
3954389900 ps |
| T330 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.497178907 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:27 PM PDT 24 |
129417000 ps |
| T242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4186497996 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:32:59 PM PDT 24 |
2615072000 ps |
| T1123 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2463323429 |
|
|
Jun 25 07:20:09 PM PDT 24 |
Jun 25 07:20:28 PM PDT 24 |
154942600 ps |
| T1124 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.4248311294 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:20:55 PM PDT 24 |
27017300 ps |
| T1125 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1867867560 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:21:21 PM PDT 24 |
2197709100 ps |
| T231 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3128918240 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:25 PM PDT 24 |
38335700 ps |
| T260 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2767862327 |
|
|
Jun 25 07:19:22 PM PDT 24 |
Jun 25 07:19:38 PM PDT 24 |
52024800 ps |
| T259 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.285203665 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:18 PM PDT 24 |
15517400 ps |
| T1126 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.980102526 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
470468800 ps |
| T288 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3906049921 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:20:04 PM PDT 24 |
431527400 ps |
| T1127 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2174245739 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:26:00 PM PDT 24 |
3377492600 ps |
| T331 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3267636005 |
|
|
Jun 25 07:21:09 PM PDT 24 |
Jun 25 07:21:25 PM PDT 24 |
16237000 ps |
| T1128 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3195274331 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:24 PM PDT 24 |
24594800 ps |
| T1129 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2024018308 |
|
|
Jun 25 07:20:32 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
14778700 ps |
| T237 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3259396206 |
|
|
Jun 25 07:20:33 PM PDT 24 |
Jun 25 07:20:53 PM PDT 24 |
62251400 ps |
| T332 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.344680530 |
|
|
Jun 25 07:20:53 PM PDT 24 |
Jun 25 07:21:08 PM PDT 24 |
123601200 ps |
| T1130 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1743886376 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
11927000 ps |
| T1131 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.364245208 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
31105700 ps |
| T1132 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1152391815 |
|
|
Jun 25 07:21:09 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
54051900 ps |
| T1133 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2160089839 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:26 PM PDT 24 |
169655300 ps |
| T1134 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2904796486 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:26 PM PDT 24 |
17130500 ps |
| T220 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1541418183 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
60398900 ps |
| T1135 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1322973575 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:59 PM PDT 24 |
223506700 ps |
| T1136 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3917680129 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:23 PM PDT 24 |
51573700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.933227237 |
|
|
Jun 25 07:20:10 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
12414000 ps |
| T1138 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.290622783 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:41 PM PDT 24 |
17844900 ps |
| T1139 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3683986714 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:35 PM PDT 24 |
21208700 ps |
| T1140 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1443436201 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:17 PM PDT 24 |
169993300 ps |
| T239 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.869723216 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:27:58 PM PDT 24 |
4172730400 ps |
| T1141 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.362202288 |
|
|
Jun 25 07:20:10 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
13992800 ps |
| T1142 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2566811761 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:33 PM PDT 24 |
56809800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.341810413 |
|
|
Jun 25 07:20:16 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
79706100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3040326839 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:20:16 PM PDT 24 |
80169800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.833819318 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:19:43 PM PDT 24 |
14218100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.4182493571 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
26942500 ps |
| T289 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2031023271 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
363804500 ps |
| T232 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2408790763 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:32 PM PDT 24 |
99401900 ps |
| T1147 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.744115234 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:36 PM PDT 24 |
25054300 ps |
| T1148 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.460070346 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:30 PM PDT 24 |
66567200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3555058049 |
|
|
Jun 25 07:21:09 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
28853400 ps |
| T1150 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4157952269 |
|
|
Jun 25 07:19:21 PM PDT 24 |
Jun 25 07:19:36 PM PDT 24 |
24924300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1497885649 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:44 PM PDT 24 |
119270700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2321565148 |
|
|
Jun 25 07:21:12 PM PDT 24 |
Jun 25 07:21:27 PM PDT 24 |
19120300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2545111673 |
|
|
Jun 25 07:20:44 PM PDT 24 |
Jun 25 07:20:59 PM PDT 24 |
16280400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.326170643 |
|
|
Jun 25 07:20:33 PM PDT 24 |
Jun 25 07:20:54 PM PDT 24 |
101251000 ps |
| T1155 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2688903755 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:31 PM PDT 24 |
14373400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3823734112 |
|
|
Jun 25 07:20:43 PM PDT 24 |
Jun 25 07:20:58 PM PDT 24 |
167397700 ps |
| T1157 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1276048640 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:46 PM PDT 24 |
158003700 ps |
| T290 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3537165481 |
|
|
Jun 25 07:20:31 PM PDT 24 |
Jun 25 07:20:52 PM PDT 24 |
144367200 ps |
| T1158 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2596505282 |
|
|
Jun 25 07:20:51 PM PDT 24 |
Jun 25 07:21:06 PM PDT 24 |
15382900 ps |
| T233 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.704114847 |
|
|
Jun 25 07:20:16 PM PDT 24 |
Jun 25 07:20:38 PM PDT 24 |
70496700 ps |
| T1159 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3281926973 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:20:59 PM PDT 24 |
19558800 ps |
| T1160 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.296413855 |
|
|
Jun 25 07:20:02 PM PDT 24 |
Jun 25 07:20:40 PM PDT 24 |
897349100 ps |
| T247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2289177578 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:27:16 PM PDT 24 |
737977100 ps |
| T291 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2611381501 |
|
|
Jun 25 07:19:27 PM PDT 24 |
Jun 25 07:19:46 PM PDT 24 |
79683300 ps |
| T348 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2929769568 |
|
|
Jun 25 07:20:31 PM PDT 24 |
Jun 25 07:36:23 PM PDT 24 |
971359400 ps |
| T243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3757182166 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:35:50 PM PDT 24 |
534127900 ps |
| T292 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1907557563 |
|
|
Jun 25 07:19:22 PM PDT 24 |
Jun 25 07:19:42 PM PDT 24 |
142067900 ps |
| T1161 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1963170997 |
|
|
Jun 25 07:20:19 PM PDT 24 |
Jun 25 07:20:38 PM PDT 24 |
48982000 ps |
| T221 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1544487644 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:19:48 PM PDT 24 |
103870100 ps |
| T1162 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1951795395 |
|
|
Jun 25 07:19:25 PM PDT 24 |
Jun 25 07:19:41 PM PDT 24 |
27358800 ps |
| T1163 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.428501691 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
41974900 ps |
| T1164 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1073611253 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:24 PM PDT 24 |
17539000 ps |
| T1165 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3128605052 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:41 PM PDT 24 |
1291921200 ps |
| T1166 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1112874589 |
|
|
Jun 25 07:20:54 PM PDT 24 |
Jun 25 07:21:08 PM PDT 24 |
25544200 ps |
| T1167 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.596963670 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:27 PM PDT 24 |
57249700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3377684783 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
15962300 ps |
| T1169 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2812446052 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:20:55 PM PDT 24 |
32477000 ps |
| T261 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1738034259 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
17260700 ps |
| T293 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3096786682 |
|
|
Jun 25 07:20:18 PM PDT 24 |
Jun 25 07:20:41 PM PDT 24 |
891023700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3089588232 |
|
|
Jun 25 07:20:31 PM PDT 24 |
Jun 25 07:20:50 PM PDT 24 |
32208000 ps |
| T1171 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.965141168 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
41313600 ps |
| T351 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.40727460 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:27:47 PM PDT 24 |
356596000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.565547895 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:23 PM PDT 24 |
31161500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.500574399 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:46 PM PDT 24 |
116200300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.100289314 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:20:15 PM PDT 24 |
24013700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.611704626 |
|
|
Jun 25 07:20:53 PM PDT 24 |
Jun 25 07:21:09 PM PDT 24 |
58371800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3136422334 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:20:44 PM PDT 24 |
4777410800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2143867089 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
38789100 ps |
| T294 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3442179779 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:44 PM PDT 24 |
57744200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2839347617 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:19 PM PDT 24 |
513228200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1345286730 |
|
|
Jun 25 07:19:20 PM PDT 24 |
Jun 25 07:19:54 PM PDT 24 |
363003500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2027972639 |
|
|
Jun 25 07:20:16 PM PDT 24 |
Jun 25 07:20:37 PM PDT 24 |
65338600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2023820377 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:42 PM PDT 24 |
17219500 ps |
| T1182 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2440061153 |
|
|
Jun 25 07:20:32 PM PDT 24 |
Jun 25 07:20:55 PM PDT 24 |
176275000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4022658792 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
158189000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3627075455 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:24 PM PDT 24 |
27522000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2206220091 |
|
|
Jun 25 07:20:17 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
115514000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.4260820706 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
21349800 ps |
| T344 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3808756211 |
|
|
Jun 25 07:20:07 PM PDT 24 |
Jun 25 07:20:27 PM PDT 24 |
37407200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.355520938 |
|
|
Jun 25 07:19:21 PM PDT 24 |
Jun 25 07:19:55 PM PDT 24 |
471542800 ps |
| T1188 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.608368356 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
128972100 ps |
| T1189 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1313452235 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:47 PM PDT 24 |
47901500 ps |
| T349 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3706423156 |
|
|
Jun 25 07:20:21 PM PDT 24 |
Jun 25 07:35:36 PM PDT 24 |
492275400 ps |
| T1190 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2916325897 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:20 PM PDT 24 |
42567200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1085731061 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:19:44 PM PDT 24 |
67870000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1482853805 |
|
|
Jun 25 07:21:07 PM PDT 24 |
Jun 25 07:21:23 PM PDT 24 |
17651200 ps |
| T238 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3497257968 |
|
|
Jun 25 07:20:07 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
44255400 ps |
| T244 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3041545966 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:42 PM PDT 24 |
69780500 ps |
| T1193 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.630911874 |
|
|
Jun 25 07:19:21 PM PDT 24 |
Jun 25 07:19:36 PM PDT 24 |
24677100 ps |
| T222 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3754719439 |
|
|
Jun 25 07:20:31 PM PDT 24 |
Jun 25 07:20:54 PM PDT 24 |
166410300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.182529342 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
92775600 ps |
| T1195 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2122006916 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
556887300 ps |
| T1196 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2224234522 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
32971900 ps |
| T1197 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.691124237 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:31 PM PDT 24 |
26975600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3941316715 |
|
|
Jun 25 07:21:09 PM PDT 24 |
Jun 25 07:21:25 PM PDT 24 |
26529100 ps |
| T1199 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.847405440 |
|
|
Jun 25 07:19:26 PM PDT 24 |
Jun 25 07:19:41 PM PDT 24 |
20330900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1696362282 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:24 PM PDT 24 |
17804800 ps |
| T223 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1878275077 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:53 PM PDT 24 |
221724400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.214141797 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
32825100 ps |
| T1202 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.732765992 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:16 PM PDT 24 |
12798900 ps |
| T350 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3349774424 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:28:06 PM PDT 24 |
464845500 ps |
| T295 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3884231940 |
|
|
Jun 25 07:20:32 PM PDT 24 |
Jun 25 07:20:54 PM PDT 24 |
102690900 ps |
| T224 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3248727889 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
262625200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.888231704 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:26 PM PDT 24 |
32984400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.4252933216 |
|
|
Jun 25 07:20:06 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
14121800 ps |
| T1205 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2485866443 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
206293400 ps |
| T1206 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3784973911 |
|
|
Jun 25 07:21:10 PM PDT 24 |
Jun 25 07:21:26 PM PDT 24 |
260200600 ps |
| T296 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1253422734 |
|
|
Jun 25 07:20:10 PM PDT 24 |
Jun 25 07:20:33 PM PDT 24 |
362555500 ps |
| T1207 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1667842082 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:20:16 PM PDT 24 |
65006000 ps |
| T1208 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2876111903 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:35 PM PDT 24 |
56886800 ps |
| T1209 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1262576362 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:23 PM PDT 24 |
14039000 ps |
| T297 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.637414999 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
393936700 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2233269927 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:36 PM PDT 24 |
76640200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.496002166 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
117854000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1685454936 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:17 PM PDT 24 |
136822700 ps |
| T1213 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2217594682 |
|
|
Jun 25 07:20:28 PM PDT 24 |
Jun 25 07:20:43 PM PDT 24 |
46465100 ps |
| T1214 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3850182065 |
|
|
Jun 25 07:20:17 PM PDT 24 |
Jun 25 07:20:38 PM PDT 24 |
99455600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.956163376 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
27338900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.4134809914 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:35 PM PDT 24 |
16411800 ps |
| T1217 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3689710553 |
|
|
Jun 25 07:20:09 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
303353400 ps |
| T1218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.254458960 |
|
|
Jun 25 07:19:26 PM PDT 24 |
Jun 25 07:20:49 PM PDT 24 |
2284707000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2008509545 |
|
|
Jun 25 07:19:25 PM PDT 24 |
Jun 25 07:19:44 PM PDT 24 |
44233200 ps |
| T245 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3031806382 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:25 PM PDT 24 |
54356700 ps |
| T345 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3357771779 |
|
|
Jun 25 07:20:33 PM PDT 24 |
Jun 25 07:33:41 PM PDT 24 |
1603686800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2466842844 |
|
|
Jun 25 07:20:40 PM PDT 24 |
Jun 25 07:20:58 PM PDT 24 |
37667500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.615526447 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:27 PM PDT 24 |
448567700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3763072032 |
|
|
Jun 25 07:20:16 PM PDT 24 |
Jun 25 07:20:35 PM PDT 24 |
31057500 ps |
| T1223 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2541905301 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:47 PM PDT 24 |
33556500 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2371365554 |
|
|
Jun 25 07:19:59 PM PDT 24 |
Jun 25 07:20:21 PM PDT 24 |
78811500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1615222353 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:30 PM PDT 24 |
18906000 ps |
| T1226 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.919592050 |
|
|
Jun 25 07:20:17 PM PDT 24 |
Jun 25 07:20:40 PM PDT 24 |
219506400 ps |
| T298 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3310586365 |
|
|
Jun 25 07:19:22 PM PDT 24 |
Jun 25 07:19:50 PM PDT 24 |
137855700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2632293841 |
|
|
Jun 25 07:20:17 PM PDT 24 |
Jun 25 07:20:37 PM PDT 24 |
35720300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2969588060 |
|
|
Jun 25 07:20:09 PM PDT 24 |
Jun 25 07:20:31 PM PDT 24 |
62004500 ps |
| T1229 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2803530170 |
|
|
Jun 25 07:20:54 PM PDT 24 |
Jun 25 07:21:09 PM PDT 24 |
24877500 ps |
| T262 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3049778263 |
|
|
Jun 25 07:20:01 PM PDT 24 |
Jun 25 07:20:17 PM PDT 24 |
35618500 ps |
| T346 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3016662902 |
|
|
Jun 25 07:19:24 PM PDT 24 |
Jun 25 07:34:39 PM PDT 24 |
1339867300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1809574105 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:28 PM PDT 24 |
56459200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1072241695 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
15374600 ps |
| T1232 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2568222706 |
|
|
Jun 25 07:21:08 PM PDT 24 |
Jun 25 07:21:23 PM PDT 24 |
78677000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1338566336 |
|
|
Jun 25 07:20:19 PM PDT 24 |
Jun 25 07:20:39 PM PDT 24 |
42248300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1838187632 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:42 PM PDT 24 |
15165800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4248036015 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
87263400 ps |
| T1236 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2122692911 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
117430700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2110577369 |
|
|
Jun 25 07:19:21 PM PDT 24 |
Jun 25 07:20:08 PM PDT 24 |
85452100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1900221718 |
|
|
Jun 25 07:20:13 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
46099100 ps |
| T1239 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1025846119 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
53720700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.250468823 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:29 PM PDT 24 |
27648400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3019146242 |
|
|
Jun 25 07:20:08 PM PDT 24 |
Jun 25 07:20:28 PM PDT 24 |
136480100 ps |
| T1242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1475960199 |
|
|
Jun 25 07:19:37 PM PDT 24 |
Jun 25 07:20:10 PM PDT 24 |
75349000 ps |
| T1243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.252220894 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
30746800 ps |
| T347 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.35021909 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:28:12 PM PDT 24 |
415341800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1147750033 |
|
|
Jun 25 07:20:00 PM PDT 24 |
Jun 25 07:21:05 PM PDT 24 |
2618735200 ps |
| T1245 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2913898364 |
|
|
Jun 25 07:20:04 PM PDT 24 |
Jun 25 07:20:22 PM PDT 24 |
102557200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2421430137 |
|
|
Jun 25 07:20:11 PM PDT 24 |
Jun 25 07:20:28 PM PDT 24 |
52278100 ps |
| T263 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2883565788 |
|
|
Jun 25 07:19:23 PM PDT 24 |
Jun 25 07:19:40 PM PDT 24 |
75424500 ps |
| T1247 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3770135864 |
|
|
Jun 25 07:20:12 PM PDT 24 |
Jun 25 07:20:34 PM PDT 24 |
73830800 ps |
| T1248 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1864940148 |
|
|
Jun 25 07:20:14 PM PDT 24 |
Jun 25 07:20:35 PM PDT 24 |
110785200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2213837881 |
|
|
Jun 25 07:20:30 PM PDT 24 |
Jun 25 07:20:53 PM PDT 24 |
56121300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2429607100 |
|
|
Jun 25 07:20:05 PM PDT 24 |
Jun 25 07:20:26 PM PDT 24 |
46500600 ps |