Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	308572	1		T1	1403		T2	1		T3	1
all_values[1]	308572	1		T1	1403		T2	1		T3	1
all_values[2]	308572	1		T1	1403		T2	1		T3	1
all_values[3]	308572	1		T1	1403		T2	1		T3	1
all_values[4]	308572	1		T1	1403		T2	1		T3	1
all_values[5]	308572	1		T1	1403		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	623355	1		T1	2806		T2	6		T3	6
auto[1]	1228077	1		T1	5612		T6	27520		T33	13248

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	905454	1		T1	4210		T2	4		T3	4
auto[1]	945978	1		T1	4208		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	308420	1		T1	1403		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	152	1		T236	3		T237	2		T238	2
all_values[1]	auto[0]	auto[1]	308409	1		T1	1403		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	163	1		T236	6		T237	7		T238	3
all_values[2]	auto[0]	auto[0]	1578	1		T2	1		T3	1		T12	1
all_values[2]	auto[0]	auto[1]	57	1		T236	1		T237	1		T238	2
all_values[2]	auto[1]	auto[0]	306865	1		T1	1403		T6	6880		T33	3312
all_values[2]	auto[1]	auto[1]	72	1		T236	4		T237	2		T325	3
all_values[3]	auto[0]	auto[0]	1578	1		T2	1		T3	1		T12	1
all_values[3]	auto[0]	auto[1]	66	1		T236	3		T237	1		T327	3
all_values[3]	auto[1]	auto[0]	82906	1		T1	1403		T6	1720		T33	1656
all_values[3]	auto[1]	auto[1]	224022	1		T6	5160		T33	1656		T34	86
all_values[4]	auto[0]	auto[0]	1113	1		T2	1		T3	1		T12	1
all_values[4]	auto[0]	auto[1]	510	1		T4	1		T5	1		T24	15
all_values[4]	auto[1]	auto[0]	203027	1		T1	1		T6	5160		T33	1656
all_values[4]	auto[1]	auto[1]	103922	1		T1	1402		T6	1720		T33	1656
all_values[5]	auto[0]	auto[0]	1494	1		T2	1		T3	1		T12	1
all_values[5]	auto[0]	auto[1]	130	1		T25	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	306893	1		T1	1403		T6	6880		T33	3312
all_values[5]	auto[1]	auto[1]	55	1		T236	2		T237	1		T328	1