Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226110	1		T1	530		T12	1		T4	216
auto[FlashEraseBank]	259819	1		T1	872		T2	1		T20	6

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	246571	1		T12	1		T4	14		T20	11
auto[FlashOpProgram]	219579	1		T1	1402		T2	1		T4	192
auto[FlashOpErase]	15779	1		T4	10		T21	261		T24	5
auto[FlashOpInvalid]	4000	1		T132	200		T257	200		T284	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	246571	1		T12	1		T4	14		T20	11
op[FlashOpProgram]	219579	1		T1	1402		T2	1		T4	192
op[FlashOpErase]	15779	1		T4	10		T21	261		T24	5
read_erase_read	537	1		T4	1		T24	1		T28	13
read_prog_read	736	1		T20	1		T5	1		T24	4

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	350154	1		T1	1161		T2	1		T5	5
auto[FlashPartInfo]	132139	1		T1	235		T12	1		T4	216
auto[FlashPartInfo1]	841	1		T7	1		T41	7		T57	64
auto[FlashPartInfo2]	2795	1		T1	6		T20	1		T23	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	177704	1		T5	4		T24	20		T23	4
auto[FlashPartData]	auto[FlashOpProgram]	165010	1		T1	1161		T2	1		T5	1
auto[FlashPartData]	auto[FlashOpErase]	3538	1		T24	5		T28	5		T41	1
auto[FlashPartData]	auto[FlashOpInvalid]	3902	1		T132	194		T257	196		T284	198
auto[FlashPartInfo]	auto[FlashOpRead]	66368	1		T12	1		T4	14		T20	10
auto[FlashPartInfo]	auto[FlashOpProgram]	53486	1		T1	235		T4	192		T20	1
auto[FlashPartInfo]	auto[FlashOpErase]	12201	1		T4	10		T21	261		T28	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	84	1		T132	6		T257	4		T284	2
auto[FlashPartInfo1]	auto[FlashOpRead]	672	1		T7	1		T41	7		T57	32
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T57	32		T72	1		T134	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T137	1		T419	1		T420	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T419	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1827	1		T20	1		T23	3		T7	17
auto[FlashPartInfo2]	auto[FlashOpProgram]	920	1		T1	6		T23	2		T118	2
auto[FlashPartInfo2]	auto[FlashOpErase]	36	1		T119	4		T145	2		T196	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T147	2		T421	2		T422	2