Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31058	1		T21	544		T82	416		T96	764
auto[1]	41	1		T23	1		T353	8		T354	5
auto[2]	87	1		T23	2		T119	14		T74	8
auto[3]	245	1		T20	1		T28	15		T27	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7853	1		T21	136		T28	5		T82	104
evic_idx[1]	7872	1		T21	136		T23	2		T28	4
evic_idx[2]	7861	1		T21	136		T23	1		T28	3
evic_idx[3]	7845	1		T20	1		T21	136		T28	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30515	1		T21	544		T28	15		T82	416
evic_op[2]	348	1		T20	1		T23	3		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7561	1		T21	136		T82	104		T96	191
evic_idx[0]	evic_op[1]	auto[1]	9	1		T353	1		T354	1		T355	4
evic_idx[0]	evic_op[1]	auto[2]	10	1		T119	4		T353	2		T356	1
evic_idx[0]	evic_op[1]	auto[3]	50	1		T28	5		T119	3		T145	3
evic_idx[0]	evic_op[2]	auto[0]	67	1		T84	1		T120	1		T198	5
evic_idx[0]	evic_op[2]	auto[1]	1	1		T357	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T358	1		T359	1		T360	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T39	1		T184	1		T361	1
evic_idx[1]	evic_op[1]	auto[0]	7564	1		T21	136		T82	104		T96	191
evic_idx[1]	evic_op[1]	auto[1]	11	1		T353	2		T354	1		T355	3
evic_idx[1]	evic_op[1]	auto[2]	10	1		T119	2		T353	1		T362	1
evic_idx[1]	evic_op[1]	auto[3]	50	1		T28	4		T119	3		T145	2
evic_idx[1]	evic_op[2]	auto[0]	73	1		T84	1		T120	1		T198	5
evic_idx[1]	evic_op[2]	auto[1]	2	1		T23	1		T363	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	2	1		T23	1		T364	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	18	1		T27	1		T52	1		T365	1
evic_idx[2]	evic_op[1]	auto[0]	7562	1		T21	136		T82	104		T96	191
evic_idx[2]	evic_op[1]	auto[1]	10	1		T353	3		T354	2		T355	1
evic_idx[2]	evic_op[1]	auto[2]	11	1		T119	4		T353	1		T362	1
evic_idx[2]	evic_op[1]	auto[3]	47	1		T28	3		T119	4		T196	7
evic_idx[2]	evic_op[2]	auto[0]	70	1		T84	1		T120	1		T198	5
evic_idx[2]	evic_op[2]	auto[1]	1	1		T366	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T23	1		T357	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	16	1		T367	1		T368	1		T211	1
evic_idx[3]	evic_op[1]	auto[0]	7562	1		T21	136		T82	104		T96	191
evic_idx[3]	evic_op[1]	auto[1]	7	1		T353	2		T354	1		T355	1
evic_idx[3]	evic_op[1]	auto[2]	10	1		T119	4		T353	1		T362	2
evic_idx[3]	evic_op[1]	auto[3]	41	1		T28	3		T119	3		T196	5
evic_idx[3]	evic_op[2]	auto[0]	67	1		T84	1		T120	1		T198	5
evic_idx[3]	evic_op[2]	auto[2]	2	1		T361	1		T357	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T20	1		T369	1		T211	1