Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6149	1		T335	2539		T336	1486		T337	2124
rd_lvl[2]	70552	1		T338	11966		T339	11874		T340	11686
rd_lvl[3]	15918	1		T144	4415		T338	393		T339	451
rd_lvl[4]	27291	1		T144	4055		T215	5569		T341	1661
rd_lvl[5]	15503	1		T6	2537		T215	1459		T342	2375
rd_lvl[6]	22060	1		T6	1174		T342	1250		T261	2473
rd_lvl[7]	9433	1		T261	311		T343	1764		T344	467
rd_lvl[8]	13533	1		T345	139		T343	1326		T346	342
rd_lvl[9]	3295	1		T34	68		T345	13		T346	76
rd_lvl[10]	3199	1		T34	13		T346	74		T347	981
rd_lvl[11]	3308	1		T348	710		T349	547		T263	201
rd_lvl[12]	7037	1		T34	5		T308	59		T348	1015
rd_lvl[13]	3085	1		T216	288		T308	17		T350	530
rd_lvl[14]	5590	1		T35	378		T216	585		T350	1021
rd_lvl[15]	2609	1		T33	577		T35	197		T308	1