Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	308572	1		T1	1403		T2	1		T3	1
all_pins[1]	308572	1		T1	1403		T2	1		T3	1
all_pins[2]	308572	1		T1	1403		T2	1		T3	1
all_pins[3]	308572	1		T1	1403		T2	1		T3	1
all_pins[4]	308572	1		T1	1403		T2	1		T3	1
all_pins[5]	308572	1		T1	1403		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1524351	1		T1	7016		T2	6		T3	6
values[0x1]	327081	1		T1	1402		T6	5532		T33	5470
transitions[0x0=>0x1]	295671	1		T1	1402		T6	5431		T33	3312
transitions[0x1=>0x0]	295657	1		T1	1402		T6	5431		T33	3312

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	308420	1		T1	1403		T2	1		T3	1
all_pins[0]	values[0x1]	152	1		T236	3		T237	2		T238	2
all_pins[0]	transitions[0x0=>0x1]	80	1		T236	1		T237	1		T238	1
all_pins[0]	transitions[0x1=>0x0]	91	1		T236	4		T237	6		T238	2
all_pins[1]	values[0x0]	308409	1		T1	1403		T2	1		T3	1
all_pins[1]	values[0x1]	163	1		T236	6		T237	7		T238	3
all_pins[1]	transitions[0x0=>0x1]	128	1		T236	3		T237	6		T238	3
all_pins[1]	transitions[0x1=>0x0]	3680	1		T33	1079		T35	8		T194	752
all_pins[2]	values[0x0]	304857	1		T1	1403		T2	1		T3	1
all_pins[2]	values[0x1]	3715	1		T33	1079		T35	8		T194	752
all_pins[2]	transitions[0x0=>0x1]	48	1		T236	4		T325	1		T326	1
all_pins[2]	transitions[0x1=>0x0]	208598	1		T6	3711		T33	577		T34	86
all_pins[3]	values[0x0]	96307	1		T1	1403		T2	1		T3	1
all_pins[3]	values[0x1]	212265	1		T6	3711		T33	1656		T34	86
all_pins[3]	transitions[0x0=>0x1]	184671	1		T6	3610		T33	577		T34	86
all_pins[3]	transitions[0x1=>0x0]	83137	1		T1	1402		T6	1720		T33	1656
all_pins[4]	values[0x0]	197841	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	110731	1		T1	1402		T6	1821		T33	2735
all_pins[4]	transitions[0x0=>0x1]	110717	1		T1	1402		T6	1821		T33	2735
all_pins[4]	transitions[0x1=>0x0]	41	1		T236	2		T237	1		T328	1
all_pins[5]	values[0x0]	308517	1		T1	1403		T2	1		T3	1
all_pins[5]	values[0x1]	55	1		T236	2		T237	1		T328	1
all_pins[5]	transitions[0x0=>0x1]	27	1		T236	2		T237	1		T370	1
all_pins[5]	transitions[0x1=>0x0]	110	1		T236	3		T237	2		T238	2