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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.33 95.70 93.97 98.31 92.52 98.19 97.38 98.21


Total test records in report: 1247
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T1089 /workspace/coverage/default/46.flash_ctrl_connect.2948066699 Jun 27 05:22:34 PM PDT 24 Jun 27 05:22:48 PM PDT 24 13760300 ps
T1090 /workspace/coverage/default/27.flash_ctrl_alert_test.539217733 Jun 27 05:20:41 PM PDT 24 Jun 27 05:20:56 PM PDT 24 52122900 ps
T1091 /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.2848109926 Jun 27 05:16:07 PM PDT 24 Jun 27 05:16:36 PM PDT 24 27847400 ps
T336 /workspace/coverage/default/26.flash_ctrl_intr_rd.1967903810 Jun 27 05:20:32 PM PDT 24 Jun 27 05:23:36 PM PDT 24 557867500 ps
T1092 /workspace/coverage/default/1.flash_ctrl_otp_reset.2983756617 Jun 27 05:11:34 PM PDT 24 Jun 27 05:13:26 PM PDT 24 133155200 ps
T1093 /workspace/coverage/default/71.flash_ctrl_otp_reset.2192588214 Jun 27 05:22:54 PM PDT 24 Jun 27 05:25:08 PM PDT 24 149970000 ps
T1094 /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.824387965 Jun 27 05:22:01 PM PDT 24 Jun 27 05:24:29 PM PDT 24 8322240500 ps
T1095 /workspace/coverage/default/66.flash_ctrl_connect.1426298208 Jun 27 05:22:56 PM PDT 24 Jun 27 05:23:14 PM PDT 24 75434900 ps
T337 /workspace/coverage/default/28.flash_ctrl_intr_rd.323767783 Jun 27 05:20:33 PM PDT 24 Jun 27 05:23:08 PM PDT 24 1131000400 ps
T1096 /workspace/coverage/default/40.flash_ctrl_otp_reset.422016205 Jun 27 05:21:59 PM PDT 24 Jun 27 05:23:52 PM PDT 24 147972400 ps
T1097 /workspace/coverage/default/5.flash_ctrl_fetch_code.182092669 Jun 27 05:14:06 PM PDT 24 Jun 27 05:14:36 PM PDT 24 351598300 ps
T1098 /workspace/coverage/default/17.flash_ctrl_rand_ops.1567365048 Jun 27 05:18:32 PM PDT 24 Jun 27 05:43:40 PM PDT 24 1537742900 ps
T1099 /workspace/coverage/default/6.flash_ctrl_rand_ops.3558366620 Jun 27 05:14:23 PM PDT 24 Jun 27 05:23:17 PM PDT 24 853148400 ps
T223 /workspace/coverage/default/2.flash_ctrl_wr_intg.1689990577 Jun 27 05:12:03 PM PDT 24 Jun 27 05:12:19 PM PDT 24 83076600 ps
T1100 /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.888058508 Jun 27 05:11:30 PM PDT 24 Jun 27 05:13:15 PM PDT 24 54128300 ps
T1101 /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1778264986 Jun 27 05:21:09 PM PDT 24 Jun 27 05:25:12 PM PDT 24 39553342800 ps
T1102 /workspace/coverage/default/1.flash_ctrl_smoke_hw.2344997008 Jun 27 05:11:32 PM PDT 24 Jun 27 05:12:00 PM PDT 24 14966000 ps
T1103 /workspace/coverage/default/22.flash_ctrl_intr_rd.3139732546 Jun 27 05:19:49 PM PDT 24 Jun 27 05:22:18 PM PDT 24 8090129000 ps
T1104 /workspace/coverage/default/16.flash_ctrl_wo.3462620748 Jun 27 05:18:14 PM PDT 24 Jun 27 05:20:24 PM PDT 24 7010777300 ps
T1105 /workspace/coverage/default/32.flash_ctrl_rw_evict.773738124 Jun 27 05:21:09 PM PDT 24 Jun 27 05:21:42 PM PDT 24 27031800 ps
T45 /workspace/coverage/default/2.flash_ctrl_access_after_disable.2398977555 Jun 27 05:12:05 PM PDT 24 Jun 27 05:12:19 PM PDT 24 13690800 ps
T1106 /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1883804906 Jun 27 05:20:32 PM PDT 24 Jun 27 05:21:04 PM PDT 24 68437200 ps
T1107 /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.82954175 Jun 27 05:14:46 PM PDT 24 Jun 27 05:15:41 PM PDT 24 10035338900 ps
T1108 /workspace/coverage/default/16.flash_ctrl_alert_test.2362943356 Jun 27 05:18:29 PM PDT 24 Jun 27 05:18:44 PM PDT 24 43131700 ps
T1109 /workspace/coverage/default/0.flash_ctrl_rw.3909081734 Jun 27 05:10:50 PM PDT 24 Jun 27 05:21:39 PM PDT 24 15997291400 ps
T1110 /workspace/coverage/default/0.flash_ctrl_intr_wr.2583475636 Jun 27 05:10:51 PM PDT 24 Jun 27 05:11:56 PM PDT 24 7735430100 ps
T1111 /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3048518312 Jun 27 05:13:50 PM PDT 24 Jun 27 05:14:05 PM PDT 24 45655300 ps
T1112 /workspace/coverage/default/49.flash_ctrl_connect.3083087817 Jun 27 05:22:53 PM PDT 24 Jun 27 05:23:11 PM PDT 24 16731800 ps
T1113 /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3933219808 Jun 27 05:18:50 PM PDT 24 Jun 27 05:21:24 PM PDT 24 10011561900 ps
T1114 /workspace/coverage/default/1.flash_ctrl_error_prog_win.3528242169 Jun 27 05:11:30 PM PDT 24 Jun 27 05:27:01 PM PDT 24 2751250000 ps
T387 /workspace/coverage/default/9.flash_ctrl_disable.3104573431 Jun 27 05:16:07 PM PDT 24 Jun 27 05:16:29 PM PDT 24 11647300 ps
T1115 /workspace/coverage/default/1.flash_ctrl_hw_rma.1922472667 Jun 27 05:11:32 PM PDT 24 Jun 27 05:41:57 PM PDT 24 316961320900 ps
T236 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3705628006 Jun 27 05:10:39 PM PDT 24 Jun 27 05:10:54 PM PDT 24 60010800 ps
T237 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2868692617 Jun 27 05:10:33 PM PDT 24 Jun 27 05:10:48 PM PDT 24 14534800 ps
T238 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1208050480 Jun 27 05:08:15 PM PDT 24 Jun 27 05:08:30 PM PDT 24 36193700 ps
T69 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3190014995 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:37 PM PDT 24 344097300 ps
T100 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3725897560 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:43 PM PDT 24 100674600 ps
T70 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.954944547 Jun 27 05:08:16 PM PDT 24 Jun 27 05:15:57 PM PDT 24 689729400 ps
T325 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.761399888 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:32 PM PDT 24 68451100 ps
T328 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.388851934 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:49 PM PDT 24 17108600 ps
T1116 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4040650784 Jun 27 05:08:29 PM PDT 24 Jun 27 05:08:44 PM PDT 24 28556800 ps
T326 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1961203745 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:50 PM PDT 24 60516600 ps
T1117 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1515564563 Jun 27 05:08:16 PM PDT 24 Jun 27 05:08:31 PM PDT 24 16125300 ps
T329 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.800633282 Jun 27 05:09:50 PM PDT 24 Jun 27 05:10:05 PM PDT 24 25582300 ps
T71 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3945514472 Jun 27 05:10:18 PM PDT 24 Jun 27 05:10:36 PM PDT 24 175369600 ps
T227 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3531331086 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:27 PM PDT 24 277953100 ps
T327 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3848371626 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:33 PM PDT 24 60594600 ps
T1118 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3063701336 Jun 27 05:08:16 PM PDT 24 Jun 27 05:08:31 PM PDT 24 19566600 ps
T1119 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1940316700 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:31 PM PDT 24 15509900 ps
T228 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.752484713 Jun 27 05:08:50 PM PDT 24 Jun 27 05:09:08 PM PDT 24 60617100 ps
T101 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.412404904 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:26 PM PDT 24 112399200 ps
T201 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3795160830 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:34 PM PDT 24 123420000 ps
T229 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1514658142 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:45 PM PDT 24 301858100 ps
T225 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2359994329 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:09 PM PDT 24 188109100 ps
T1120 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1900977155 Jun 27 05:09:47 PM PDT 24 Jun 27 05:10:02 PM PDT 24 21005400 ps
T1121 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4212712253 Jun 27 05:09:47 PM PDT 24 Jun 27 05:10:04 PM PDT 24 53067900 ps
T330 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.593217357 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:32 PM PDT 24 18043800 ps
T202 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1998617032 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:35 PM PDT 24 38313900 ps
T231 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2390233854 Jun 27 05:08:51 PM PDT 24 Jun 27 05:09:55 PM PDT 24 1243993100 ps
T1122 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3483829049 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:34 PM PDT 24 22633700 ps
T230 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4134938824 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:06 PM PDT 24 67257800 ps
T252 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.865263772 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:52 PM PDT 24 140012300 ps
T1123 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3205122364 Jun 27 05:09:06 PM PDT 24 Jun 27 05:09:22 PM PDT 24 41275600 ps
T1124 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1618562284 Jun 27 05:10:18 PM PDT 24 Jun 27 05:10:35 PM PDT 24 19803300 ps
T224 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2291600426 Jun 27 05:09:49 PM PDT 24 Jun 27 05:17:26 PM PDT 24 181020700 ps
T1125 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2975400356 Jun 27 05:08:50 PM PDT 24 Jun 27 05:09:08 PM PDT 24 140092200 ps
T276 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1813788198 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:41 PM PDT 24 50366200 ps
T331 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1146775216 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:40 PM PDT 24 14278600 ps
T203 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.57765803 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:35 PM PDT 24 65145200 ps
T1126 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2485996829 Jun 27 05:08:48 PM PDT 24 Jun 27 05:10:08 PM PDT 24 2283461600 ps
T1127 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1365619160 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:06 PM PDT 24 158438400 ps
T204 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1619363070 Jun 27 05:09:49 PM PDT 24 Jun 27 05:17:30 PM PDT 24 473613700 ps
T234 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3156953534 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:38 PM PDT 24 44141800 ps
T235 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1992126725 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:06 PM PDT 24 275152700 ps
T324 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.967900484 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:25 PM PDT 24 491739500 ps
T1128 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.36767904 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:37 PM PDT 24 24258100 ps
T287 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.766585572 Jun 27 05:08:30 PM PDT 24 Jun 27 05:09:10 PM PDT 24 783792100 ps
T288 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3767128208 Jun 27 05:08:49 PM PDT 24 Jun 27 05:09:17 PM PDT 24 39551600 ps
T1129 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.658999209 Jun 27 05:10:17 PM PDT 24 Jun 27 05:10:32 PM PDT 24 16830700 ps
T1130 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2904737429 Jun 27 05:10:17 PM PDT 24 Jun 27 05:10:35 PM PDT 24 13134300 ps
T370 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.16508271 Jun 27 05:08:49 PM PDT 24 Jun 27 05:09:04 PM PDT 24 51777300 ps
T1131 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3906828381 Jun 27 05:08:47 PM PDT 24 Jun 27 05:09:04 PM PDT 24 22123000 ps
T289 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2080488764 Jun 27 05:08:33 PM PDT 24 Jun 27 05:16:20 PM PDT 24 1710148000 ps
T267 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3170107428 Jun 27 05:08:47 PM PDT 24 Jun 27 05:09:02 PM PDT 24 15625300 ps
T277 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1076303890 Jun 27 05:08:30 PM PDT 24 Jun 27 05:09:07 PM PDT 24 2101878100 ps
T290 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1611236327 Jun 27 05:08:38 PM PDT 24 Jun 27 05:09:50 PM PDT 24 2848103100 ps
T278 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1002248437 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:42 PM PDT 24 38456600 ps
T291 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.15045461 Jun 27 05:08:51 PM PDT 24 Jun 27 05:21:21 PM PDT 24 3126528400 ps
T1132 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.881798342 Jun 27 05:08:51 PM PDT 24 Jun 27 05:09:08 PM PDT 24 39842600 ps
T1133 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2110433710 Jun 27 05:10:14 PM PDT 24 Jun 27 05:10:29 PM PDT 24 30636600 ps
T334 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3688507948 Jun 27 05:11:43 PM PDT 24 Jun 27 05:11:57 PM PDT 24 23523300 ps
T255 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2400806521 Jun 27 05:08:38 PM PDT 24 Jun 27 05:16:17 PM PDT 24 794313100 ps
T256 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1624643931 Jun 27 05:08:49 PM PDT 24 Jun 27 05:09:06 PM PDT 24 54098800 ps
T332 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3835542483 Jun 27 05:10:36 PM PDT 24 Jun 27 05:10:51 PM PDT 24 17239500 ps
T292 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3538850609 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:35 PM PDT 24 67922400 ps
T241 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1194214403 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:25 PM PDT 24 86460900 ps
T333 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3728372829 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:49 PM PDT 24 15745600 ps
T1134 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4278217071 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:23 PM PDT 24 16214400 ps
T1135 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1290536465 Jun 27 05:10:17 PM PDT 24 Jun 27 05:10:52 PM PDT 24 128010900 ps
T254 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2737818806 Jun 27 05:10:13 PM PDT 24 Jun 27 05:10:31 PM PDT 24 92851400 ps
T1136 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4199228823 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:34 PM PDT 24 37113800 ps
T248 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2805942092 Jun 27 05:10:20 PM PDT 24 Jun 27 05:17:59 PM PDT 24 692488300 ps
T1137 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1837754773 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:52 PM PDT 24 233398100 ps
T373 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1784509913 Jun 27 05:09:07 PM PDT 24 Jun 27 05:23:52 PM PDT 24 415902800 ps
T1138 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1716073344 Jun 27 05:10:40 PM PDT 24 Jun 27 05:11:01 PM PDT 24 75765600 ps
T1139 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2857185234 Jun 27 05:09:06 PM PDT 24 Jun 27 05:09:21 PM PDT 24 57816600 ps
T1140 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2693812466 Jun 27 05:08:17 PM PDT 24 Jun 27 05:08:31 PM PDT 24 25840500 ps
T232 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1906856861 Jun 27 05:10:18 PM PDT 24 Jun 27 05:10:40 PM PDT 24 59258500 ps
T293 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.490585597 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:43 PM PDT 24 535728200 ps
T1141 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1520817120 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:07 PM PDT 24 65271600 ps
T1142 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.754168309 Jun 27 05:10:33 PM PDT 24 Jun 27 05:10:48 PM PDT 24 184735900 ps
T294 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3079693245 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:34 PM PDT 24 860197700 ps
T295 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2599898552 Jun 27 05:09:25 PM PDT 24 Jun 27 05:17:08 PM PDT 24 1749812200 ps
T1143 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1198744082 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:43 PM PDT 24 16685300 ps
T1144 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1244594982 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:10 PM PDT 24 265109800 ps
T1145 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1189645708 Jun 27 05:10:37 PM PDT 24 Jun 27 05:10:52 PM PDT 24 17685700 ps
T1146 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1544213326 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:51 PM PDT 24 17467100 ps
T1147 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.667662222 Jun 27 05:08:49 PM PDT 24 Jun 27 05:09:37 PM PDT 24 85458700 ps
T1148 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4233106925 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:41 PM PDT 24 24147800 ps
T1149 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4011678873 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:27 PM PDT 24 171015300 ps
T1150 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2555318383 Jun 27 05:08:50 PM PDT 24 Jun 27 05:09:05 PM PDT 24 80394100 ps
T1151 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4172939401 Jun 27 05:10:14 PM PDT 24 Jun 27 05:10:29 PM PDT 24 15651000 ps
T1152 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.660383105 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:51 PM PDT 24 23467300 ps
T296 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1614907823 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:09 PM PDT 24 60208300 ps
T1153 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1785881101 Jun 27 05:08:50 PM PDT 24 Jun 27 05:09:07 PM PDT 24 14277900 ps
T1154 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1246887564 Jun 27 05:10:20 PM PDT 24 Jun 27 05:10:40 PM PDT 24 58345700 ps
T1155 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.468717993 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:36 PM PDT 24 23162800 ps
T374 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4083960509 Jun 27 05:10:17 PM PDT 24 Jun 27 05:25:21 PM PDT 24 3089435100 ps
T1156 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.509265879 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:51 PM PDT 24 114328200 ps
T242 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3600618962 Jun 27 05:10:15 PM PDT 24 Jun 27 05:22:44 PM PDT 24 2275329900 ps
T1157 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1435538251 Jun 27 05:10:36 PM PDT 24 Jun 27 05:10:51 PM PDT 24 132410600 ps
T1158 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1984000721 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:07 PM PDT 24 54801400 ps
T1159 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1490848360 Jun 27 05:10:14 PM PDT 24 Jun 27 05:10:31 PM PDT 24 13702300 ps
T266 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1814545825 Jun 27 05:08:19 PM PDT 24 Jun 27 05:08:34 PM PDT 24 29098800 ps
T1160 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3728189097 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:25 PM PDT 24 64136600 ps
T1161 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1258220661 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:50 PM PDT 24 29386600 ps
T1162 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2583339960 Jun 27 05:10:17 PM PDT 24 Jun 27 05:10:35 PM PDT 24 45564800 ps
T249 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1301284439 Jun 27 05:09:05 PM PDT 24 Jun 27 05:09:23 PM PDT 24 274975400 ps
T297 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.851050428 Jun 27 05:10:20 PM PDT 24 Jun 27 05:10:39 PM PDT 24 71086900 ps
T1163 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1020259633 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:05 PM PDT 24 47919000 ps
T1164 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3068258562 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:44 PM PDT 24 39006100 ps
T246 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2960095160 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:39 PM PDT 24 96858400 ps
T1165 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1293669623 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:42 PM PDT 24 59414300 ps
T1166 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2136352789 Jun 27 05:09:06 PM PDT 24 Jun 27 05:09:21 PM PDT 24 99790100 ps
T1167 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3853097543 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:06 PM PDT 24 23959500 ps
T1168 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1397731706 Jun 27 05:10:13 PM PDT 24 Jun 27 05:10:27 PM PDT 24 45370200 ps
T1169 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.57362289 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:05 PM PDT 24 44448900 ps
T1170 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1416492564 Jun 27 05:08:31 PM PDT 24 Jun 27 05:09:18 PM PDT 24 90448700 ps
T1171 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1025640168 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:33 PM PDT 24 64500100 ps
T1172 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.206041825 Jun 27 05:08:53 PM PDT 24 Jun 27 05:09:07 PM PDT 24 48138500 ps
T1173 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.753475576 Jun 27 05:10:38 PM PDT 24 Jun 27 05:10:52 PM PDT 24 31388500 ps
T1174 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2204772971 Jun 27 05:10:22 PM PDT 24 Jun 27 05:10:39 PM PDT 24 31858400 ps
T1175 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1684132771 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:50 PM PDT 24 55900500 ps
T1176 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4071067178 Jun 27 05:08:31 PM PDT 24 Jun 27 05:09:37 PM PDT 24 2195963400 ps
T298 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1264042864 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:40 PM PDT 24 412755000 ps
T1177 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4143562260 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:49 PM PDT 24 29790600 ps
T247 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2202225774 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:09 PM PDT 24 192279700 ps
T1178 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2508264642 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:38 PM PDT 24 136628600 ps
T1179 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1719802239 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:35 PM PDT 24 14454300 ps
T1180 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.830396689 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:40 PM PDT 24 119374600 ps
T1181 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1922355839 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:31 PM PDT 24 18270900 ps
T1182 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2325825721 Jun 27 05:08:33 PM PDT 24 Jun 27 05:08:50 PM PDT 24 42306200 ps
T1183 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.938245910 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:34 PM PDT 24 11633600 ps
T1184 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.904474444 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:43 PM PDT 24 916083400 ps
T1185 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.551077077 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:42 PM PDT 24 28684300 ps
T1186 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2360508546 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:26 PM PDT 24 653038200 ps
T1187 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2228562998 Jun 27 05:10:39 PM PDT 24 Jun 27 05:10:54 PM PDT 24 15534600 ps
T233 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3578429782 Jun 27 05:09:06 PM PDT 24 Jun 27 05:09:26 PM PDT 24 49307700 ps
T244 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1366123074 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:40 PM PDT 24 66575900 ps
T1188 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1437689370 Jun 27 05:08:47 PM PDT 24 Jun 27 05:09:46 PM PDT 24 1757479100 ps
T376 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3059176342 Jun 27 05:10:17 PM PDT 24 Jun 27 05:17:52 PM PDT 24 858170300 ps
T1189 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.776947956 Jun 27 05:09:47 PM PDT 24 Jun 27 05:10:06 PM PDT 24 109304300 ps
T299 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2601615039 Jun 27 05:08:45 PM PDT 24 Jun 27 05:09:16 PM PDT 24 57075900 ps
T371 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2218509365 Jun 27 05:09:24 PM PDT 24 Jun 27 05:15:54 PM PDT 24 1972501900 ps
T1190 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3845042656 Jun 27 05:08:33 PM PDT 24 Jun 27 05:08:49 PM PDT 24 57114500 ps
T1191 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2026469613 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:41 PM PDT 24 13426500 ps
T1192 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2980264112 Jun 27 05:10:38 PM PDT 24 Jun 27 05:10:53 PM PDT 24 181723400 ps
T1193 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1054640348 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:04 PM PDT 24 99513400 ps
T300 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3777990081 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:44 PM PDT 24 171825400 ps
T243 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.674074333 Jun 27 05:09:25 PM PDT 24 Jun 27 05:24:27 PM PDT 24 346126600 ps
T1194 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3934954521 Jun 27 05:10:38 PM PDT 24 Jun 27 05:10:52 PM PDT 24 18219700 ps
T268 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.84326981 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:03 PM PDT 24 32082600 ps
T1195 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1037747376 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:09 PM PDT 24 271580500 ps
T1196 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1905138128 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:09 PM PDT 24 162419000 ps
T245 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2959191035 Jun 27 05:09:08 PM PDT 24 Jun 27 05:09:30 PM PDT 24 351985000 ps
T1197 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2581019659 Jun 27 05:08:51 PM PDT 24 Jun 27 05:15:15 PM PDT 24 2026829300 ps
T1198 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.872475129 Jun 27 05:08:33 PM PDT 24 Jun 27 05:08:47 PM PDT 24 15281200 ps
T1199 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3182509637 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:42 PM PDT 24 26843200 ps
T1200 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.318716642 Jun 27 05:08:32 PM PDT 24 Jun 27 05:08:46 PM PDT 24 83940800 ps
T1201 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1478351222 Jun 27 05:08:33 PM PDT 24 Jun 27 05:08:49 PM PDT 24 17659700 ps
T1202 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.665202569 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:06 PM PDT 24 413400500 ps
T1203 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1371490835 Jun 27 05:10:36 PM PDT 24 Jun 27 05:10:51 PM PDT 24 188698400 ps
T1204 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1743746167 Jun 27 05:09:25 PM PDT 24 Jun 27 05:09:40 PM PDT 24 144223200 ps
T1205 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2516404967 Jun 27 05:10:22 PM PDT 24 Jun 27 05:10:38 PM PDT 24 46020900 ps
T375 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.137654777 Jun 27 05:10:16 PM PDT 24 Jun 27 05:23:03 PM PDT 24 3398124500 ps
T250 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.547016268 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:06 PM PDT 24 71228500 ps
T372 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3151995683 Jun 27 05:09:49 PM PDT 24 Jun 27 05:24:51 PM PDT 24 827661700 ps
T1206 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1921053812 Jun 27 05:09:07 PM PDT 24 Jun 27 05:09:21 PM PDT 24 31483800 ps
T1207 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.68365757 Jun 27 05:10:19 PM PDT 24 Jun 27 05:10:34 PM PDT 24 15635700 ps
T378 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.547013525 Jun 27 05:09:07 PM PDT 24 Jun 27 05:16:53 PM PDT 24 1705268300 ps
T1208 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3527479520 Jun 27 05:10:41 PM PDT 24 Jun 27 05:10:55 PM PDT 24 18111800 ps
T1209 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3111082333 Jun 27 05:08:31 PM PDT 24 Jun 27 05:08:46 PM PDT 24 79688500 ps
T1210 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1466976835 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:34 PM PDT 24 82842500 ps
T1211 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2154296977 Jun 27 05:10:14 PM PDT 24 Jun 27 05:10:33 PM PDT 24 25650700 ps
T1212 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.974832630 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:05 PM PDT 24 41525300 ps
T1213 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3941581279 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:52 PM PDT 24 125556800 ps
T1214 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3367397036 Jun 27 05:10:16 PM PDT 24 Jun 27 05:10:36 PM PDT 24 50615100 ps
T1215 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.316464097 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:34 PM PDT 24 152085300 ps
T1216 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1931345332 Jun 27 05:08:32 PM PDT 24 Jun 27 05:08:51 PM PDT 24 88371600 ps
T1217 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2742979729 Jun 27 05:10:41 PM PDT 24 Jun 27 05:10:55 PM PDT 24 19210400 ps
T1218 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.836105588 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:04 PM PDT 24 150635900 ps
T1219 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.503064469 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:35 PM PDT 24 40726300 ps
T1220 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1634367430 Jun 27 05:10:36 PM PDT 24 Jun 27 05:10:51 PM PDT 24 29065100 ps
T1221 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3801597293 Jun 27 05:08:31 PM PDT 24 Jun 27 05:08:48 PM PDT 24 39826400 ps
T1222 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.321744463 Jun 27 05:09:06 PM PDT 24 Jun 27 05:09:22 PM PDT 24 13057600 ps
T253 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1553628926 Jun 27 05:08:31 PM PDT 24 Jun 27 05:08:50 PM PDT 24 55533300 ps
T1223 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.916269803 Jun 27 05:09:24 PM PDT 24 Jun 27 05:09:44 PM PDT 24 206190100 ps
T1224 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3216248599 Jun 27 05:10:15 PM PDT 24 Jun 27 05:10:31 PM PDT 24 53445000 ps
T269 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.784804592 Jun 27 05:08:47 PM PDT 24 Jun 27 05:09:02 PM PDT 24 29366300 ps
T1225 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1670694022 Jun 27 05:08:47 PM PDT 24 Jun 27 05:09:05 PM PDT 24 326846400 ps
T1226 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1365479300 Jun 27 05:10:22 PM PDT 24 Jun 27 05:10:36 PM PDT 24 22334600 ps
T1227 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2615870012 Jun 27 05:08:46 PM PDT 24 Jun 27 05:09:44 PM PDT 24 3092877800 ps
T1228 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1597723815 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:07 PM PDT 24 96572500 ps
T1229 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.398042560 Jun 27 05:08:50 PM PDT 24 Jun 27 05:10:25 PM PDT 24 6424131400 ps
T1230 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.957010529 Jun 27 05:08:32 PM PDT 24 Jun 27 05:09:48 PM PDT 24 2230542800 ps
T1231 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1295854466 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:51 PM PDT 24 81553800 ps
T1232 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2325253040 Jun 27 05:10:35 PM PDT 24 Jun 27 05:10:51 PM PDT 24 15849600 ps
T239 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.441986853 Jun 27 05:09:26 PM PDT 24 Jun 27 05:09:48 PM PDT 24 62959400 ps
T1233 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1546955832 Jun 27 05:09:10 PM PDT 24 Jun 27 05:09:29 PM PDT 24 614186800 ps
T1234 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.193969997 Jun 27 05:09:09 PM PDT 24 Jun 27 05:09:23 PM PDT 24 67510200 ps
T1235 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1744092414 Jun 27 05:09:49 PM PDT 24 Jun 27 05:10:07 PM PDT 24 40692400 ps
T1236 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.841722409 Jun 27 05:10:37 PM PDT 24 Jun 27 05:10:52 PM PDT 24 15827900 ps
T1237 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3995461992 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:49 PM PDT 24 55946800 ps
T1238 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.173966750 Jun 27 05:08:38 PM PDT 24 Jun 27 05:08:53 PM PDT 24 42184200 ps
T1239 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3495103555 Jun 27 05:10:16 PM PDT 24 Jun 27 05:17:56 PM PDT 24 1456923700 ps
T1240 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.389540349 Jun 27 05:08:31 PM PDT 24 Jun 27 05:08:52 PM PDT 24 75360400 ps
T1241 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2542353784 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:03 PM PDT 24 39674600 ps
T377 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.245258641 Jun 27 05:10:17 PM PDT 24 Jun 27 05:25:18 PM PDT 24 698062100 ps
T1242 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.557762590 Jun 27 05:09:48 PM PDT 24 Jun 27 05:10:07 PM PDT 24 356107900 ps
T270 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.641805499 Jun 27 05:08:38 PM PDT 24 Jun 27 05:08:52 PM PDT 24 39957200 ps
T1243 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2317976991 Jun 27 05:10:38 PM PDT 24 Jun 27 05:10:54 PM PDT 24 17080500 ps
T1244 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3463486077 Jun 27 05:08:54 PM PDT 24 Jun 27 05:09:16 PM PDT 24 725732300 ps
T1245 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1992152165 Jun 27 05:10:34 PM PDT 24 Jun 27 05:10:50 PM PDT 24 35432100 ps
T1246 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1605620785 Jun 27 05:08:14 PM PDT 24 Jun 27 05:09:00 PM PDT 24 146433400 ps
T240 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2976607550 Jun 27 05:08:13 PM PDT 24 Jun 27 05:08:31 PM PDT 24 81156400 ps
T251 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.512886870 Jun 27 05:08:48 PM PDT 24 Jun 27 05:09:09 PM PDT 24 55480200 ps
T1247 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1708092421 Jun 27 05:10:38 PM PDT 24 Jun 27 05:10:53 PM PDT 24 63047800 ps

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2496247087
Short name T20
Test name
Test status
Simulation time 31490100 ps
CPU time 31.47 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:20:47 PM PDT 24
Peak memory 275836 kb
Host smart-e95736b9-d430-4a01-8e21-0de297e22965
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496247087 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2496247087
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1071222345
Short name T24
Test name
Test status
Simulation time 1916812700 ps
CPU time 1862.21 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:43:56 PM PDT 24
Peak memory 298396 kb
Host smart-7989eba0-3eee-46b3-a101-e01b43cc7158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071222345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1071222345
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.954944547
Short name T70
Test name
Test status
Simulation time 689729400 ps
CPU time 459.65 seconds
Started Jun 27 05:08:16 PM PDT 24
Finished Jun 27 05:15:57 PM PDT 24
Peak memory 263632 kb
Host smart-692e46b8-52ca-4703-937c-99e5ef9d62c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954944547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.954944547
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.2841069318
Short name T76
Test name
Test status
Simulation time 40681400 ps
CPU time 134.84 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:25:11 PM PDT 24
Peak memory 265540 kb
Host smart-6efaa457-e555-4ade-8e97-0ad0079bad57
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841069318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.2841069318
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1952495279
Short name T25
Test name
Test status
Simulation time 7929531400 ps
CPU time 849.62 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:27:05 PM PDT 24
Peak memory 343036 kb
Host smart-a4acd9a7-ff8c-47db-9640-dc7135e901a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952495279 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1952495279
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.668054492
Short name T81
Test name
Test status
Simulation time 98712873700 ps
CPU time 1843.28 seconds
Started Jun 27 05:11:35 PM PDT 24
Finished Jun 27 05:42:20 PM PDT 24
Peak memory 260272 kb
Host smart-9b7e392a-b2b5-4bc7-967f-7abf57520137
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668054492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.668054492
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.412404904
Short name T101
Test name
Test status
Simulation time 112399200 ps
CPU time 17.65 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:26 PM PDT 24
Peak memory 271084 kb
Host smart-d504b97f-2d95-4f58-aeea-24eb6248e9ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412404904 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.412404904
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.359331762
Short name T18
Test name
Test status
Simulation time 1012589400 ps
CPU time 4830.34 seconds
Started Jun 27 05:12:05 PM PDT 24
Finished Jun 27 06:32:37 PM PDT 24
Peak memory 283788 kb
Host smart-bdaae9c0-970a-4539-86f2-ed1919b316a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359331762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.359331762
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2410562904
Short name T21
Test name
Test status
Simulation time 2259876400 ps
CPU time 155.55 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:22:02 PM PDT 24
Peak memory 261356 kb
Host smart-49d87628-96fa-4b71-a3e8-ab0da455c9b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410562904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2410562904
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.4270473571
Short name T74
Test name
Test status
Simulation time 44494619900 ps
CPU time 552.26 seconds
Started Jun 27 05:11:31 PM PDT 24
Finished Jun 27 05:20:45 PM PDT 24
Peak memory 263820 kb
Host smart-d2ff7bb9-7284-4293-936d-61a498db7f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270473571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.4270473571
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.4191548143
Short name T84
Test name
Test status
Simulation time 31285938100 ps
CPU time 823.82 seconds
Started Jun 27 05:15:53 PM PDT 24
Finished Jun 27 05:29:37 PM PDT 24
Peak memory 274836 kb
Host smart-c7c486f3-bf4b-409f-b4ba-593a9850fa49
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191548143 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.4191548143
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1086685790
Short name T90
Test name
Test status
Simulation time 992507800 ps
CPU time 68.72 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:12:40 PM PDT 24
Peak memory 260740 kb
Host smart-5723cb2f-a02e-4191-ad42-680187405a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086685790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1086685790
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.4210001543
Short name T16
Test name
Test status
Simulation time 10012883600 ps
CPU time 94.23 seconds
Started Jun 27 05:12:36 PM PDT 24
Finished Jun 27 05:14:11 PM PDT 24
Peak memory 294912 kb
Host smart-862577aa-852a-4319-aa43-f4f984520b31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210001543 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.4210001543
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4054292638
Short name T15
Test name
Test status
Simulation time 15962800 ps
CPU time 14.12 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:24 PM PDT 24
Peak memory 265420 kb
Host smart-dcc8f98a-a1ee-47e5-8a62-5a9237da4650
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054292638 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4054292638
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3705628006
Short name T236
Test name
Test status
Simulation time 60010800 ps
CPU time 13.24 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 05:10:54 PM PDT 24
Peak memory 261032 kb
Host smart-b3442b5e-5529-47b3-b4b5-7bc2a161886b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705628006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3705628006
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.143061192
Short name T111
Test name
Test status
Simulation time 64829100 ps
CPU time 131.57 seconds
Started Jun 27 05:12:37 PM PDT 24
Finished Jun 27 05:14:50 PM PDT 24
Peak memory 265668 kb
Host smart-4d1fd114-9789-4b7b-b602-c83745c4f16f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143061192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp
_reset.143061192
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3135043986
Short name T173
Test name
Test status
Simulation time 41467400 ps
CPU time 132.8 seconds
Started Jun 27 05:22:53 PM PDT 24
Finished Jun 27 05:25:07 PM PDT 24
Peak memory 260576 kb
Host smart-cfc4e229-f966-4368-8559-1e0d8371ef02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135043986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3135043986
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.750635487
Short name T34
Test name
Test status
Simulation time 24744757400 ps
CPU time 168.3 seconds
Started Jun 27 05:17:10 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 291352 kb
Host smart-db184096-aefb-4fa2-b423-37d8d07fa315
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750635487 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.750635487
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2359994329
Short name T225
Test name
Test status
Simulation time 188109100 ps
CPU time 19.26 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:09 PM PDT 24
Peak memory 262872 kb
Host smart-a9002a95-b8b9-4452-abaa-692cdb88384f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359994329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2359994329
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1814329161
Short name T99
Test name
Test status
Simulation time 22438100 ps
CPU time 13.49 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:15:51 PM PDT 24
Peak memory 260116 kb
Host smart-2da5e1a5-7e98-4ba5-8b85-d1687c2a3e8c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814329161 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.1814329161
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.520534006
Short name T4
Test name
Test status
Simulation time 3920295200 ps
CPU time 80.59 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:21:12 PM PDT 24
Peak memory 264172 kb
Host smart-4a986de9-8dc2-4451-84ce-efb3e082eda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520534006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.520534006
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2383716300
Short name T49
Test name
Test status
Simulation time 30785300 ps
CPU time 22.17 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:21:52 PM PDT 24
Peak memory 273864 kb
Host smart-df01da9e-c758-4f99-8e91-97499ebf0a31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383716300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2383716300
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.4048025827
Short name T304
Test name
Test status
Simulation time 32374600 ps
CPU time 13.71 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:08 PM PDT 24
Peak memory 259048 kb
Host smart-36905fe6-aa86-4446-a987-9c391a96294a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048025827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
4048025827
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.810315235
Short name T46
Test name
Test status
Simulation time 1065914500 ps
CPU time 23.28 seconds
Started Jun 27 05:11:53 PM PDT 24
Finished Jun 27 05:12:17 PM PDT 24
Peak memory 262796 kb
Host smart-edd4dbab-130d-446e-b9c2-8ce0e8d9907d
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810315235 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_fetch_code.810315235
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.725145549
Short name T171
Test name
Test status
Simulation time 216451900 ps
CPU time 132.35 seconds
Started Jun 27 05:20:44 PM PDT 24
Finished Jun 27 05:22:57 PM PDT 24
Peak memory 264988 kb
Host smart-3fa1bb64-c0b4-411f-a679-09161f64b9b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725145549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.725145549
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2658171189
Short name T164
Test name
Test status
Simulation time 163828133500 ps
CPU time 942.85 seconds
Started Jun 27 05:12:38 PM PDT 24
Finished Jun 27 05:28:21 PM PDT 24
Peak memory 261776 kb
Host smart-3d827f96-1061-41c6-a5a6-7f7ff1942dbe
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658171189 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2658171189
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.2643457032
Short name T175
Test name
Test status
Simulation time 245022781700 ps
CPU time 2511.22 seconds
Started Jun 27 05:11:52 PM PDT 24
Finished Jun 27 05:53:45 PM PDT 24
Peak memory 264376 kb
Host smart-100860c2-a24a-494f-b6e3-0419fc9f6a29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643457032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.2643457032
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2885784234
Short name T154
Test name
Test status
Simulation time 856551700 ps
CPU time 70.39 seconds
Started Jun 27 05:10:52 PM PDT 24
Finished Jun 27 05:12:04 PM PDT 24
Peak memory 260816 kb
Host smart-21cf14da-ad54-4cb2-b036-bf1ab61dbcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885784234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2885784234
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.25572807
Short name T301
Test name
Test status
Simulation time 6629479400 ps
CPU time 121.13 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:25:00 PM PDT 24
Peak memory 263712 kb
Host smart-1ab01863-8999-4b17-95ee-dbddfd7b6934
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25572807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw
_sec_otp.25572807
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.4266380828
Short name T92
Test name
Test status
Simulation time 1375288900 ps
CPU time 71.85 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:13:07 PM PDT 24
Peak memory 260864 kb
Host smart-41a8c4d6-3a8c-4c93-a146-8f9cb368677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266380828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.4266380828
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.2350212939
Short name T119
Test name
Test status
Simulation time 261132200 ps
CPU time 34.41 seconds
Started Jun 27 05:18:20 PM PDT 24
Finished Jun 27 05:18:56 PM PDT 24
Peak memory 278196 kb
Host smart-adfe9c0b-5a1f-4b1f-80a9-1cc921354ae9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350212939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.2350212939
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1814545825
Short name T266
Test name
Test status
Simulation time 29098800 ps
CPU time 13.56 seconds
Started Jun 27 05:08:19 PM PDT 24
Finished Jun 27 05:08:34 PM PDT 24
Peak memory 262404 kb
Host smart-22f21ce9-0233-4e71-9a83-577173d1917a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814545825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.1814545825
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1992126725
Short name T235
Test name
Test status
Simulation time 275152700 ps
CPU time 17.43 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:06 PM PDT 24
Peak memory 263644 kb
Host smart-9d367df4-69d9-47d9-ac27-fa524d189fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992126725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1
992126725
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2291600426
Short name T224
Test name
Test status
Simulation time 181020700 ps
CPU time 455.4 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:17:26 PM PDT 24
Peak memory 263648 kb
Host smart-e1164d3d-39e7-4379-8170-c478edc1b83c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291600426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2291600426
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1136137367
Short name T503
Test name
Test status
Simulation time 2776933300 ps
CPU time 142.38 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:23:20 PM PDT 24
Peak memory 291372 kb
Host smart-3fd2d36d-416a-4bce-bd18-86f4d6113448
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136137367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1136137367
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.660611030
Short name T147
Test name
Test status
Simulation time 2083664000 ps
CPU time 69.26 seconds
Started Jun 27 05:14:23 PM PDT 24
Finished Jun 27 05:15:33 PM PDT 24
Peak memory 264096 kb
Host smart-8abc0843-83fe-41aa-8bbe-42d04769cfc1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660611030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.660611030
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2236716676
Short name T63
Test name
Test status
Simulation time 1438852900 ps
CPU time 2485.91 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:54:22 PM PDT 24
Peak memory 265080 kb
Host smart-224b3ab1-88c7-49af-9a80-a65c8a719f7b
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236716676 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2236716676
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.277829820
Short name T315
Test name
Test status
Simulation time 11329097200 ps
CPU time 143.86 seconds
Started Jun 27 05:15:35 PM PDT 24
Finished Jun 27 05:18:00 PM PDT 24
Peak memory 263752 kb
Host smart-3a9143d6-6125-435e-8f45-ae40bbb0b080
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277829820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw
_sec_otp.277829820
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1689990577
Short name T223
Test name
Test status
Simulation time 83076600 ps
CPU time 15.14 seconds
Started Jun 27 05:12:03 PM PDT 24
Finished Jun 27 05:12:19 PM PDT 24
Peak memory 265092 kb
Host smart-2f788a8c-7fa0-4801-b9ed-3a4713bb1bc0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689990577 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1689990577
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3834778465
Short name T355
Test name
Test status
Simulation time 64152000 ps
CPU time 32.07 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:15:48 PM PDT 24
Peak memory 275920 kb
Host smart-9dd4d99c-f712-4b84-8a28-36896b2aff5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834778465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3834778465
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3170107428
Short name T267
Test name
Test status
Simulation time 15625300 ps
CPU time 13.39 seconds
Started Jun 27 05:08:47 PM PDT 24
Finished Jun 27 05:09:02 PM PDT 24
Peak memory 261968 kb
Host smart-6ed980ee-4ca7-426e-a8b0-bab3bdf5c0dc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170107428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.3170107428
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.358101226
Short name T575
Test name
Test status
Simulation time 17540766200 ps
CPU time 683.99 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:24:19 PM PDT 24
Peak memory 310032 kb
Host smart-7e6045e4-7e1d-4cfa-ad82-ced05d2edc5b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358101226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_rw.358101226
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.1655308793
Short name T185
Test name
Test status
Simulation time 8053457600 ps
CPU time 748.44 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:27:45 PM PDT 24
Peak memory 340560 kb
Host smart-8ab0625f-b265-4036-9d54-48f71f054a60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655308793 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.1655308793
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3688507948
Short name T334
Test name
Test status
Simulation time 23523300 ps
CPU time 13.14 seconds
Started Jun 27 05:11:43 PM PDT 24
Finished Jun 27 05:11:57 PM PDT 24
Peak memory 260684 kb
Host smart-45e1b32c-4fcc-40f5-8305-b53d79553f02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688507948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3688507948
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.349921282
Short name T23
Test name
Test status
Simulation time 342411100 ps
CPU time 32.17 seconds
Started Jun 27 05:19:27 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 275888 kb
Host smart-7e5597d3-069c-481a-827b-dee5eee52275
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349921282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_rw_evict.349921282
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.3765645341
Short name T335
Test name
Test status
Simulation time 15423734300 ps
CPU time 199.69 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:17:28 PM PDT 24
Peak memory 294080 kb
Host smart-358a3a05-22f1-4a79-8a82-e9a6e6111058
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765645341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.3765645341
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2512827965
Short name T115
Test name
Test status
Simulation time 836112000 ps
CPU time 18.16 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:11:50 PM PDT 24
Peak memory 265656 kb
Host smart-708a11bb-2013-4b92-a310-150cd14a674b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512827965 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2512827965
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.2845752465
Short name T59
Test name
Test status
Simulation time 1602435100 ps
CPU time 4748.7 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 06:32:07 PM PDT 24
Peak memory 290892 kb
Host smart-a1c6ac84-d6ce-4a40-9338-76487dd5e89b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845752465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.2845752465
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3516448267
Short name T213
Test name
Test status
Simulation time 139897400 ps
CPU time 14.3 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:11:48 PM PDT 24
Peak memory 265360 kb
Host smart-3c35841f-8ab7-4e02-88be-8248fdec562a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3516448267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3516448267
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1906856861
Short name T232
Test name
Test status
Simulation time 59258500 ps
CPU time 19.99 seconds
Started Jun 27 05:10:18 PM PDT 24
Finished Jun 27 05:10:40 PM PDT 24
Peak memory 263528 kb
Host smart-218b1df6-6b33-47ce-8f86-2b8b31116f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906856861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1906856861
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.279391561
Short name T58
Test name
Test status
Simulation time 25517400 ps
CPU time 13.64 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:13:11 PM PDT 24
Peak memory 260596 kb
Host smart-a8595b6e-0956-4ec6-b1b1-8ff54725fef8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279391561 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.279391561
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3027224811
Short name T217
Test name
Test status
Simulation time 188365000 ps
CPU time 13.9 seconds
Started Jun 27 05:12:52 PM PDT 24
Finished Jun 27 05:13:07 PM PDT 24
Peak memory 265048 kb
Host smart-bf255c89-4834-46f3-9643-5f3d298a7b71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027224811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3027224811
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3416932531
Short name T975
Test name
Test status
Simulation time 26923000 ps
CPU time 14.4 seconds
Started Jun 27 05:17:43 PM PDT 24
Finished Jun 27 05:17:58 PM PDT 24
Peak memory 261020 kb
Host smart-85eda05f-3ac8-45c3-8b10-cc896a8c4f76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416932531 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3416932531
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3561955682
Short name T83
Test name
Test status
Simulation time 11663800 ps
CPU time 22.14 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:14 PM PDT 24
Peak memory 274012 kb
Host smart-b1e7419e-ebbe-4666-9d91-c6aa04127aa5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561955682 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3561955682
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.137654777
Short name T375
Test name
Test status
Simulation time 3398124500 ps
CPU time 764.53 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:23:03 PM PDT 24
Peak memory 263548 kb
Host smart-60522335-0264-4288-9cea-12985958324c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137654777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.137654777
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.245258641
Short name T377
Test name
Test status
Simulation time 698062100 ps
CPU time 898.68 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:25:18 PM PDT 24
Peak memory 263704 kb
Host smart-61d6c28e-a5c7-46aa-9469-4cad9ddf3025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245258641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_tl_intg_err.245258641
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.547013525
Short name T378
Test name
Test status
Simulation time 1705268300 ps
CPU time 464.36 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:16:53 PM PDT 24
Peak memory 263620 kb
Host smart-bae156f5-aee2-49a0-9610-acb74407104d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547013525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
tl_intg_err.547013525
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1964411829
Short name T419
Test name
Test status
Simulation time 4032740900 ps
CPU time 98.3 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:13:10 PM PDT 24
Peak memory 260956 kb
Host smart-87c92518-64bd-4ac1-b26b-b47032f6b9e7
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964411829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1964411829
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1209840053
Short name T33
Test name
Test status
Simulation time 88669524500 ps
CPU time 270.78 seconds
Started Jun 27 05:16:10 PM PDT 24
Finished Jun 27 05:20:42 PM PDT 24
Peak memory 292244 kb
Host smart-e2b85efb-7481-449d-91eb-e21b8b4e285f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209840053 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1209840053
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.815117910
Short name T834
Test name
Test status
Simulation time 45562100 ps
CPU time 13.67 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:24 PM PDT 24
Peak memory 265532 kb
Host smart-8d229b07-19d4-4bd9-bd49-e4ede965f00d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815117910 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.815117910
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1567013387
Short name T106
Test name
Test status
Simulation time 25499400 ps
CPU time 13.46 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:19:05 PM PDT 24
Peak memory 275392 kb
Host smart-1af1f68a-7987-49da-9fe3-81ef058c46b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567013387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1567013387
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2805646602
Short name T127
Test name
Test status
Simulation time 5006556000 ps
CPU time 859.84 seconds
Started Jun 27 05:11:48 PM PDT 24
Finished Jun 27 05:26:09 PM PDT 24
Peak memory 273692 kb
Host smart-74153161-6bb2-4e75-808a-9af28ce28c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805646602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2805646602
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3744439119
Short name T192
Test name
Test status
Simulation time 15106800 ps
CPU time 13.89 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:11:49 PM PDT 24
Peak memory 262916 kb
Host smart-56d25c03-0b0f-40fd-a976-51094a13a21a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744439119 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3744439119
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3709122440
Short name T50
Test name
Test status
Simulation time 798512600 ps
CPU time 15.53 seconds
Started Jun 27 05:12:36 PM PDT 24
Finished Jun 27 05:12:52 PM PDT 24
Peak memory 265688 kb
Host smart-0511dfb0-219c-4982-b97e-dc85db19c420
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709122440 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3709122440
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.2255276492
Short name T102
Test name
Test status
Simulation time 343295600 ps
CPU time 133.49 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:22:05 PM PDT 24
Peak memory 265484 kb
Host smart-7b1b5419-0e07-4173-a772-49ce75d5a191
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255276492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.2255276492
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.295923596
Short name T151
Test name
Test status
Simulation time 10012420200 ps
CPU time 118.66 seconds
Started Jun 27 05:11:12 PM PDT 24
Finished Jun 27 05:13:12 PM PDT 24
Peak memory 311600 kb
Host smart-9a35af65-ba03-43fa-af49-0b2e8f8ee239
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295923596 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.295923596
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1027385457
Short name T165
Test name
Test status
Simulation time 10018864100 ps
CPU time 183.35 seconds
Started Jun 27 05:11:52 PM PDT 24
Finished Jun 27 05:14:56 PM PDT 24
Peak memory 297008 kb
Host smart-67db9eb3-e85d-4948-90a9-933e75874703
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027385457 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1027385457
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2080488764
Short name T289
Test name
Test status
Simulation time 1710148000 ps
CPU time 465.92 seconds
Started Jun 27 05:08:33 PM PDT 24
Finished Jun 27 05:16:20 PM PDT 24
Peak memory 263512 kb
Host smart-20347cde-2dba-4d5d-9508-d447be44a24b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080488764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2080488764
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3540707560
Short name T546
Test name
Test status
Simulation time 1221081100 ps
CPU time 68.37 seconds
Started Jun 27 05:16:45 PM PDT 24
Finished Jun 27 05:17:55 PM PDT 24
Peak memory 265620 kb
Host smart-715d9b29-0db8-4970-a273-ea7c91574b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540707560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3540707560
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2914822921
Short name T731
Test name
Test status
Simulation time 5143714900 ps
CPU time 65.94 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:20:58 PM PDT 24
Peak memory 264240 kb
Host smart-537c7c45-6492-4c29-942e-ca77c432f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914822921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2914822921
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1604768888
Short name T357
Test name
Test status
Simulation time 79865200 ps
CPU time 29.78 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:21:05 PM PDT 24
Peak memory 275928 kb
Host smart-243f02f5-a34f-444c-b7e2-ddc3b4f9428d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604768888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1604768888
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.1235867551
Short name T402
Test name
Test status
Simulation time 1491524000 ps
CPU time 59.14 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:23:01 PM PDT 24
Peak memory 264232 kb
Host smart-8c8de06d-8eb6-4498-a0ec-45cbdeb00150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235867551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1235867551
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.128619679
Short name T414
Test name
Test status
Simulation time 1786877700 ps
CPU time 60.9 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:23:04 PM PDT 24
Peak memory 264316 kb
Host smart-7b42f4d8-f30f-4b1f-8adc-895098600981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128619679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.128619679
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1194214403
Short name T241
Test name
Test status
Simulation time 86460900 ps
CPU time 16.33 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:25 PM PDT 24
Peak memory 263676 kb
Host smart-f2dc41a2-abe2-468f-93aa-905fd956db86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194214403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
194214403
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.2907887756
Short name T11
Test name
Test status
Simulation time 15705700 ps
CPU time 13.96 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:11:25 PM PDT 24
Peak memory 265688 kb
Host smart-960b790d-3c8e-4551-82aa-d5203ecc72b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907887756 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2907887756
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4134148487
Short name T66
Test name
Test status
Simulation time 26563600 ps
CPU time 14.02 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:24 PM PDT 24
Peak memory 277284 kb
Host smart-6307eebc-364f-4a54-9dec-f294671621b8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4134148487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4134148487
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.679036707
Short name T447
Test name
Test status
Simulation time 40926200 ps
CPU time 31.31 seconds
Started Jun 27 05:17:43 PM PDT 24
Finished Jun 27 05:18:16 PM PDT 24
Peak memory 275996 kb
Host smart-579c1fa3-2f5f-476e-9039-e5bda6bca0c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679036707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_rw_evict.679036707
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.216656493
Short name T42
Test name
Test status
Simulation time 10893600 ps
CPU time 21.59 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:18:06 PM PDT 24
Peak memory 265848 kb
Host smart-977524b9-0575-4cee-8963-a2167db56eec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216656493 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.216656493
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1552019097
Short name T134
Test name
Test status
Simulation time 180976972400 ps
CPU time 3763.75 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 06:14:16 PM PDT 24
Peak memory 265344 kb
Host smart-6e263aba-6807-4691-ba14-9e676ce71d4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552019097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1552019097
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1054640348
Short name T1193
Test name
Test status
Simulation time 99513400 ps
CPU time 13.79 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:04 PM PDT 24
Peak memory 260940 kb
Host smart-dc95bf1b-a2cf-4212-b823-c102be468039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054640348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
1054640348
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2805942092
Short name T248
Test name
Test status
Simulation time 692488300 ps
CPU time 457.06 seconds
Started Jun 27 05:10:20 PM PDT 24
Finished Jun 27 05:17:59 PM PDT 24
Peak memory 263540 kb
Host smart-54b69cd3-18d9-490b-b8fc-52fcea0f7f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805942092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.2805942092
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.3117032637
Short name T886
Test name
Test status
Simulation time 41052200 ps
CPU time 22.27 seconds
Started Jun 27 05:11:11 PM PDT 24
Finished Jun 27 05:11:34 PM PDT 24
Peak memory 273964 kb
Host smart-4b734ad1-3855-4b44-bcb5-3c3f980d76d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117032637 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.3117032637
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.3491977348
Short name T366
Test name
Test status
Simulation time 379042200 ps
CPU time 43.36 seconds
Started Jun 27 05:11:08 PM PDT 24
Finished Jun 27 05:11:53 PM PDT 24
Peak memory 265600 kb
Host smart-fa003340-d320-4f19-abaa-bb40f2903e6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491977348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.3491977348
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.125561345
Short name T542
Test name
Test status
Simulation time 31570700 ps
CPU time 13.96 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:11:44 PM PDT 24
Peak memory 265388 kb
Host smart-0dcc7e74-1d74-47ef-80ea-e7859201f6c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125561345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_prog_reset.125561345
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3463760844
Short name T400
Test name
Test status
Simulation time 11366400 ps
CPU time 20.64 seconds
Started Jun 27 05:16:30 PM PDT 24
Finished Jun 27 05:16:52 PM PDT 24
Peak memory 265816 kb
Host smart-7baedf06-772c-4084-9193-51a95a9bac76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463760844 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3463760844
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3495534837
Short name T726
Test name
Test status
Simulation time 78647200 ps
CPU time 28.49 seconds
Started Jun 27 05:17:54 PM PDT 24
Finished Jun 27 05:18:24 PM PDT 24
Peak memory 275836 kb
Host smart-d54e1447-9c92-491d-a069-69a9c03367e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495534837 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3495534837
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.808805116
Short name T587
Test name
Test status
Simulation time 15741300 ps
CPU time 22.13 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:18:55 PM PDT 24
Peak memory 265300 kb
Host smart-baadd5f6-95c9-490e-b918-0f7018f50684
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808805116 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.808805116
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.136859049
Short name T382
Test name
Test status
Simulation time 11050900 ps
CPU time 22.32 seconds
Started Jun 27 05:12:05 PM PDT 24
Finished Jun 27 05:12:28 PM PDT 24
Peak memory 274264 kb
Host smart-17a4ea0f-652e-47d1-81a4-00b3651bad37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136859049 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.136859049
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.101159259
Short name T411
Test name
Test status
Simulation time 1097880400 ps
CPU time 60.56 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:21:16 PM PDT 24
Peak memory 265220 kb
Host smart-f722bd4c-83d7-48ce-9fd3-2712636e5b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101159259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.101159259
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2831914902
Short name T404
Test name
Test status
Simulation time 3986041700 ps
CPU time 70.61 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:14:08 PM PDT 24
Peak memory 265584 kb
Host smart-dea8cdc4-a140-4256-9a3f-78beb446c730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831914902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2831914902
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3118683339
Short name T380
Test name
Test status
Simulation time 11418000 ps
CPU time 21.07 seconds
Started Jun 27 05:22:02 PM PDT 24
Finished Jun 27 05:22:25 PM PDT 24
Peak memory 274072 kb
Host smart-f14ec8ef-5dfe-4e46-9eb5-f44712667c4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118683339 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3118683339
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3165971073
Short name T205
Test name
Test status
Simulation time 776250400 ps
CPU time 19.39 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:30 PM PDT 24
Peak memory 265720 kb
Host smart-fe8ca2ff-b348-4420-9581-4dc92bbae9dc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165971073 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3165971073
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.2209222801
Short name T29
Test name
Test status
Simulation time 1886224400 ps
CPU time 56.25 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:12:27 PM PDT 24
Peak memory 260352 kb
Host smart-a03d924f-2928-4898-945b-a17c9713a7ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209222801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.2209222801
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.4037077517
Short name T160
Test name
Test status
Simulation time 240214019800 ps
CPU time 1058.76 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:35:25 PM PDT 24
Peak memory 264912 kb
Host smart-8f172cc1-bb23-40a9-a66b-5a5fa0c27d8a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037077517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.4037077517
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.3184743992
Short name T199
Test name
Test status
Simulation time 18636339000 ps
CPU time 608.3 seconds
Started Jun 27 05:17:43 PM PDT 24
Finished Jun 27 05:27:52 PM PDT 24
Peak memory 310164 kb
Host smart-7a96a59c-2823-4fe3-9607-8751ce2f03a5
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184743992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.3184743992
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2202225774
Short name T247
Test name
Test status
Simulation time 192279700 ps
CPU time 18.64 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:09 PM PDT 24
Peak memory 263652 kb
Host smart-49043a20-75bb-4952-90eb-b30a376ad4fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202225774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2202225774
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2224930303
Short name T89
Test name
Test status
Simulation time 52435708800 ps
CPU time 274.7 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 293628 kb
Host smart-22010ded-31aa-48a8-bcf5-43e0d8e8b03d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224930303 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.2224930303
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.237470875
Short name T799
Test name
Test status
Simulation time 16254972700 ps
CPU time 2202.71 seconds
Started Jun 27 05:10:54 PM PDT 24
Finished Jun 27 05:47:37 PM PDT 24
Peak memory 263228 kb
Host smart-33371e3f-eb8d-48f5-a482-6fd223a54a0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=237470875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.237470875
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.3129925833
Short name T198
Test name
Test status
Simulation time 84967400 ps
CPU time 71.67 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 05:11:53 PM PDT 24
Peak memory 265624 kb
Host smart-69534bec-94bd-40cf-990b-d7b1b8118c87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129925833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.3129925833
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.84664809
Short name T122
Test name
Test status
Simulation time 104119234400 ps
CPU time 402.93 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 05:17:24 PM PDT 24
Peak memory 275280 kb
Host smart-91e8950d-82f6-4b34-8880-2e19f19b5aca
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84664809 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.84664809
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.504449525
Short name T117
Test name
Test status
Simulation time 119627200 ps
CPU time 103.75 seconds
Started Jun 27 05:11:31 PM PDT 24
Finished Jun 27 05:13:17 PM PDT 24
Peak memory 273208 kb
Host smart-da717d1b-81e5-458b-b7ef-157fa07c1a62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504449525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_derr_detect.504449525
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1611226704
Short name T116
Test name
Test status
Simulation time 741272300 ps
CPU time 16.34 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:13:14 PM PDT 24
Peak memory 263384 kb
Host smart-70b64450-3ea5-4341-8763-0e5dd40ed140
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611226704 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1611226704
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.766585572
Short name T287
Test name
Test status
Simulation time 783792100 ps
CPU time 39.87 seconds
Started Jun 27 05:08:30 PM PDT 24
Finished Jun 27 05:09:10 PM PDT 24
Peak memory 260948 kb
Host smart-0d726b0f-f127-49e9-9276-207a98f5c2bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766585572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_aliasing.766585572
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.4071067178
Short name T1176
Test name
Test status
Simulation time 2195963400 ps
CPU time 65.45 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:09:37 PM PDT 24
Peak memory 261136 kb
Host smart-32bcfbe5-c2f5-4203-9ae4-6f42dc924aef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071067178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.4071067178
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1605620785
Short name T1246
Test name
Test status
Simulation time 146433400 ps
CPU time 44.37 seconds
Started Jun 27 05:08:14 PM PDT 24
Finished Jun 27 05:09:00 PM PDT 24
Peak memory 261184 kb
Host smart-e5c9a2dc-04bc-4b6f-ada9-21cde49dbe4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605620785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1605620785
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1670694022
Short name T1225
Test name
Test status
Simulation time 326846400 ps
CPU time 16.24 seconds
Started Jun 27 05:08:47 PM PDT 24
Finished Jun 27 05:09:05 PM PDT 24
Peak memory 270348 kb
Host smart-3ec83c3d-66ea-410c-8704-387a94fccd8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670694022 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1670694022
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3845042656
Short name T1190
Test name
Test status
Simulation time 57114500 ps
CPU time 15.57 seconds
Started Jun 27 05:08:33 PM PDT 24
Finished Jun 27 05:08:49 PM PDT 24
Peak memory 263432 kb
Host smart-37531076-e647-4a3b-ab42-e6bd5b691f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845042656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.3845042656
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1208050480
Short name T238
Test name
Test status
Simulation time 36193700 ps
CPU time 13.52 seconds
Started Jun 27 05:08:15 PM PDT 24
Finished Jun 27 05:08:30 PM PDT 24
Peak memory 261192 kb
Host smart-5d69475d-2fd2-405e-942a-034b72c6219e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208050480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
208050480
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1515564563
Short name T1117
Test name
Test status
Simulation time 16125300 ps
CPU time 13.21 seconds
Started Jun 27 05:08:16 PM PDT 24
Finished Jun 27 05:08:31 PM PDT 24
Peak memory 261084 kb
Host smart-d9725977-e1ef-4ea6-8e14-343502d4ff27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515564563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1515564563
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1076303890
Short name T277
Test name
Test status
Simulation time 2101878100 ps
CPU time 36 seconds
Started Jun 27 05:08:30 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 263568 kb
Host smart-32950546-e097-4c18-9d34-0eb1eb99e80c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076303890 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1076303890
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3063701336
Short name T1118
Test name
Test status
Simulation time 19566600 ps
CPU time 13.4 seconds
Started Jun 27 05:08:16 PM PDT 24
Finished Jun 27 05:08:31 PM PDT 24
Peak memory 253008 kb
Host smart-45e89cca-2499-45ee-a633-790dde7f616a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063701336 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.3063701336
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2693812466
Short name T1140
Test name
Test status
Simulation time 25840500 ps
CPU time 13.18 seconds
Started Jun 27 05:08:17 PM PDT 24
Finished Jun 27 05:08:31 PM PDT 24
Peak memory 252884 kb
Host smart-c291b886-4207-4ab8-82bb-e04177b792be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693812466 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2693812466
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2976607550
Short name T240
Test name
Test status
Simulation time 81156400 ps
CPU time 16.62 seconds
Started Jun 27 05:08:13 PM PDT 24
Finished Jun 27 05:08:31 PM PDT 24
Peak memory 263828 kb
Host smart-d5db3424-51a8-4961-be8b-0ecf2ff49231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976607550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
976607550
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2360508546
Short name T1186
Test name
Test status
Simulation time 653038200 ps
CPU time 38.44 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:26 PM PDT 24
Peak memory 261100 kb
Host smart-10a355f6-cb0b-4608-8589-e5295b917f8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360508546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2360508546
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.957010529
Short name T1230
Test name
Test status
Simulation time 2230542800 ps
CPU time 75.56 seconds
Started Jun 27 05:08:32 PM PDT 24
Finished Jun 27 05:09:48 PM PDT 24
Peak memory 261120 kb
Host smart-7278e121-e109-47f2-8e27-4c049b77e987
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957010529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_bit_bash.957010529
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2601615039
Short name T299
Test name
Test status
Simulation time 57075900 ps
CPU time 30.14 seconds
Started Jun 27 05:08:45 PM PDT 24
Finished Jun 27 05:09:16 PM PDT 24
Peak memory 263088 kb
Host smart-565aaebc-d079-419f-8c2a-f681cd60ae57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601615039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.2601615039
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1931345332
Short name T1216
Test name
Test status
Simulation time 88371600 ps
CPU time 18.4 seconds
Started Jun 27 05:08:32 PM PDT 24
Finished Jun 27 05:08:51 PM PDT 24
Peak memory 271896 kb
Host smart-9ad80d83-5208-4623-b15c-cfe991698149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931345332 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1931345332
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.836105588
Short name T1218
Test name
Test status
Simulation time 150635900 ps
CPU time 15.77 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:04 PM PDT 24
Peak memory 263568 kb
Host smart-3b19e57d-df4e-46c1-b1d2-9a32a2451cd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836105588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_csr_rw.836105588
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1478351222
Short name T1201
Test name
Test status
Simulation time 17659700 ps
CPU time 14.58 seconds
Started Jun 27 05:08:33 PM PDT 24
Finished Jun 27 05:08:49 PM PDT 24
Peak memory 260996 kb
Host smart-2679803f-a539-4f17-b730-1abd463d472b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478351222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1
478351222
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4040650784
Short name T1116
Test name
Test status
Simulation time 28556800 ps
CPU time 14.11 seconds
Started Jun 27 05:08:29 PM PDT 24
Finished Jun 27 05:08:44 PM PDT 24
Peak memory 260896 kb
Host smart-1064f3a8-6bc3-4ae2-b206-27de621e5922
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040650784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.4040650784
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1905138128
Short name T1196
Test name
Test status
Simulation time 162419000 ps
CPU time 19.74 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:09 PM PDT 24
Peak memory 261372 kb
Host smart-827b93a1-3704-42a7-8e33-2111fdc305f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905138128 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1905138128
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2325825721
Short name T1182
Test name
Test status
Simulation time 42306200 ps
CPU time 16.19 seconds
Started Jun 27 05:08:33 PM PDT 24
Finished Jun 27 05:08:50 PM PDT 24
Peak memory 252860 kb
Host smart-a5ec1964-84df-41e2-8bb7-aaecba34e1c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325825721 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2325825721
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3801597293
Short name T1221
Test name
Test status
Simulation time 39826400 ps
CPU time 15.94 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:08:48 PM PDT 24
Peak memory 252852 kb
Host smart-63750bf6-514b-47bc-b920-91ed9ea4d409
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801597293 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3801597293
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1553628926
Short name T253
Test name
Test status
Simulation time 55533300 ps
CPU time 18.23 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:08:50 PM PDT 24
Peak memory 263676 kb
Host smart-dc9fa79f-d5b2-4f8a-b3cd-3d25f089b8d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553628926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1
553628926
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1244594982
Short name T1144
Test name
Test status
Simulation time 265109800 ps
CPU time 19.84 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:10 PM PDT 24
Peak memory 270516 kb
Host smart-0512470f-6430-41bf-bdc1-9b039d7f5a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244594982 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1244594982
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.557762590
Short name T1242
Test name
Test status
Simulation time 356107900 ps
CPU time 17.06 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:07 PM PDT 24
Peak memory 263576 kb
Host smart-d2039fd6-0871-489a-9df2-8929842980f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557762590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.557762590
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1020259633
Short name T1163
Test name
Test status
Simulation time 47919000 ps
CPU time 13.5 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:05 PM PDT 24
Peak memory 260916 kb
Host smart-9893780a-3293-4fe1-8f04-1dd23ca8e6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020259633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1020259633
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.665202569
Short name T1202
Test name
Test status
Simulation time 413400500 ps
CPU time 16.14 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 262964 kb
Host smart-21ca7a80-7217-493a-9963-6e7a1a11c56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665202569 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.665202569
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1900977155
Short name T1120
Test name
Test status
Simulation time 21005400 ps
CPU time 13.26 seconds
Started Jun 27 05:09:47 PM PDT 24
Finished Jun 27 05:10:02 PM PDT 24
Peak memory 252808 kb
Host smart-2812cc83-5e7c-4b0c-bc8e-83e6584485af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900977155 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1900977155
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3853097543
Short name T1167
Test name
Test status
Simulation time 23959500 ps
CPU time 15.69 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 252732 kb
Host smart-4f8b85de-57ae-463c-a9a1-7d1fbc27fc88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853097543 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3853097543
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1619363070
Short name T204
Test name
Test status
Simulation time 473613700 ps
CPU time 459.23 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:17:30 PM PDT 24
Peak memory 263652 kb
Host smart-4961066e-e583-40e9-9c93-e2d40dd66534
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619363070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.1619363070
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.776947956
Short name T1189
Test name
Test status
Simulation time 109304300 ps
CPU time 16.99 seconds
Started Jun 27 05:09:47 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 263708 kb
Host smart-987e97db-aa58-4ad6-90e3-00e2f29ee2b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776947956 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.776947956
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1744092414
Short name T1235
Test name
Test status
Simulation time 40692400 ps
CPU time 16.66 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:07 PM PDT 24
Peak memory 263548 kb
Host smart-736ae531-15fe-4c7b-bbe9-22a3c6d5be7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744092414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1744092414
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.800633282
Short name T329
Test name
Test status
Simulation time 25582300 ps
CPU time 13.44 seconds
Started Jun 27 05:09:50 PM PDT 24
Finished Jun 27 05:10:05 PM PDT 24
Peak memory 261008 kb
Host smart-b39f59ba-4871-44c8-a24c-aad224a32e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800633282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.800633282
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3728189097
Short name T1160
Test name
Test status
Simulation time 64136600 ps
CPU time 35.02 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:25 PM PDT 24
Peak memory 263876 kb
Host smart-39c92592-7393-4b4e-b0a4-7a49f7362c2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728189097 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3728189097
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.974832630
Short name T1212
Test name
Test status
Simulation time 41525300 ps
CPU time 13.8 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:05 PM PDT 24
Peak memory 252820 kb
Host smart-cf4a7f3d-d604-4013-bb95-d5662b21d8b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974832630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.974832630
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1984000721
Short name T1158
Test name
Test status
Simulation time 54801400 ps
CPU time 15.83 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:07 PM PDT 24
Peak memory 252848 kb
Host smart-bd037b9a-5a89-4938-b005-266bae09708e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984000721 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.1984000721
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.547016268
Short name T250
Test name
Test status
Simulation time 71228500 ps
CPU time 16.29 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 263672 kb
Host smart-259248ee-2616-49d0-8d17-1b50ecd94f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547016268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.547016268
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3945514472
Short name T71
Test name
Test status
Simulation time 175369600 ps
CPU time 15.78 seconds
Started Jun 27 05:10:18 PM PDT 24
Finished Jun 27 05:10:36 PM PDT 24
Peak memory 270084 kb
Host smart-88fa6c49-3eea-4804-a001-d00aa6df9bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945514472 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.3945514472
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1025640168
Short name T1171
Test name
Test status
Simulation time 64500100 ps
CPU time 14.79 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:33 PM PDT 24
Peak memory 263568 kb
Host smart-d38374b8-0440-4a19-a302-d266ab450d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025640168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1025640168
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3079693245
Short name T294
Test name
Test status
Simulation time 860197700 ps
CPU time 16.47 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 263600 kb
Host smart-b1eafd94-c07c-47b9-8072-2e8f8c5b2ae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079693245 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3079693245
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4212712253
Short name T1121
Test name
Test status
Simulation time 53067900 ps
CPU time 15.49 seconds
Started Jun 27 05:09:47 PM PDT 24
Finished Jun 27 05:10:04 PM PDT 24
Peak memory 252812 kb
Host smart-396cff52-d87e-4335-ae3c-834ff16ec983
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212712253 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.4212712253
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1365619160
Short name T1127
Test name
Test status
Simulation time 158438400 ps
CPU time 15.83 seconds
Started Jun 27 05:09:48 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 252904 kb
Host smart-b76b3b25-5c01-4c03-a4df-e41f03eac16c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365619160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1365619160
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3151995683
Short name T372
Test name
Test status
Simulation time 827661700 ps
CPU time 900.46 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:24:51 PM PDT 24
Peak memory 263696 kb
Host smart-7c9778f9-fab5-4cb8-bb9d-6ff3946c6761
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151995683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.3151995683
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1264042864
Short name T298
Test name
Test status
Simulation time 412755000 ps
CPU time 19.3 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:40 PM PDT 24
Peak memory 271904 kb
Host smart-1325431f-76fb-4eec-abbd-701d67106def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264042864 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1264042864
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4199228823
Short name T1136
Test name
Test status
Simulation time 37113800 ps
CPU time 16.63 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 263556 kb
Host smart-2b86f9ff-8337-4150-baa4-fe33336f28c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199228823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.4199228823
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.593217357
Short name T330
Test name
Test status
Simulation time 18043800 ps
CPU time 14.09 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:32 PM PDT 24
Peak memory 261068 kb
Host smart-eb3838af-736d-4ab6-bc29-2cde79d69262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593217357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.593217357
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1290536465
Short name T1135
Test name
Test status
Simulation time 128010900 ps
CPU time 32.55 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 263064 kb
Host smart-b343b337-91e6-4b2b-a66d-b36aa5e81dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290536465 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1290536465
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.468717993
Short name T1155
Test name
Test status
Simulation time 23162800 ps
CPU time 15.79 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:36 PM PDT 24
Peak memory 252880 kb
Host smart-71f38d1c-3d0a-4ede-8c90-9e1261855648
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468717993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.468717993
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.938245910
Short name T1183
Test name
Test status
Simulation time 11633600 ps
CPU time 16.64 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 252864 kb
Host smart-c3df56b6-9de5-4453-8d19-f253ff73d2e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938245910 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.938245910
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3156953534
Short name T234
Test name
Test status
Simulation time 44141800 ps
CPU time 16.89 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:38 PM PDT 24
Peak memory 263620 kb
Host smart-4b6ef0f5-7f8e-4352-8dd1-1f652f57eb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156953534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3156953534
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3495103555
Short name T1239
Test name
Test status
Simulation time 1456923700 ps
CPU time 458.08 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:17:56 PM PDT 24
Peak memory 263600 kb
Host smart-03252d4c-e968-4493-acfd-749fe2fbf47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495103555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3495103555
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2960095160
Short name T246
Test name
Test status
Simulation time 96858400 ps
CPU time 18 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:39 PM PDT 24
Peak memory 271828 kb
Host smart-e2a80385-4e17-4373-bba5-ec75f9ecc3b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960095160 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.2960095160
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3216248599
Short name T1224
Test name
Test status
Simulation time 53445000 ps
CPU time 14.55 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:31 PM PDT 24
Peak memory 260940 kb
Host smart-b6bf3201-eff2-478b-b5c9-cd5d77003b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216248599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3216248599
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3848371626
Short name T327
Test name
Test status
Simulation time 60594600 ps
CPU time 14.29 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:33 PM PDT 24
Peak memory 260892 kb
Host smart-e5ba3f6a-b615-4733-b3bb-dd42783c8e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848371626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3848371626
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1466976835
Short name T1210
Test name
Test status
Simulation time 82842500 ps
CPU time 16.7 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 261188 kb
Host smart-4564ea8c-14c9-49fe-a7a2-b3aae4c0f084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466976835 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1466976835
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2516404967
Short name T1205
Test name
Test status
Simulation time 46020900 ps
CPU time 15.66 seconds
Started Jun 27 05:10:22 PM PDT 24
Finished Jun 27 05:10:38 PM PDT 24
Peak memory 252744 kb
Host smart-9cf7ec1f-befb-465b-a7a4-d7bb850a398c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516404967 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2516404967
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2904737429
Short name T1130
Test name
Test status
Simulation time 13134300 ps
CPU time 16.58 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 253140 kb
Host smart-a40464d2-659e-44ef-a55c-d4e586458fa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904737429 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2904737429
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2508264642
Short name T1178
Test name
Test status
Simulation time 136628600 ps
CPU time 20.32 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:38 PM PDT 24
Peak memory 263676 kb
Host smart-99659b75-88c9-4a0f-b93e-9e719790375e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508264642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
2508264642
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3600618962
Short name T242
Test name
Test status
Simulation time 2275329900 ps
CPU time 747.11 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:22:44 PM PDT 24
Peak memory 263660 kb
Host smart-7ebc230d-3efb-4145-9433-086d32ac77b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600618962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3600618962
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3795160830
Short name T201
Test name
Test status
Simulation time 123420000 ps
CPU time 17.3 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 270360 kb
Host smart-1a112573-e180-433c-9692-99a62a8678a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795160830 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3795160830
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3538850609
Short name T292
Test name
Test status
Simulation time 67922400 ps
CPU time 18.05 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 261112 kb
Host smart-72eae3a2-f130-461c-b65c-c5df096aa6db
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538850609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.3538850609
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1397731706
Short name T1168
Test name
Test status
Simulation time 45370200 ps
CPU time 13.26 seconds
Started Jun 27 05:10:13 PM PDT 24
Finished Jun 27 05:10:27 PM PDT 24
Peak memory 260964 kb
Host smart-82de04d4-93d6-4359-b05d-04e8f9fd758f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397731706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
1397731706
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.509265879
Short name T1156
Test name
Test status
Simulation time 114328200 ps
CPU time 33.39 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 263652 kb
Host smart-e84bcb98-eb43-4b3c-a321-6262ddf1fb15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509265879 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.509265879
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.36767904
Short name T1128
Test name
Test status
Simulation time 24258100 ps
CPU time 15.94 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:37 PM PDT 24
Peak memory 252872 kb
Host smart-610138ff-2908-44cb-a04b-14bc16cd5457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.36767904
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1940316700
Short name T1119
Test name
Test status
Simulation time 15509900 ps
CPU time 14.27 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:31 PM PDT 24
Peak memory 252740 kb
Host smart-f465060b-4604-4665-a62d-452f132b3f14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940316700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1940316700
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1998617032
Short name T202
Test name
Test status
Simulation time 38313900 ps
CPU time 16.48 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 263660 kb
Host smart-cd27d398-f9b2-4ecb-9550-9748246f61ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998617032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1998617032
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.851050428
Short name T297
Test name
Test status
Simulation time 71086900 ps
CPU time 17.77 seconds
Started Jun 27 05:10:20 PM PDT 24
Finished Jun 27 05:10:39 PM PDT 24
Peak memory 263700 kb
Host smart-362ee325-ca0d-4b76-8f25-498f4ec5a73d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851050428 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.851050428
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3190014995
Short name T69
Test name
Test status
Simulation time 344097300 ps
CPU time 18.03 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:37 PM PDT 24
Peak memory 263580 kb
Host smart-495e5923-4673-4d99-8ea6-b7e736cc32d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190014995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.3190014995
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4172939401
Short name T1151
Test name
Test status
Simulation time 15651000 ps
CPU time 13.61 seconds
Started Jun 27 05:10:14 PM PDT 24
Finished Jun 27 05:10:29 PM PDT 24
Peak memory 261004 kb
Host smart-0f1f6c4f-8a0d-4464-b1a0-cccece134fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172939401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
4172939401
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3941581279
Short name T1213
Test name
Test status
Simulation time 125556800 ps
CPU time 34.84 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 261212 kb
Host smart-55b30572-5099-43c2-8262-a61b5fdc4275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941581279 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3941581279
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1490848360
Short name T1159
Test name
Test status
Simulation time 13702300 ps
CPU time 15.61 seconds
Started Jun 27 05:10:14 PM PDT 24
Finished Jun 27 05:10:31 PM PDT 24
Peak memory 252868 kb
Host smart-8f37d7b3-eed1-4c41-8ff9-55f447f29b9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490848360 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1490848360
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2583339960
Short name T1162
Test name
Test status
Simulation time 45564800 ps
CPU time 16.05 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 252756 kb
Host smart-c808e955-cc6a-4fa6-8fed-dc41c4780880
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583339960 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2583339960
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4083960509
Short name T374
Test name
Test status
Simulation time 3089435100 ps
CPU time 901.67 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:25:21 PM PDT 24
Peak memory 263900 kb
Host smart-a7c78839-0ab3-49c3-965d-c434f1868f06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083960509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.4083960509
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2154296977
Short name T1211
Test name
Test status
Simulation time 25650700 ps
CPU time 17.89 seconds
Started Jun 27 05:10:14 PM PDT 24
Finished Jun 27 05:10:33 PM PDT 24
Peak memory 271884 kb
Host smart-6e9b7f96-da92-46b2-8f21-2d98cec7169b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154296977 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.2154296977
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2204772971
Short name T1174
Test name
Test status
Simulation time 31858400 ps
CPU time 16.55 seconds
Started Jun 27 05:10:22 PM PDT 24
Finished Jun 27 05:10:39 PM PDT 24
Peak memory 260924 kb
Host smart-5c864bee-154b-4ef5-ac04-e3a991309ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204772971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2204772971
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.658999209
Short name T1129
Test name
Test status
Simulation time 16830700 ps
CPU time 13.41 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:10:32 PM PDT 24
Peak memory 260968 kb
Host smart-5d2ae115-b5b2-4df8-abb1-8727f8903d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658999209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.658999209
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.503064469
Short name T1219
Test name
Test status
Simulation time 40726300 ps
CPU time 18.76 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 263316 kb
Host smart-8e63f7e0-366a-4a4c-8396-e80f2fe290a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503064469 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.503064469
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2110433710
Short name T1133
Test name
Test status
Simulation time 30636600 ps
CPU time 13.23 seconds
Started Jun 27 05:10:14 PM PDT 24
Finished Jun 27 05:10:29 PM PDT 24
Peak memory 252812 kb
Host smart-5eddfda9-fd60-4156-9dcc-b209dfe3f3dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110433710 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2110433710
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1618562284
Short name T1124
Test name
Test status
Simulation time 19803300 ps
CPU time 15.57 seconds
Started Jun 27 05:10:18 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 252844 kb
Host smart-538ce7d5-7198-435e-8782-102bc4a1eccf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618562284 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1618562284
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.57765803
Short name T203
Test name
Test status
Simulation time 65145200 ps
CPU time 16.51 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 263612 kb
Host smart-30c77cf2-e1c6-426b-b0a8-ce883f953c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57765803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.57765803
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2737818806
Short name T254
Test name
Test status
Simulation time 92851400 ps
CPU time 16.79 seconds
Started Jun 27 05:10:13 PM PDT 24
Finished Jun 27 05:10:31 PM PDT 24
Peak memory 271868 kb
Host smart-0f33c0b6-9fc8-4029-92b4-85f126bc6bb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737818806 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2737818806
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3367397036
Short name T1214
Test name
Test status
Simulation time 50615100 ps
CPU time 17.83 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:36 PM PDT 24
Peak memory 260960 kb
Host smart-fc877f19-e6ab-426e-9c5b-e842ca0d60bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367397036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.3367397036
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.761399888
Short name T325
Test name
Test status
Simulation time 68451100 ps
CPU time 13.62 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:32 PM PDT 24
Peak memory 261024 kb
Host smart-76ace121-9cd1-4ee7-98da-806af59430fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761399888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.761399888
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1837754773
Short name T1137
Test name
Test status
Simulation time 233398100 ps
CPU time 33.93 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 263704 kb
Host smart-7d51a9be-cfc4-4009-8a8b-20f1d105e31c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837754773 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1837754773
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1922355839
Short name T1181
Test name
Test status
Simulation time 18270900 ps
CPU time 13.18 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:31 PM PDT 24
Peak memory 252896 kb
Host smart-f6590a31-9e03-4ae2-b91b-64faf2d544db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922355839 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.1922355839
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1365479300
Short name T1226
Test name
Test status
Simulation time 22334600 ps
CPU time 13.71 seconds
Started Jun 27 05:10:22 PM PDT 24
Finished Jun 27 05:10:36 PM PDT 24
Peak memory 252704 kb
Host smart-1ff95ea4-6770-498c-880a-d165053a143c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365479300 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1365479300
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.1366123074
Short name T244
Test name
Test status
Simulation time 66575900 ps
CPU time 21.18 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:40 PM PDT 24
Peak memory 263404 kb
Host smart-557c3d74-42e4-45a3-a893-cbe19379e493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366123074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
1366123074
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3059176342
Short name T376
Test name
Test status
Simulation time 858170300 ps
CPU time 452.51 seconds
Started Jun 27 05:10:17 PM PDT 24
Finished Jun 27 05:17:52 PM PDT 24
Peak memory 263644 kb
Host smart-faa25fee-efaa-4a0f-81d4-1b5e9873dc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059176342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3059176342
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.865263772
Short name T252
Test name
Test status
Simulation time 140012300 ps
CPU time 16.15 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 271872 kb
Host smart-130454ce-51e7-4ebf-95f3-56879cdbae52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865263772 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.865263772
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1246887564
Short name T1154
Test name
Test status
Simulation time 58345700 ps
CPU time 17.94 seconds
Started Jun 27 05:10:20 PM PDT 24
Finished Jun 27 05:10:40 PM PDT 24
Peak memory 263588 kb
Host smart-dd717789-79ce-498c-8112-2101abb14ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246887564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1246887564
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.68365757
Short name T1207
Test name
Test status
Simulation time 15635700 ps
CPU time 14.01 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 260988 kb
Host smart-e03a29bd-6243-430f-a249-401c4439bd14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68365757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.68365757
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1716073344
Short name T1138
Test name
Test status
Simulation time 75765600 ps
CPU time 19.5 seconds
Started Jun 27 05:10:40 PM PDT 24
Finished Jun 27 05:11:01 PM PDT 24
Peak memory 261168 kb
Host smart-4f931a34-711f-43fb-9cac-35f3a48b754e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716073344 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.1716073344
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3483829049
Short name T1122
Test name
Test status
Simulation time 22633700 ps
CPU time 15.64 seconds
Started Jun 27 05:10:16 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 252904 kb
Host smart-1380cab6-d5fe-4325-858c-61623f450034
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483829049 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3483829049
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1719802239
Short name T1179
Test name
Test status
Simulation time 14454300 ps
CPU time 13.93 seconds
Started Jun 27 05:10:19 PM PDT 24
Finished Jun 27 05:10:35 PM PDT 24
Peak memory 252944 kb
Host smart-93a8a9f9-4a0a-442a-8a4c-093e8c5bae1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719802239 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.1719802239
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.316464097
Short name T1215
Test name
Test status
Simulation time 152085300 ps
CPU time 16.32 seconds
Started Jun 27 05:10:15 PM PDT 24
Finished Jun 27 05:10:34 PM PDT 24
Peak memory 263584 kb
Host smart-bc3a751a-d458-4da4-8849-451d00c94608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316464097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.316464097
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2615870012
Short name T1227
Test name
Test status
Simulation time 3092877800 ps
CPU time 55.24 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:44 PM PDT 24
Peak memory 261104 kb
Host smart-99d053cb-9916-4799-8206-c13272ed5fc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615870012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.2615870012
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1611236327
Short name T290
Test name
Test status
Simulation time 2848103100 ps
CPU time 71.5 seconds
Started Jun 27 05:08:38 PM PDT 24
Finished Jun 27 05:09:50 PM PDT 24
Peak memory 261116 kb
Host smart-62c20444-46d6-49f2-bc79-fa15e48066e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611236327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1611236327
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1416492564
Short name T1170
Test name
Test status
Simulation time 90448700 ps
CPU time 46.08 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:09:18 PM PDT 24
Peak memory 261072 kb
Host smart-530d1cae-ba3e-4ca9-8014-14c5bb9b06f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416492564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1416492564
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.389540349
Short name T1240
Test name
Test status
Simulation time 75360400 ps
CPU time 20 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:08:52 PM PDT 24
Peak memory 271916 kb
Host smart-5427d917-224c-46e7-93a5-117c21a8cd94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389540349 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.389540349
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3111082333
Short name T1209
Test name
Test status
Simulation time 79688500 ps
CPU time 14.15 seconds
Started Jun 27 05:08:31 PM PDT 24
Finished Jun 27 05:08:46 PM PDT 24
Peak memory 263564 kb
Host smart-a2d0ca48-1a50-4c8e-a191-4abbc797329e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111082333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3111082333
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.872475129
Short name T1198
Test name
Test status
Simulation time 15281200 ps
CPU time 13.42 seconds
Started Jun 27 05:08:33 PM PDT 24
Finished Jun 27 05:08:47 PM PDT 24
Peak memory 260956 kb
Host smart-796723e1-7a78-41d8-9c56-4ce371decbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872475129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.872475129
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.641805499
Short name T270
Test name
Test status
Simulation time 39957200 ps
CPU time 13.7 seconds
Started Jun 27 05:08:38 PM PDT 24
Finished Jun 27 05:08:52 PM PDT 24
Peak memory 262692 kb
Host smart-3654d92b-0316-4af5-9c0b-d46301d06e49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641805499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_mem_partial_access.641805499
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.173966750
Short name T1238
Test name
Test status
Simulation time 42184200 ps
CPU time 14.11 seconds
Started Jun 27 05:08:38 PM PDT 24
Finished Jun 27 05:08:53 PM PDT 24
Peak memory 260888 kb
Host smart-b108a54a-79a2-4553-860e-122925745d37
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173966750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.173966750
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.4134938824
Short name T230
Test name
Test status
Simulation time 67257800 ps
CPU time 18.49 seconds
Started Jun 27 05:08:46 PM PDT 24
Finished Jun 27 05:09:06 PM PDT 24
Peak memory 262820 kb
Host smart-7c426ae3-d1a5-40a3-b1c8-5793380d431d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134938824 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.4134938824
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.318716642
Short name T1200
Test name
Test status
Simulation time 83940800 ps
CPU time 13.33 seconds
Started Jun 27 05:08:32 PM PDT 24
Finished Jun 27 05:08:46 PM PDT 24
Peak memory 252876 kb
Host smart-e6cb92b0-7109-4c5c-9db7-a8544db3feca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318716642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.318716642
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3906828381
Short name T1131
Test name
Test status
Simulation time 22123000 ps
CPU time 15.34 seconds
Started Jun 27 05:08:47 PM PDT 24
Finished Jun 27 05:09:04 PM PDT 24
Peak memory 252772 kb
Host smart-056b0255-a49c-4be2-9f9f-3dab48dc4826
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906828381 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3906828381
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2400806521
Short name T255
Test name
Test status
Simulation time 794313100 ps
CPU time 458.76 seconds
Started Jun 27 05:08:38 PM PDT 24
Finished Jun 27 05:16:17 PM PDT 24
Peak memory 263664 kb
Host smart-aa52f59d-f932-46f5-991a-cfd26a0682cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400806521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2400806521
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1435538251
Short name T1157
Test name
Test status
Simulation time 132410600 ps
CPU time 13.6 seconds
Started Jun 27 05:10:36 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 261020 kb
Host smart-531d6c4c-6615-473a-a349-c727798581cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435538251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
1435538251
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1189645708
Short name T1145
Test name
Test status
Simulation time 17685700 ps
CPU time 13.4 seconds
Started Jun 27 05:10:37 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 260924 kb
Host smart-a763490b-03a1-469b-9c99-b89fdbe5fe2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189645708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
1189645708
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1371490835
Short name T1203
Test name
Test status
Simulation time 188698400 ps
CPU time 13.64 seconds
Started Jun 27 05:10:36 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 261116 kb
Host smart-10b7f92b-fcf9-4d85-92b9-82b2ec5fe008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371490835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
1371490835
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.753475576
Short name T1173
Test name
Test status
Simulation time 31388500 ps
CPU time 13.3 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 261032 kb
Host smart-2036a19c-2528-453a-bed1-ca7cf5cd89f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753475576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.753475576
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1258220661
Short name T1161
Test name
Test status
Simulation time 29386600 ps
CPU time 13.27 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:50 PM PDT 24
Peak memory 260896 kb
Host smart-0d257ac5-a438-4a6b-bd91-e7e78679bc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258220661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
1258220661
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2325253040
Short name T1232
Test name
Test status
Simulation time 15849600 ps
CPU time 14.13 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260948 kb
Host smart-ec707290-8590-4a45-b254-5510d5b47af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325253040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
2325253040
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1295854466
Short name T1231
Test name
Test status
Simulation time 81553800 ps
CPU time 13.95 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260980 kb
Host smart-c478e46c-3c43-49e7-9a57-3909844bd921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295854466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
1295854466
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.754168309
Short name T1142
Test name
Test status
Simulation time 184735900 ps
CPU time 13.83 seconds
Started Jun 27 05:10:33 PM PDT 24
Finished Jun 27 05:10:48 PM PDT 24
Peak memory 261120 kb
Host smart-48bd9018-ed65-4fed-bd46-2e5371c4087b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754168309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.754168309
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2317976991
Short name T1243
Test name
Test status
Simulation time 17080500 ps
CPU time 14.02 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:10:54 PM PDT 24
Peak memory 260956 kb
Host smart-ed3dddc5-3dde-4584-a7d4-2fe9f8077793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317976991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2317976991
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2390233854
Short name T231
Test name
Test status
Simulation time 1243993100 ps
CPU time 62.52 seconds
Started Jun 27 05:08:51 PM PDT 24
Finished Jun 27 05:09:55 PM PDT 24
Peak memory 261092 kb
Host smart-7b618d41-ec58-4eb6-96a5-6a0034e113a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390233854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2390233854
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.398042560
Short name T1229
Test name
Test status
Simulation time 6424131400 ps
CPU time 92.43 seconds
Started Jun 27 05:08:50 PM PDT 24
Finished Jun 27 05:10:25 PM PDT 24
Peak memory 261068 kb
Host smart-70cbe0df-eac6-4b3d-b6fd-fb5bcc0550ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398042560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_bit_bash.398042560
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3767128208
Short name T288
Test name
Test status
Simulation time 39551600 ps
CPU time 25.48 seconds
Started Jun 27 05:08:49 PM PDT 24
Finished Jun 27 05:09:17 PM PDT 24
Peak memory 261132 kb
Host smart-dd6cd397-30cb-4ed0-a5a2-693d7540b674
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767128208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3767128208
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1624643931
Short name T256
Test name
Test status
Simulation time 54098800 ps
CPU time 15.46 seconds
Started Jun 27 05:08:49 PM PDT 24
Finished Jun 27 05:09:06 PM PDT 24
Peak memory 277808 kb
Host smart-a487886c-1eba-4643-b316-6c08f07a98c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624643931 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1624643931
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.752484713
Short name T228
Test name
Test status
Simulation time 60617100 ps
CPU time 16.65 seconds
Started Jun 27 05:08:50 PM PDT 24
Finished Jun 27 05:09:08 PM PDT 24
Peak memory 263312 kb
Host smart-016feb4a-6970-4e4c-8428-d325a01fdb06
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752484713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_csr_rw.752484713
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2555318383
Short name T1150
Test name
Test status
Simulation time 80394100 ps
CPU time 13.3 seconds
Started Jun 27 05:08:50 PM PDT 24
Finished Jun 27 05:09:05 PM PDT 24
Peak memory 260972 kb
Host smart-e11579bb-ff7c-4452-9af3-d4aef6bad619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555318383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2
555318383
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.84326981
Short name T268
Test name
Test status
Simulation time 32082600 ps
CPU time 13.58 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:03 PM PDT 24
Peak memory 262000 kb
Host smart-c97f86f5-efd5-49ea-85bb-c7401eb3be8a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84326981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_mem_partial_access.84326981
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2542353784
Short name T1241
Test name
Test status
Simulation time 39674600 ps
CPU time 13.31 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:03 PM PDT 24
Peak memory 260924 kb
Host smart-750acc79-b250-4266-a5f4-c90dccfc41f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542353784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2542353784
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3463486077
Short name T1244
Test name
Test status
Simulation time 725732300 ps
CPU time 21.41 seconds
Started Jun 27 05:08:54 PM PDT 24
Finished Jun 27 05:09:16 PM PDT 24
Peak memory 263676 kb
Host smart-ec3946a0-6878-4a5c-88a0-de5c84af58cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463486077 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3463486077
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2975400356
Short name T1125
Test name
Test status
Simulation time 140092200 ps
CPU time 15.97 seconds
Started Jun 27 05:08:50 PM PDT 24
Finished Jun 27 05:09:08 PM PDT 24
Peak memory 252860 kb
Host smart-dea2a001-bc91-4a39-9318-1d646f8c56b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975400356 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2975400356
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.57362289
Short name T1169
Test name
Test status
Simulation time 44448900 ps
CPU time 15.32 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:05 PM PDT 24
Peak memory 252956 kb
Host smart-b99f2680-712b-41c7-adcf-9f0cc2d5d633
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57362289 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.57362289
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1520817120
Short name T1141
Test name
Test status
Simulation time 65271600 ps
CPU time 16.9 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 263616 kb
Host smart-9405327e-1f39-4f51-8986-a91eab393c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520817120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
520817120
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2581019659
Short name T1197
Test name
Test status
Simulation time 2026829300 ps
CPU time 382.45 seconds
Started Jun 27 05:08:51 PM PDT 24
Finished Jun 27 05:15:15 PM PDT 24
Peak memory 263552 kb
Host smart-515d4b7c-640a-4b72-b464-0658ab948ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581019659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2581019659
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2868692617
Short name T237
Test name
Test status
Simulation time 14534800 ps
CPU time 13.8 seconds
Started Jun 27 05:10:33 PM PDT 24
Finished Jun 27 05:10:48 PM PDT 24
Peak memory 260992 kb
Host smart-a3dd6001-8195-4c52-b397-9352a40e92ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868692617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
2868692617
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3835542483
Short name T332
Test name
Test status
Simulation time 17239500 ps
CPU time 13.29 seconds
Started Jun 27 05:10:36 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260956 kb
Host smart-33a26237-9811-4b47-bae3-6d4b21eab613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835542483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3835542483
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1684132771
Short name T1175
Test name
Test status
Simulation time 55900500 ps
CPU time 13.42 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:50 PM PDT 24
Peak memory 261064 kb
Host smart-b2d049be-a579-4770-94a5-6d7fb444d66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684132771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1684132771
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3934954521
Short name T1194
Test name
Test status
Simulation time 18219700 ps
CPU time 13.29 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 260988 kb
Host smart-9596e8c9-5b24-4c98-808a-bc1f0eccc713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934954521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3934954521
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2228562998
Short name T1187
Test name
Test status
Simulation time 15534600 ps
CPU time 13.58 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 05:10:54 PM PDT 24
Peak memory 261004 kb
Host smart-99b6fe87-521f-49a0-9a72-ca9ab67487e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228562998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
2228562998
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1634367430
Short name T1220
Test name
Test status
Simulation time 29065100 ps
CPU time 13.39 seconds
Started Jun 27 05:10:36 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260976 kb
Host smart-5ad8055e-c36b-49c1-9f88-e086a04961e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634367430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1634367430
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3527479520
Short name T1208
Test name
Test status
Simulation time 18111800 ps
CPU time 13.44 seconds
Started Jun 27 05:10:41 PM PDT 24
Finished Jun 27 05:10:55 PM PDT 24
Peak memory 261040 kb
Host smart-8529fe8c-e77d-496f-8489-9d9ebbf78004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527479520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3527479520
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1961203745
Short name T326
Test name
Test status
Simulation time 60516600 ps
CPU time 13.51 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:50 PM PDT 24
Peak memory 261112 kb
Host smart-4305adaa-22d9-45e0-a2bd-4987e3305466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961203745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1961203745
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.660383105
Short name T1152
Test name
Test status
Simulation time 23467300 ps
CPU time 13.99 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260956 kb
Host smart-46da4082-05e0-4265-a175-933d3b0edf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660383105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.660383105
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1437689370
Short name T1188
Test name
Test status
Simulation time 1757479100 ps
CPU time 56.56 seconds
Started Jun 27 05:08:47 PM PDT 24
Finished Jun 27 05:09:46 PM PDT 24
Peak memory 261144 kb
Host smart-d9ae481b-2a2d-4ed7-af67-c51d2def81c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437689370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1437689370
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2485996829
Short name T1126
Test name
Test status
Simulation time 2283461600 ps
CPU time 77.82 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:10:08 PM PDT 24
Peak memory 261048 kb
Host smart-fce431c6-998d-4ec9-8f97-5e9b76d454e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485996829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2485996829
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.667662222
Short name T1147
Test name
Test status
Simulation time 85458700 ps
CPU time 46.2 seconds
Started Jun 27 05:08:49 PM PDT 24
Finished Jun 27 05:09:37 PM PDT 24
Peak memory 261048 kb
Host smart-499fd2ad-6df8-4ca7-a389-1d9860fcabd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667662222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.667662222
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1597723815
Short name T1228
Test name
Test status
Simulation time 96572500 ps
CPU time 17.26 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 261100 kb
Host smart-c88483fc-dd08-48dd-aad3-f2de82e2fca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597723815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.1597723815
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.16508271
Short name T370
Test name
Test status
Simulation time 51777300 ps
CPU time 13.22 seconds
Started Jun 27 05:08:49 PM PDT 24
Finished Jun 27 05:09:04 PM PDT 24
Peak memory 260776 kb
Host smart-80388225-5651-4103-88e7-b6c725826755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.16508271
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.784804592
Short name T269
Test name
Test status
Simulation time 29366300 ps
CPU time 13.45 seconds
Started Jun 27 05:08:47 PM PDT 24
Finished Jun 27 05:09:02 PM PDT 24
Peak memory 262844 kb
Host smart-0dd47e52-beba-41e4-a0ab-bc23c485ef04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784804592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.784804592
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.206041825
Short name T1172
Test name
Test status
Simulation time 48138500 ps
CPU time 13.39 seconds
Started Jun 27 05:08:53 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 261108 kb
Host smart-7ed6535b-8bc7-4f48-bcf5-3a68e04860a0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206041825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.206041825
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1037747376
Short name T1195
Test name
Test status
Simulation time 271580500 ps
CPU time 19.78 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:09 PM PDT 24
Peak memory 263576 kb
Host smart-9047d22c-a262-49a6-a8cb-58a6a37ba331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037747376 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1037747376
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1785881101
Short name T1153
Test name
Test status
Simulation time 14277900 ps
CPU time 15.49 seconds
Started Jun 27 05:08:50 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 252932 kb
Host smart-9ef9e983-050f-4f9c-a320-d9e38d41873a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785881101 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.1785881101
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.881798342
Short name T1132
Test name
Test status
Simulation time 39842600 ps
CPU time 15.28 seconds
Started Jun 27 05:08:51 PM PDT 24
Finished Jun 27 05:09:08 PM PDT 24
Peak memory 252836 kb
Host smart-992a163a-75a6-4bfb-a372-2511a2b30400
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881798342 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.881798342
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.512886870
Short name T251
Test name
Test status
Simulation time 55480200 ps
CPU time 18.96 seconds
Started Jun 27 05:08:48 PM PDT 24
Finished Jun 27 05:09:09 PM PDT 24
Peak memory 263692 kb
Host smart-d5b70b3f-2ec9-4364-b18d-1ea048a9e10e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512886870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.512886870
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.15045461
Short name T291
Test name
Test status
Simulation time 3126528400 ps
CPU time 747.96 seconds
Started Jun 27 05:08:51 PM PDT 24
Finished Jun 27 05:21:21 PM PDT 24
Peak memory 263568 kb
Host smart-2b333230-f399-426e-9720-2e8a3785812c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15045461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_t
l_intg_err.15045461
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4143562260
Short name T1177
Test name
Test status
Simulation time 29790600 ps
CPU time 13.71 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:49 PM PDT 24
Peak memory 261072 kb
Host smart-7254eb79-7123-4022-be2b-4ca68ee12aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143562260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
4143562260
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1992152165
Short name T1245
Test name
Test status
Simulation time 35432100 ps
CPU time 13.89 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:50 PM PDT 24
Peak memory 260724 kb
Host smart-5e25511b-4f28-4250-a090-2f2fa4b15131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992152165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
1992152165
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2742979729
Short name T1217
Test name
Test status
Simulation time 19210400 ps
CPU time 13.4 seconds
Started Jun 27 05:10:41 PM PDT 24
Finished Jun 27 05:10:55 PM PDT 24
Peak memory 261040 kb
Host smart-501dd042-6c99-4d8c-a341-5eed8ce55808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742979729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
2742979729
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.841722409
Short name T1236
Test name
Test status
Simulation time 15827900 ps
CPU time 13.29 seconds
Started Jun 27 05:10:37 PM PDT 24
Finished Jun 27 05:10:52 PM PDT 24
Peak memory 260924 kb
Host smart-c746f784-0f4e-4102-91ad-75217ac2790a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841722409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.841722409
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3995461992
Short name T1237
Test name
Test status
Simulation time 55946800 ps
CPU time 13.58 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:49 PM PDT 24
Peak memory 261112 kb
Host smart-e9db0f17-5137-4ebd-8eee-8829de2962f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995461992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3995461992
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3728372829
Short name T333
Test name
Test status
Simulation time 15745600 ps
CPU time 13.35 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:49 PM PDT 24
Peak memory 261000 kb
Host smart-aae0da16-8be0-4e51-9b97-949a955e8b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728372829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3728372829
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1544213326
Short name T1146
Test name
Test status
Simulation time 17467100 ps
CPU time 13.66 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:10:51 PM PDT 24
Peak memory 260880 kb
Host smart-ec4637e0-faf5-47e1-949e-f4bd6fd9fca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544213326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1544213326
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2980264112
Short name T1192
Test name
Test status
Simulation time 181723400 ps
CPU time 13.48 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:10:53 PM PDT 24
Peak memory 261068 kb
Host smart-f2d9b579-e860-43ee-8784-88c89fdbcd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980264112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2980264112
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.388851934
Short name T328
Test name
Test status
Simulation time 17108600 ps
CPU time 13.45 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:10:49 PM PDT 24
Peak memory 261040 kb
Host smart-7b4abe9e-cde4-43b5-b962-4a3f21d90800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388851934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.388851934
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1708092421
Short name T1247
Test name
Test status
Simulation time 63047800 ps
CPU time 13.39 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:10:53 PM PDT 24
Peak memory 261096 kb
Host smart-c37bf5da-40d0-4fc5-87fe-0562a6754fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708092421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
1708092421
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1301284439
Short name T249
Test name
Test status
Simulation time 274975400 ps
CPU time 17.29 seconds
Started Jun 27 05:09:05 PM PDT 24
Finished Jun 27 05:09:23 PM PDT 24
Peak memory 263640 kb
Host smart-e3656cfc-4fd3-45d2-9b97-5ae8dc6ea340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301284439 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1301284439
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2136352789
Short name T1166
Test name
Test status
Simulation time 99790100 ps
CPU time 15.02 seconds
Started Jun 27 05:09:06 PM PDT 24
Finished Jun 27 05:09:21 PM PDT 24
Peak memory 261072 kb
Host smart-08543620-9b4c-40e9-b226-fbdf05d4966f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136352789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.2136352789
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2857185234
Short name T1139
Test name
Test status
Simulation time 57816600 ps
CPU time 13.2 seconds
Started Jun 27 05:09:06 PM PDT 24
Finished Jun 27 05:09:21 PM PDT 24
Peak memory 260880 kb
Host smart-8011b354-5d8c-43ba-a7ac-2f045a57e0de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857185234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
857185234
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1546955832
Short name T1233
Test name
Test status
Simulation time 614186800 ps
CPU time 18.71 seconds
Started Jun 27 05:09:10 PM PDT 24
Finished Jun 27 05:09:29 PM PDT 24
Peak memory 262840 kb
Host smart-730c1bb7-cdcb-4965-b057-b6c8bdee95cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546955832 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1546955832
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1921053812
Short name T1206
Test name
Test status
Simulation time 31483800 ps
CPU time 13.15 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:21 PM PDT 24
Peak memory 252924 kb
Host smart-7a9cf5ac-9495-4fdd-a2f5-b0b52fb2689f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921053812 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1921053812
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.193969997
Short name T1234
Test name
Test status
Simulation time 67510200 ps
CPU time 13.53 seconds
Started Jun 27 05:09:09 PM PDT 24
Finished Jun 27 05:09:23 PM PDT 24
Peak memory 252852 kb
Host smart-cd1db96d-755d-4ec5-b536-f64f42d26115
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193969997 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.193969997
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.967900484
Short name T324
Test name
Test status
Simulation time 491739500 ps
CPU time 16.21 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:25 PM PDT 24
Peak memory 263620 kb
Host smart-3250de54-9ff6-414a-b49e-4477d43eddcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967900484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.967900484
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3578429782
Short name T233
Test name
Test status
Simulation time 49307700 ps
CPU time 18.45 seconds
Started Jun 27 05:09:06 PM PDT 24
Finished Jun 27 05:09:26 PM PDT 24
Peak memory 272108 kb
Host smart-7fd90203-3610-4d8c-89ee-e27500822a8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578429782 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3578429782
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3531331086
Short name T227
Test name
Test status
Simulation time 277953100 ps
CPU time 18.59 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:27 PM PDT 24
Peak memory 263588 kb
Host smart-85a2f8ea-d6fc-4ee2-90b8-127b8b4af629
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531331086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3531331086
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.4278217071
Short name T1134
Test name
Test status
Simulation time 16214400 ps
CPU time 14 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:23 PM PDT 24
Peak memory 261048 kb
Host smart-fb5abdff-34e1-4fa2-8823-07c729a71ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278217071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.4
278217071
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.4011678873
Short name T1149
Test name
Test status
Simulation time 171015300 ps
CPU time 18.21 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:09:27 PM PDT 24
Peak memory 261076 kb
Host smart-d1b559a1-a712-4185-9377-4eb3901c3018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011678873 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.4011678873
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3205122364
Short name T1123
Test name
Test status
Simulation time 41275600 ps
CPU time 15.52 seconds
Started Jun 27 05:09:06 PM PDT 24
Finished Jun 27 05:09:22 PM PDT 24
Peak memory 252888 kb
Host smart-e9cb776f-c581-41de-9ce0-43ae658e2454
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205122364 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3205122364
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.321744463
Short name T1222
Test name
Test status
Simulation time 13057600 ps
CPU time 15.55 seconds
Started Jun 27 05:09:06 PM PDT 24
Finished Jun 27 05:09:22 PM PDT 24
Peak memory 252864 kb
Host smart-e2015bab-021d-49c8-bd4e-daa5d9a750b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321744463 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.321744463
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1784509913
Short name T373
Test name
Test status
Simulation time 415902800 ps
CPU time 883.24 seconds
Started Jun 27 05:09:07 PM PDT 24
Finished Jun 27 05:23:52 PM PDT 24
Peak memory 263636 kb
Host smart-248632f3-bd0b-4746-a29f-82c8ef182cce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784509913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.1784509913
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3777990081
Short name T300
Test name
Test status
Simulation time 171825400 ps
CPU time 17.2 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:44 PM PDT 24
Peak memory 270540 kb
Host smart-e2f0dae2-2d89-4800-815f-e2a8026edbeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777990081 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3777990081
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.916269803
Short name T1223
Test name
Test status
Simulation time 206190100 ps
CPU time 17.72 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:44 PM PDT 24
Peak memory 263408 kb
Host smart-dc2c06e5-7710-4b2d-8070-00b82caf1d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916269803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.916269803
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1743746167
Short name T1204
Test name
Test status
Simulation time 144223200 ps
CPU time 13.75 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:40 PM PDT 24
Peak memory 260892 kb
Host smart-d1b5e977-d2b1-422e-aadb-43e18e603fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743746167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1
743746167
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1002248437
Short name T278
Test name
Test status
Simulation time 38456600 ps
CPU time 17.45 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:42 PM PDT 24
Peak memory 263432 kb
Host smart-41a1245c-7288-4ca5-a933-b4afd2e0fe27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002248437 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1002248437
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2026469613
Short name T1191
Test name
Test status
Simulation time 13426500 ps
CPU time 13.57 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:41 PM PDT 24
Peak memory 252904 kb
Host smart-7f85d2f9-c2ac-467e-986f-4c0ecd1b3826
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026469613 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2026469613
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4233106925
Short name T1148
Test name
Test status
Simulation time 24147800 ps
CPU time 15.38 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:41 PM PDT 24
Peak memory 252888 kb
Host smart-b317237f-2fd7-4ebf-bc4a-5a3532d1cf84
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233106925 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.4233106925
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2959191035
Short name T245
Test name
Test status
Simulation time 351985000 ps
CPU time 20.38 seconds
Started Jun 27 05:09:08 PM PDT 24
Finished Jun 27 05:09:30 PM PDT 24
Peak memory 263660 kb
Host smart-2a26b34d-e1c8-4593-ad4f-c69acecb07c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959191035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
959191035
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2218509365
Short name T371
Test name
Test status
Simulation time 1972501900 ps
CPU time 387.53 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:15:54 PM PDT 24
Peak memory 263640 kb
Host smart-a65a562e-ab40-4006-aaaf-9a9908bc67d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218509365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2218509365
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1514658142
Short name T229
Test name
Test status
Simulation time 301858100 ps
CPU time 18.93 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:45 PM PDT 24
Peak memory 271908 kb
Host smart-97dd744c-402a-493c-bf30-27b4cebefbf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514658142 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1514658142
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3068258562
Short name T1164
Test name
Test status
Simulation time 39006100 ps
CPU time 17.22 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:44 PM PDT 24
Peak memory 261112 kb
Host smart-f4310ac9-97f1-47ce-99b4-48145e7282f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068258562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3068258562
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1146775216
Short name T331
Test name
Test status
Simulation time 14278600 ps
CPU time 13.55 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:40 PM PDT 24
Peak memory 260936 kb
Host smart-8627c7b2-2395-4f6c-a005-7ffda2bbafb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146775216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1
146775216
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.490585597
Short name T293
Test name
Test status
Simulation time 535728200 ps
CPU time 15.89 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:43 PM PDT 24
Peak memory 262564 kb
Host smart-504bef29-ca8d-4c7b-9157-76fddfdddb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490585597 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.490585597
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1198744082
Short name T1143
Test name
Test status
Simulation time 16685300 ps
CPU time 15.62 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:43 PM PDT 24
Peak memory 252912 kb
Host smart-4e1fe4c3-606c-411d-9963-e42cc78c2d58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198744082 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1198744082
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1293669623
Short name T1165
Test name
Test status
Simulation time 59414300 ps
CPU time 15.87 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:42 PM PDT 24
Peak memory 252760 kb
Host smart-f5b48818-4941-41b4-b3f5-ef67be564533
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293669623 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1293669623
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3725897560
Short name T100
Test name
Test status
Simulation time 100674600 ps
CPU time 18.9 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:43 PM PDT 24
Peak memory 263676 kb
Host smart-58918c9a-069e-4250-a368-b84017ecb7f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725897560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
725897560
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2599898552
Short name T295
Test name
Test status
Simulation time 1749812200 ps
CPU time 461.58 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:17:08 PM PDT 24
Peak memory 263660 kb
Host smart-ddbca0a5-049c-4950-9a40-dd88c64195d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599898552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2599898552
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1614907823
Short name T296
Test name
Test status
Simulation time 60208300 ps
CPU time 17.72 seconds
Started Jun 27 05:09:49 PM PDT 24
Finished Jun 27 05:10:09 PM PDT 24
Peak memory 276396 kb
Host smart-e9adef34-2e1e-4019-ae2d-0ae0d03fce4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614907823 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1614907823
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1813788198
Short name T276
Test name
Test status
Simulation time 50366200 ps
CPU time 14.32 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:41 PM PDT 24
Peak memory 263584 kb
Host smart-ba139a29-452f-435d-b400-1f217744827c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813788198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1813788198
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3182509637
Short name T1199
Test name
Test status
Simulation time 26843200 ps
CPU time 14.22 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:42 PM PDT 24
Peak memory 260980 kb
Host smart-4e0a1d17-9049-4b16-8e33-a2a89654f0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182509637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3
182509637
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.904474444
Short name T1184
Test name
Test status
Simulation time 916083400 ps
CPU time 17.63 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:43 PM PDT 24
Peak memory 262300 kb
Host smart-94e04be6-1a4e-4f3c-9738-509a457dbfeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904474444 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.904474444
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.830396689
Short name T1180
Test name
Test status
Simulation time 119374600 ps
CPU time 15.7 seconds
Started Jun 27 05:09:24 PM PDT 24
Finished Jun 27 05:09:40 PM PDT 24
Peak memory 252884 kb
Host smart-c40b7ac0-882d-4dd4-9519-38a4f83d1dcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830396689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.830396689
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.551077077
Short name T1185
Test name
Test status
Simulation time 28684300 ps
CPU time 15.39 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:09:42 PM PDT 24
Peak memory 252848 kb
Host smart-4d1a2d7d-30c9-4125-8557-4c1ac656a0b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551077077 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.551077077
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.441986853
Short name T239
Test name
Test status
Simulation time 62959400 ps
CPU time 20.31 seconds
Started Jun 27 05:09:26 PM PDT 24
Finished Jun 27 05:09:48 PM PDT 24
Peak memory 263596 kb
Host smart-ee60c7d3-3155-400e-aec4-34b7de52a3d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441986853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.441986853
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.674074333
Short name T243
Test name
Test status
Simulation time 346126600 ps
CPU time 900.64 seconds
Started Jun 27 05:09:25 PM PDT 24
Finished Jun 27 05:24:27 PM PDT 24
Peak memory 263672 kb
Host smart-34675bcc-df16-41e9-a39c-28524c4f9872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674074333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.674074333
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2885095670
Short name T1051
Test name
Test status
Simulation time 102761800 ps
CPU time 13.62 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:11:48 PM PDT 24
Peak memory 258564 kb
Host smart-6a7a30ab-50cb-46a2-9ada-63d4ff7aea9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885095670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
885095670
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3242063984
Short name T379
Test name
Test status
Simulation time 70013800 ps
CPU time 14.26 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:11:25 PM PDT 24
Peak memory 261724 kb
Host smart-7d87383e-f058-4fe2-9966-c6f5d89cb0f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242063984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3242063984
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.4221407981
Short name T1033
Test name
Test status
Simulation time 63610100 ps
CPU time 16.18 seconds
Started Jun 27 05:11:11 PM PDT 24
Finished Jun 27 05:11:28 PM PDT 24
Peak memory 275420 kb
Host smart-347b4dfd-d833-4de9-a4c7-a2d10c6be4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221407981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.4221407981
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.4122491470
Short name T795
Test name
Test status
Simulation time 182049400 ps
CPU time 102.55 seconds
Started Jun 27 05:10:52 PM PDT 24
Finished Jun 27 05:12:36 PM PDT 24
Peak memory 282232 kb
Host smart-c71c462f-a100-46f8-83fe-57a98b1de16f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122491470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.4122491470
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2668687075
Short name T138
Test name
Test status
Simulation time 20770119100 ps
CPU time 481.35 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:18:37 PM PDT 24
Peak memory 263784 kb
Host smart-a706f283-9594-4cd8-8fec-e416c5b1446d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668687075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2668687075
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.35701959
Short name T88
Test name
Test status
Simulation time 1897438500 ps
CPU time 2057.97 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:44:58 PM PDT 24
Peak memory 265384 kb
Host smart-3e29a47b-0c3a-4387-961b-6e5a1e4d2988
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35701959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_error_prog_type.35701959
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3211603166
Short name T899
Test name
Test status
Simulation time 1005394600 ps
CPU time 870.19 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:25:10 PM PDT 24
Peak memory 273700 kb
Host smart-a7def9db-032c-4568-88e7-92bccb1dad61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211603166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3211603166
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.4170625209
Short name T976
Test name
Test status
Simulation time 108795000 ps
CPU time 21.39 seconds
Started Jun 27 05:10:37 PM PDT 24
Finished Jun 27 05:11:00 PM PDT 24
Peak memory 264076 kb
Host smart-2811e03e-35cf-43fa-8a8e-4f0dbdbf3844
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170625209 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_fetch_code.4170625209
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.2359191405
Short name T57
Test name
Test status
Simulation time 48915255600 ps
CPU time 4281.86 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 06:22:03 PM PDT 24
Peak memory 265436 kb
Host smart-2b401837-e455-42ac-b066-f0efddb51d33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359191405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.2359191405
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1658803115
Short name T824
Test name
Test status
Simulation time 480094561100 ps
CPU time 1749.23 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:39:46 PM PDT 24
Peak memory 264428 kb
Host smart-4c511e9e-9b3c-4304-ac15-8d9d887b93b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658803115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1658803115
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1406758550
Short name T161
Test name
Test status
Simulation time 320252716200 ps
CPU time 1039.87 seconds
Started Jun 27 05:10:39 PM PDT 24
Finished Jun 27 05:28:01 PM PDT 24
Peak memory 265472 kb
Host smart-977b8678-d018-4c53-9656-7e2edcb29524
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406758550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1406758550
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.4101625602
Short name T82
Test name
Test status
Simulation time 9435730400 ps
CPU time 94.33 seconds
Started Jun 27 05:10:40 PM PDT 24
Finished Jun 27 05:12:16 PM PDT 24
Peak memory 261324 kb
Host smart-72c54ee2-91a2-4067-8c40-32acbd92bc14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101625602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.4101625602
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.559161410
Short name T655
Test name
Test status
Simulation time 5440192000 ps
CPU time 181.27 seconds
Started Jun 27 05:10:49 PM PDT 24
Finished Jun 27 05:13:51 PM PDT 24
Peak memory 285132 kb
Host smart-9bdbb717-89da-41ea-895d-4763f477f548
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559161410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.559161410
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.869417064
Short name T990
Test name
Test status
Simulation time 11389611600 ps
CPU time 139.52 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:13:12 PM PDT 24
Peak memory 293380 kb
Host smart-5877fb8b-e748-40fe-840a-5c9f11313be6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869417064 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.869417064
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2583475636
Short name T1110
Test name
Test status
Simulation time 7735430100 ps
CPU time 63.1 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:11:56 PM PDT 24
Peak memory 260812 kb
Host smart-871c95a0-409c-41e3-84b9-1c105dc1750c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583475636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2583475636
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3424469632
Short name T772
Test name
Test status
Simulation time 89679097200 ps
CPU time 194.06 seconds
Started Jun 27 05:10:49 PM PDT 24
Finished Jun 27 05:14:04 PM PDT 24
Peak memory 265404 kb
Host smart-89ab1fdb-0d64-4a64-ae2a-442044cf0263
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342
4469632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3424469632
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.3584702206
Short name T463
Test name
Test status
Simulation time 4060195700 ps
CPU time 92.4 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:12:25 PM PDT 24
Peak memory 263736 kb
Host smart-5a0b068c-ad6a-4ba2-aea7-3294baf6f8ef
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584702206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.3584702206
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.105011674
Short name T839
Test name
Test status
Simulation time 48313800 ps
CPU time 13.61 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:11:25 PM PDT 24
Peak memory 260020 kb
Host smart-bd292609-515e-4499-8581-615f4af923ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105011674 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.105011674
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2876895215
Short name T1073
Test name
Test status
Simulation time 46155400 ps
CPU time 111.92 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:12:32 PM PDT 24
Peak memory 260600 kb
Host smart-a765b2e8-5911-4bf1-a329-c4421ab3cc33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876895215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2876895215
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3240985891
Short name T948
Test name
Test status
Simulation time 4245813700 ps
CPU time 601.9 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:20:41 PM PDT 24
Peak memory 263408 kb
Host smart-091af5eb-943e-40c2-ab91-d834b896d13a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240985891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3240985891
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.2281400636
Short name T711
Test name
Test status
Simulation time 21267800 ps
CPU time 13.85 seconds
Started Jun 27 05:11:07 PM PDT 24
Finished Jun 27 05:11:22 PM PDT 24
Peak memory 265316 kb
Host smart-c494c5bd-408b-4247-bcf7-b4bbb57a10f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281400636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.flash_ctrl_prog_reset.2281400636
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.1696410541
Short name T672
Test name
Test status
Simulation time 34565100 ps
CPU time 56.38 seconds
Started Jun 27 05:10:34 PM PDT 24
Finished Jun 27 05:11:32 PM PDT 24
Peak memory 263424 kb
Host smart-4d5330c6-31b3-4465-8855-ff264a3ab288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696410541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.1696410541
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1460389359
Short name T1008
Test name
Test status
Simulation time 191335200 ps
CPU time 99.3 seconds
Started Jun 27 05:10:41 PM PDT 24
Finished Jun 27 05:12:21 PM PDT 24
Peak memory 263072 kb
Host smart-2f3808a6-3ad0-4c6c-8a20-fe31ea5ba160
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460389359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1460389359
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3933074951
Short name T200
Test name
Test status
Simulation time 123664300 ps
CPU time 29.28 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:11:40 PM PDT 24
Peak memory 280564 kb
Host smart-7fef1824-7b36-42e7-9a6c-0d465f20356f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933074951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3933074951
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.3915869567
Short name T686
Test name
Test status
Simulation time 545028700 ps
CPU time 48.24 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:59 PM PDT 24
Peak memory 281116 kb
Host smart-c0c75b19-f4ee-42ff-9ee3-a7cb9fdbe82c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915869567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.3915869567
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.2497130658
Short name T145
Test name
Test status
Simulation time 65044800 ps
CPU time 34.74 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:11:46 PM PDT 24
Peak memory 275888 kb
Host smart-5b7fb25a-d418-4788-bf83-d85bc7c82960
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497130658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.2497130658
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1802220921
Short name T900
Test name
Test status
Simulation time 85699700 ps
CPU time 18.59 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:11:11 PM PDT 24
Peak memory 259472 kb
Host smart-820d5364-7dfb-4e58-8a65-9143ab0bba29
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1802220921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1802220921
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.4053520321
Short name T516
Test name
Test status
Simulation time 280535400 ps
CPU time 27.09 seconds
Started Jun 27 05:10:50 PM PDT 24
Finished Jun 27 05:11:19 PM PDT 24
Peak memory 274064 kb
Host smart-68d4d835-1ae1-4f1f-87bb-2881db6cf795
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053520321 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.4053520321
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1537005595
Short name T222
Test name
Test status
Simulation time 165569400 ps
CPU time 26.68 seconds
Started Jun 27 05:10:53 PM PDT 24
Finished Jun 27 05:11:21 PM PDT 24
Peak memory 265856 kb
Host smart-a80e9a0f-0683-4a4a-b707-1492db0b2caf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537005595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.1537005595
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.4240225755
Short name T176
Test name
Test status
Simulation time 219299020400 ps
CPU time 1017.48 seconds
Started Jun 27 05:11:10 PM PDT 24
Finished Jun 27 05:28:08 PM PDT 24
Peak memory 261824 kb
Host smart-3447dc27-574d-46a6-9e7e-5a90e0f98ee1
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240225755 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.4240225755
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2911537064
Short name T1010
Test name
Test status
Simulation time 2520019000 ps
CPU time 100.62 seconds
Started Jun 27 05:11:56 PM PDT 24
Finished Jun 27 05:13:37 PM PDT 24
Peak memory 289480 kb
Host smart-007d60b6-64ae-4616-a503-7ac7cafc353e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911537064 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.2911537064
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.3493688238
Short name T51
Test name
Test status
Simulation time 1364976900 ps
CPU time 154.43 seconds
Started Jun 27 05:10:53 PM PDT 24
Finished Jun 27 05:13:28 PM PDT 24
Peak memory 283464 kb
Host smart-60aa6cf5-dfb6-4107-9d40-214858480c13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3493688238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3493688238
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2495766632
Short name T417
Test name
Test status
Simulation time 585021000 ps
CPU time 132.27 seconds
Started Jun 27 05:10:52 PM PDT 24
Finished Jun 27 05:13:06 PM PDT 24
Peak memory 295516 kb
Host smart-3e5a38c5-4034-4ce8-a855-553cbb3c0548
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495766632 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2495766632
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.3909081734
Short name T1109
Test name
Test status
Simulation time 15997291400 ps
CPU time 647.15 seconds
Started Jun 27 05:10:50 PM PDT 24
Finished Jun 27 05:21:39 PM PDT 24
Peak memory 318100 kb
Host smart-8e9428c2-f32c-4ed3-a664-8d219093874f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909081734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.3909081734
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.4098226453
Short name T651
Test name
Test status
Simulation time 26817274700 ps
CPU time 645.83 seconds
Started Jun 27 05:10:55 PM PDT 24
Finished Jun 27 05:21:41 PM PDT 24
Peak memory 335300 kb
Host smart-35b49070-ec9f-479a-b108-4a90a8a54bda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098226453 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.4098226453
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3940962115
Short name T565
Test name
Test status
Simulation time 45200700 ps
CPU time 31.43 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:42 PM PDT 24
Peak memory 270312 kb
Host smart-58612c4b-3724-4d07-bc3e-31eea384c88b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940962115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3940962115
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3611029398
Short name T703
Test name
Test status
Simulation time 27896800 ps
CPU time 30.91 seconds
Started Jun 27 05:11:08 PM PDT 24
Finished Jun 27 05:11:40 PM PDT 24
Peak memory 275132 kb
Host smart-3af3faae-f618-4c1a-8de6-deaee9345498
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611029398 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.3611029398
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.2078928444
Short name T19
Test name
Test status
Simulation time 2861942000 ps
CPU time 4771.87 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 06:30:42 PM PDT 24
Peak memory 287700 kb
Host smart-35d1f3af-9327-4ae6-b332-0a6eaa45a60e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078928444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2078928444
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3775109190
Short name T1028
Test name
Test status
Simulation time 2265578600 ps
CPU time 60.04 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:12:10 PM PDT 24
Peak memory 265300 kb
Host smart-17050329-8e39-45db-ae82-1571e28e3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775109190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3775109190
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.954331799
Short name T143
Test name
Test status
Simulation time 21575690800 ps
CPU time 122.63 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:12:55 PM PDT 24
Peak memory 265792 kb
Host smart-1592720c-c406-460f-ac12-e3a753614c73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954331799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.954331799
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.90017976
Short name T482
Test name
Test status
Simulation time 467190300 ps
CPU time 52.15 seconds
Started Jun 27 05:10:49 PM PDT 24
Finished Jun 27 05:11:42 PM PDT 24
Peak memory 274048 kb
Host smart-cb7ea1e8-eadd-4d58-bd15-4a95ef1fa91e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90017976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_counter.90017976
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.1035516825
Short name T510
Test name
Test status
Simulation time 72289400 ps
CPU time 172.3 seconds
Started Jun 27 05:10:33 PM PDT 24
Finished Jun 27 05:13:27 PM PDT 24
Peak memory 278616 kb
Host smart-590c4ca8-f2f0-4c9a-a67c-11a27d221d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035516825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1035516825
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.3510606293
Short name T629
Test name
Test status
Simulation time 26671900 ps
CPU time 24.13 seconds
Started Jun 27 05:10:35 PM PDT 24
Finished Jun 27 05:11:01 PM PDT 24
Peak memory 260356 kb
Host smart-e27d7f21-cd42-4529-bd0c-b27a9efe390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510606293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3510606293
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2730081337
Short name T877
Test name
Test status
Simulation time 184968100 ps
CPU time 87.06 seconds
Started Jun 27 05:11:11 PM PDT 24
Finished Jun 27 05:12:38 PM PDT 24
Peak memory 261148 kb
Host smart-a616f8ef-9c51-4446-9283-8946013349fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730081337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2730081337
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1102811981
Short name T822
Test name
Test status
Simulation time 90060600 ps
CPU time 25.1 seconds
Started Jun 27 05:10:38 PM PDT 24
Finished Jun 27 05:11:05 PM PDT 24
Peak memory 260076 kb
Host smart-c40fc769-361e-4d77-8177-1e0b2ddf9632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102811981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1102811981
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.1675024276
Short name T771
Test name
Test status
Simulation time 3547624900 ps
CPU time 151.66 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:13:25 PM PDT 24
Peak memory 265648 kb
Host smart-38a24805-cf57-417c-8ba9-61e4cf5aa3e4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675024276 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.1675024276
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1924556890
Short name T10
Test name
Test status
Simulation time 87201300 ps
CPU time 15.49 seconds
Started Jun 27 05:11:09 PM PDT 24
Finished Jun 27 05:11:25 PM PDT 24
Peak memory 260696 kb
Host smart-49e57464-0f4b-4792-ab64-5b33562c679e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924556890 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1924556890
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3332182730
Short name T953
Test name
Test status
Simulation time 41845600 ps
CPU time 15.16 seconds
Started Jun 27 05:10:51 PM PDT 24
Finished Jun 27 05:11:08 PM PDT 24
Peak memory 259144 kb
Host smart-bf79353a-8416-4af1-8981-0a2da72c76d3
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3332182730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3332182730
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.934459725
Short name T9
Test name
Test status
Simulation time 118777200 ps
CPU time 13.75 seconds
Started Jun 27 05:11:31 PM PDT 24
Finished Jun 27 05:11:46 PM PDT 24
Peak memory 261784 kb
Host smart-1733fce5-2270-4bdc-a0df-4687e588c75b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934459725 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.934459725
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3749175505
Short name T541
Test name
Test status
Simulation time 60114300 ps
CPU time 13.58 seconds
Started Jun 27 05:11:47 PM PDT 24
Finished Jun 27 05:12:02 PM PDT 24
Peak memory 265624 kb
Host smart-e6002a75-6400-4509-bf32-9767a462c768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749175505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
749175505
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2895132961
Short name T837
Test name
Test status
Simulation time 69714900 ps
CPU time 14.04 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:11:46 PM PDT 24
Peak memory 261988 kb
Host smart-5728ef63-d81b-4521-b266-552f15e4e813
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895132961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2895132961
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3952762891
Short name T1013
Test name
Test status
Simulation time 22162200 ps
CPU time 16.1 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:11:50 PM PDT 24
Peak memory 275312 kb
Host smart-0eedb88c-1089-43f9-a45a-5916e08d8c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952762891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3952762891
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.2813213102
Short name T179
Test name
Test status
Simulation time 11566200 ps
CPU time 22.17 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:11:57 PM PDT 24
Peak memory 265648 kb
Host smart-85ecaa0d-6538-4bde-8683-39a37f7a6761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813213102 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.2813213102
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.650335073
Short name T472
Test name
Test status
Simulation time 24253832300 ps
CPU time 2439.81 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:52:14 PM PDT 24
Peak memory 265564 kb
Host smart-0a06be27-54ec-468d-8dee-f3d0435be8e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=650335073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.650335073
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.300799410
Short name T87
Test name
Test status
Simulation time 443783100 ps
CPU time 1949.07 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:44:00 PM PDT 24
Peak memory 262616 kb
Host smart-92bd0748-8fba-49e9-a0a5-d411802beb95
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300799410 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.300799410
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3528242169
Short name T1114
Test name
Test status
Simulation time 2751250000 ps
CPU time 929.63 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:27:01 PM PDT 24
Peak memory 270724 kb
Host smart-2379681f-bedf-424a-ba77-d22b2891276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528242169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3528242169
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.3888983066
Short name T545
Test name
Test status
Simulation time 1840349900 ps
CPU time 29.4 seconds
Started Jun 27 05:11:34 PM PDT 24
Finished Jun 27 05:12:04 PM PDT 24
Peak memory 262920 kb
Host smart-feaf3cad-f4f9-41fe-84ae-0afc27f028d8
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888983066 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_fetch_code.3888983066
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2753026488
Short name T260
Test name
Test status
Simulation time 1359708400 ps
CPU time 40.54 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:12:15 PM PDT 24
Peak memory 263192 kb
Host smart-d5fa957f-f2f0-477b-8281-d12985a5d9ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753026488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2753026488
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1907618773
Short name T103
Test name
Test status
Simulation time 329409415400 ps
CPU time 2264.55 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:49:18 PM PDT 24
Peak memory 263960 kb
Host smart-a15bc498-5bc2-48ea-8f37-fb2f50681ce0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907618773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1907618773
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.4219266003
Short name T262
Test name
Test status
Simulation time 213792500 ps
CPU time 72.54 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:12:47 PM PDT 24
Peak memory 265580 kb
Host smart-e757b928-fea2-4d70-8c5d-680cd6910aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219266003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.4219266003
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3296241652
Short name T894
Test name
Test status
Simulation time 77177000 ps
CPU time 13.48 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:12:04 PM PDT 24
Peak memory 265340 kb
Host smart-549ef7a3-1219-471d-9605-16d1de57b197
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296241652 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3296241652
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1922472667
Short name T1115
Test name
Test status
Simulation time 316961320900 ps
CPU time 1823.37 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:41:57 PM PDT 24
Peak memory 261052 kb
Host smart-3cc668a6-783d-4365-a92e-38a9c5047ef0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922472667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1922472667
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2691148750
Short name T928
Test name
Test status
Simulation time 80143918000 ps
CPU time 826.6 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:25:21 PM PDT 24
Peak memory 261252 kb
Host smart-a57a7ca7-331a-48c6-b643-e5ca1530ccb3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691148750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2691148750
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1534498593
Short name T96
Test name
Test status
Simulation time 12560429200 ps
CPU time 288.12 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:16:20 PM PDT 24
Peak memory 263624 kb
Host smart-daeb45f9-0cfb-4ee0-9aa4-7a6f399dc960
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534498593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1534498593
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.3635026756
Short name T478
Test name
Test status
Simulation time 2072466200 ps
CPU time 170.09 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:14:24 PM PDT 24
Peak memory 294808 kb
Host smart-e47189e7-6863-4d09-8899-802d00f91d56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635026756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.3635026756
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1241420260
Short name T194
Test name
Test status
Simulation time 17716027800 ps
CPU time 220.72 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:15:15 PM PDT 24
Peak memory 293448 kb
Host smart-2826f3fb-d5b9-4daf-8b66-530d3a568ef9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241420260 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.1241420260
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1960040593
Short name T467
Test name
Test status
Simulation time 85180219100 ps
CPU time 190.97 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:14:43 PM PDT 24
Peak memory 260888 kb
Host smart-5089d3ce-0dc9-4dcb-a01e-f64011a4215e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196
0040593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1960040593
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2569077790
Short name T448
Test name
Test status
Simulation time 15379800 ps
CPU time 13.66 seconds
Started Jun 27 05:11:54 PM PDT 24
Finished Jun 27 05:12:09 PM PDT 24
Peak memory 265060 kb
Host smart-7db40998-5c0a-440b-aeac-39b166bb3d9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569077790 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2569077790
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.852857941
Short name T916
Test name
Test status
Simulation time 9669791300 ps
CPU time 311.75 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:16:42 PM PDT 24
Peak memory 275032 kb
Host smart-28b46c6f-2eaa-4130-b347-2fe29294d15b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852857941 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.852857941
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.2983756617
Short name T1092
Test name
Test status
Simulation time 133155200 ps
CPU time 111.66 seconds
Started Jun 27 05:11:34 PM PDT 24
Finished Jun 27 05:13:26 PM PDT 24
Peak memory 265272 kb
Host smart-4fd5d800-93a4-4f7a-ae84-e4273b4593de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983756617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.2983756617
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.856039692
Short name T926
Test name
Test status
Simulation time 17329685700 ps
CPU time 201.89 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:14:57 PM PDT 24
Peak memory 290396 kb
Host smart-4530432d-e91c-4481-86bb-279a6f22381d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856039692 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.856039692
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3295741779
Short name T207
Test name
Test status
Simulation time 39137900 ps
CPU time 154.36 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:14:09 PM PDT 24
Peak memory 263372 kb
Host smart-d57c6f01-c1cc-4b09-9276-2639045a7479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3295741779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3295741779
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.2664240027
Short name T801
Test name
Test status
Simulation time 456720800 ps
CPU time 582.82 seconds
Started Jun 27 05:11:28 PM PDT 24
Finished Jun 27 05:21:13 PM PDT 24
Peak memory 283912 kb
Host smart-5eecc34d-764f-425a-9956-7d3d0c3680a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664240027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2664240027
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.888058508
Short name T1100
Test name
Test status
Simulation time 54128300 ps
CPU time 102.28 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:13:15 PM PDT 24
Peak memory 263184 kb
Host smart-a6b13074-955c-4faf-b7d7-2b4c7d432018
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888058508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.888058508
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1262497741
Short name T998
Test name
Test status
Simulation time 145549100 ps
CPU time 29.45 seconds
Started Jun 27 05:11:35 PM PDT 24
Finished Jun 27 05:12:05 PM PDT 24
Peak memory 280652 kb
Host smart-342357f9-01f3-4c19-a303-48919ff451ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262497741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1262497741
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.1148237437
Short name T28
Test name
Test status
Simulation time 142806700 ps
CPU time 35.25 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:12:09 PM PDT 24
Peak memory 275996 kb
Host smart-9b11befb-7cd1-4999-b654-3b85e839f0b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148237437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.1148237437
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3204426812
Short name T648
Test name
Test status
Simulation time 229844700 ps
CPU time 26.7 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:11:58 PM PDT 24
Peak memory 274032 kb
Host smart-fbbbc7ba-0839-4f8c-a67f-ce1956915b62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204426812 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3204426812
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.460980636
Short name T177
Test name
Test status
Simulation time 159332801300 ps
CPU time 1044.96 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:29:17 PM PDT 24
Peak memory 261708 kb
Host smart-bf6a2f5d-49e4-49ea-966b-9e3160d20360
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460980636 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.460980636
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3610583403
Short name T598
Test name
Test status
Simulation time 2639958500 ps
CPU time 104.51 seconds
Started Jun 27 05:11:35 PM PDT 24
Finished Jun 27 05:13:20 PM PDT 24
Peak memory 289336 kb
Host smart-d1809e70-8880-4c44-b523-bfa7dbe0b4b8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610583403 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.3610583403
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.3281668320
Short name T754
Test name
Test status
Simulation time 896225000 ps
CPU time 123.68 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:13:34 PM PDT 24
Peak memory 282336 kb
Host smart-4078aa5b-2f3b-4b45-b51f-7f2d3b719b0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3281668320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.3281668320
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2919875356
Short name T423
Test name
Test status
Simulation time 2384648100 ps
CPU time 135.79 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:13:49 PM PDT 24
Peak memory 295268 kb
Host smart-d05728bc-50bc-459c-a409-b27b4a4c367b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919875356 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2919875356
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.1670789293
Short name T592
Test name
Test status
Simulation time 5739065000 ps
CPU time 384.33 seconds
Started Jun 27 05:11:35 PM PDT 24
Finished Jun 27 05:18:00 PM PDT 24
Peak memory 310088 kb
Host smart-41b9cc2c-1986-45ff-a86a-4eb970c147de
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670789293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.1670789293
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.2985051569
Short name T1031
Test name
Test status
Simulation time 4504741700 ps
CPU time 667.76 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:22:38 PM PDT 24
Peak memory 333084 kb
Host smart-4ec35ad7-3e54-4a73-9574-555473aa9683
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985051569 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.2985051569
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3568817878
Short name T1047
Test name
Test status
Simulation time 69247600 ps
CPU time 28.55 seconds
Started Jun 27 05:11:31 PM PDT 24
Finished Jun 27 05:12:01 PM PDT 24
Peak memory 275964 kb
Host smart-ec5fee02-f62c-4476-959a-542a1ebd8184
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568817878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3568817878
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2577213554
Short name T957
Test name
Test status
Simulation time 46887800 ps
CPU time 31.73 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:12:04 PM PDT 24
Peak memory 275852 kb
Host smart-997b9748-a976-4a5d-8d1e-603a4437b00b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577213554 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2577213554
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.3308744078
Short name T60
Test name
Test status
Simulation time 2648335000 ps
CPU time 4765 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 06:31:00 PM PDT 24
Peak memory 288092 kb
Host smart-0a8729d8-7c23-44fc-9019-a905b086634b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308744078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3308744078
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.42622280
Short name T265
Test name
Test status
Simulation time 2861524000 ps
CPU time 68.6 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:12:40 PM PDT 24
Peak memory 263908 kb
Host smart-bf1b1625-b431-48e9-89e5-f672c2fd4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42622280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.42622280
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.2209983071
Short name T437
Test name
Test status
Simulation time 3039608600 ps
CPU time 84.4 seconds
Started Jun 27 05:11:34 PM PDT 24
Finished Jun 27 05:12:59 PM PDT 24
Peak memory 265792 kb
Host smart-296df9f5-6e9a-4d48-bbc4-c2b34b34d1d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209983071 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.2209983071
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.2980527507
Short name T994
Test name
Test status
Simulation time 1448133200 ps
CPU time 75.09 seconds
Started Jun 27 05:11:31 PM PDT 24
Finished Jun 27 05:12:48 PM PDT 24
Peak memory 274368 kb
Host smart-83000d58-8226-4706-852e-4c1c66b4862f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980527507 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.2980527507
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.786892740
Short name T393
Test name
Test status
Simulation time 61468300 ps
CPU time 143.48 seconds
Started Jun 27 05:11:30 PM PDT 24
Finished Jun 27 05:13:55 PM PDT 24
Peak memory 277424 kb
Host smart-7ea646b7-ef20-4c3d-a465-2ab1e6de52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786892740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.786892740
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2344997008
Short name T1102
Test name
Test status
Simulation time 14966000 ps
CPU time 26.29 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:12:00 PM PDT 24
Peak memory 260064 kb
Host smart-b1fdaba7-0b02-499f-97bd-3077815311e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344997008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2344997008
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1020959755
Short name T638
Test name
Test status
Simulation time 2676017100 ps
CPU time 727.18 seconds
Started Jun 27 05:11:35 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 284088 kb
Host smart-20447f4a-262c-4136-9964-b5a259b9f2b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020959755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1020959755
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.3806979232
Short name T676
Test name
Test status
Simulation time 163280500 ps
CPU time 24.09 seconds
Started Jun 27 05:11:29 PM PDT 24
Finished Jun 27 05:11:54 PM PDT 24
Peak memory 262916 kb
Host smart-f829472b-57d6-49f9-a6ff-3623511fd10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806979232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.3806979232
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.169933962
Short name T118
Test name
Test status
Simulation time 2064131300 ps
CPU time 149.13 seconds
Started Jun 27 05:11:33 PM PDT 24
Finished Jun 27 05:14:04 PM PDT 24
Peak memory 260244 kb
Host smart-e35a0991-8afd-4af1-b183-5977326b67ea
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169933962 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_wo.169933962
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2777913055
Short name T22
Test name
Test status
Simulation time 46457200 ps
CPU time 15.35 seconds
Started Jun 27 05:11:32 PM PDT 24
Finished Jun 27 05:11:49 PM PDT 24
Peak memory 265204 kb
Host smart-38207d8c-e0a7-467e-914c-3f9d7a503e7c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777913055 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2777913055
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3057208392
Short name T809
Test name
Test status
Simulation time 81292600 ps
CPU time 13.89 seconds
Started Jun 27 05:16:27 PM PDT 24
Finished Jun 27 05:16:42 PM PDT 24
Peak memory 265492 kb
Host smart-d6f9250a-ab7f-433c-9b39-06225a8b5833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057208392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3057208392
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.3510214716
Short name T593
Test name
Test status
Simulation time 20140500 ps
CPU time 13.47 seconds
Started Jun 27 05:16:28 PM PDT 24
Finished Jun 27 05:16:43 PM PDT 24
Peak memory 275244 kb
Host smart-24f51b31-cd1e-4e48-8a65-3adde6c6523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510214716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3510214716
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2775405876
Short name T851
Test name
Test status
Simulation time 10020286500 ps
CPU time 73.24 seconds
Started Jun 27 05:16:27 PM PDT 24
Finished Jun 27 05:17:41 PM PDT 24
Peak memory 286668 kb
Host smart-aabad3fd-ca67-41b8-b9ec-9b9930d0ea7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775405876 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2775405876
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3328936067
Short name T983
Test name
Test status
Simulation time 46464100 ps
CPU time 13.95 seconds
Started Jun 27 05:16:26 PM PDT 24
Finished Jun 27 05:16:40 PM PDT 24
Peak memory 258736 kb
Host smart-cf7f9f59-575c-46f6-862c-bed88bdbdf65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328936067 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3328936067
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3138874454
Short name T1027
Test name
Test status
Simulation time 160184155700 ps
CPU time 934.24 seconds
Started Jun 27 05:16:08 PM PDT 24
Finished Jun 27 05:31:43 PM PDT 24
Peak memory 265384 kb
Host smart-debdf881-97f4-4634-ab3e-777985b1a157
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138874454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3138874454
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1703979739
Short name T736
Test name
Test status
Simulation time 28759473600 ps
CPU time 103.66 seconds
Started Jun 27 05:16:10 PM PDT 24
Finished Jun 27 05:17:54 PM PDT 24
Peak memory 263168 kb
Host smart-e0920776-eb82-48a5-9462-a6ba3a5bb4fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703979739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1703979739
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1705433328
Short name T966
Test name
Test status
Simulation time 6705733600 ps
CPU time 204.22 seconds
Started Jun 27 05:16:25 PM PDT 24
Finished Jun 27 05:19:50 PM PDT 24
Peak memory 285208 kb
Host smart-a2695001-75ab-4030-8da1-61ff820f2df2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705433328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1705433328
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3401182350
Short name T996
Test name
Test status
Simulation time 6009540300 ps
CPU time 139.61 seconds
Started Jun 27 05:16:29 PM PDT 24
Finished Jun 27 05:18:50 PM PDT 24
Peak memory 294580 kb
Host smart-6c7e9c48-6748-4efd-a31c-c3a447aa054a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401182350 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3401182350
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.590606296
Short name T764
Test name
Test status
Simulation time 14976823400 ps
CPU time 75.5 seconds
Started Jun 27 05:16:25 PM PDT 24
Finished Jun 27 05:17:42 PM PDT 24
Peak memory 263048 kb
Host smart-bbef3efc-32ed-4b28-897f-7ec79a32b188
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590606296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.590606296
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.4068940883
Short name T14
Test name
Test status
Simulation time 154464400 ps
CPU time 13.46 seconds
Started Jun 27 05:16:30 PM PDT 24
Finished Jun 27 05:16:44 PM PDT 24
Peak memory 260252 kb
Host smart-13c8fc9f-28e8-4320-bdda-8a0f5f6bdc2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068940883 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.4068940883
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3854621191
Short name T136
Test name
Test status
Simulation time 10132870000 ps
CPU time 682.04 seconds
Started Jun 27 05:16:29 PM PDT 24
Finished Jun 27 05:27:52 PM PDT 24
Peak memory 274852 kb
Host smart-2e08c139-7c14-4b20-90a0-b54c80e7d3fd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854621191 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.3854621191
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.1646738010
Short name T514
Test name
Test status
Simulation time 47584200 ps
CPU time 133.14 seconds
Started Jun 27 05:16:07 PM PDT 24
Finished Jun 27 05:18:21 PM PDT 24
Peak memory 265528 kb
Host smart-5188fb9e-79f9-45e1-8b8a-2b19ab88648d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646738010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.1646738010
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3462398157
Short name T749
Test name
Test status
Simulation time 140399600 ps
CPU time 286.59 seconds
Started Jun 27 05:16:09 PM PDT 24
Finished Jun 27 05:20:57 PM PDT 24
Peak memory 263312 kb
Host smart-6961e89f-627d-43c5-a96f-f713de3d4f59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462398157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3462398157
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.859470196
Short name T1012
Test name
Test status
Simulation time 74898200 ps
CPU time 14.22 seconds
Started Jun 27 05:16:25 PM PDT 24
Finished Jun 27 05:16:40 PM PDT 24
Peak memory 259764 kb
Host smart-c9968ac7-e8a5-4f69-b3f2-c195f3372918
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859470196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.flash_ctrl_prog_reset.859470196
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1058112196
Short name T835
Test name
Test status
Simulation time 460176100 ps
CPU time 861.86 seconds
Started Jun 27 05:16:09 PM PDT 24
Finished Jun 27 05:30:32 PM PDT 24
Peak memory 283320 kb
Host smart-50bd3249-d5ca-49de-a87f-2d565583be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058112196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1058112196
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3930680303
Short name T353
Test name
Test status
Simulation time 185614000 ps
CPU time 34.83 seconds
Started Jun 27 05:16:26 PM PDT 24
Finished Jun 27 05:17:01 PM PDT 24
Peak memory 275940 kb
Host smart-f7e89071-0a71-48f9-b4ca-25d0c501f545
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930680303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3930680303
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.3829577577
Short name T633
Test name
Test status
Simulation time 2678195100 ps
CPU time 117.8 seconds
Started Jun 27 05:16:28 PM PDT 24
Finished Jun 27 05:18:27 PM PDT 24
Peak memory 290524 kb
Host smart-3704fd1b-1911-4ac4-9a7f-5a13c15d9a6a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829577577 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.3829577577
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2563963646
Short name T365
Test name
Test status
Simulation time 36737300 ps
CPU time 29.54 seconds
Started Jun 27 05:16:25 PM PDT 24
Finished Jun 27 05:16:56 PM PDT 24
Peak memory 275876 kb
Host smart-37efc422-8440-4817-8924-443da1ee2eae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563963646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2563963646
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3989779198
Short name T893
Test name
Test status
Simulation time 7737471300 ps
CPU time 70.92 seconds
Started Jun 27 05:16:29 PM PDT 24
Finished Jun 27 05:17:41 PM PDT 24
Peak memory 264192 kb
Host smart-59c4674b-9c3b-4b1d-94a1-876bf71f8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989779198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3989779198
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.3588650114
Short name T128
Test name
Test status
Simulation time 33732800 ps
CPU time 196.85 seconds
Started Jun 27 05:16:06 PM PDT 24
Finished Jun 27 05:19:23 PM PDT 24
Peak memory 281912 kb
Host smart-9203881a-6f87-4654-9c62-60e77db5bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588650114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3588650114
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.2365789333
Short name T854
Test name
Test status
Simulation time 1983092700 ps
CPU time 179.23 seconds
Started Jun 27 05:16:28 PM PDT 24
Finished Jun 27 05:19:28 PM PDT 24
Peak memory 260148 kb
Host smart-9024b0f3-cf22-4bc7-9245-6ade3905ca77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365789333 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.2365789333
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3894634099
Short name T636
Test name
Test status
Simulation time 348303900 ps
CPU time 13.81 seconds
Started Jun 27 05:16:50 PM PDT 24
Finished Jun 27 05:17:04 PM PDT 24
Peak memory 265512 kb
Host smart-499d41d2-cac8-4851-a9e1-97721cb635ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894634099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3894634099
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.1229435226
Short name T761
Test name
Test status
Simulation time 26358100 ps
CPU time 15.65 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:17:03 PM PDT 24
Peak memory 275128 kb
Host smart-f8fc1ece-93de-47b4-960c-2a4c34a37a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229435226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1229435226
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3421221550
Short name T150
Test name
Test status
Simulation time 20791800 ps
CPU time 21.8 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:17:09 PM PDT 24
Peak memory 273900 kb
Host smart-7a76205d-e267-4237-88d8-cb5d9ad0776f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421221550 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3421221550
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4029920043
Short name T774
Test name
Test status
Simulation time 10019877000 ps
CPU time 64.26 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:17:51 PM PDT 24
Peak memory 268996 kb
Host smart-96d81c51-ef17-4cf3-ad6d-08c92537bcde
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029920043 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.4029920043
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.886735903
Short name T820
Test name
Test status
Simulation time 25775700 ps
CPU time 13.43 seconds
Started Jun 27 05:16:45 PM PDT 24
Finished Jun 27 05:16:59 PM PDT 24
Peak memory 265112 kb
Host smart-3d025043-6109-48f3-b5f1-2628849a6612
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886735903 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.886735903
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3099390764
Short name T163
Test name
Test status
Simulation time 40125844600 ps
CPU time 822.14 seconds
Started Jun 27 05:16:43 PM PDT 24
Finished Jun 27 05:30:26 PM PDT 24
Peak memory 264888 kb
Host smart-53b9e3e0-8ec3-49e1-857a-7ba6327218a5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099390764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3099390764
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.128039664
Short name T614
Test name
Test status
Simulation time 679032100 ps
CPU time 34.56 seconds
Started Jun 27 05:16:26 PM PDT 24
Finished Jun 27 05:17:01 PM PDT 24
Peak memory 263364 kb
Host smart-1dfed17d-afaa-4d88-bc49-93aa06b46929
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128039664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_h
w_sec_otp.128039664
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1874345563
Short name T350
Test name
Test status
Simulation time 10833668700 ps
CPU time 199.39 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:20:07 PM PDT 24
Peak memory 285264 kb
Host smart-0343f664-7832-4a0b-b156-cb116b01b5da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874345563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1874345563
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2119650498
Short name T340
Test name
Test status
Simulation time 32843363400 ps
CPU time 317.11 seconds
Started Jun 27 05:16:49 PM PDT 24
Finished Jun 27 05:22:07 PM PDT 24
Peak memory 292236 kb
Host smart-dd5db6d9-53fa-45b3-b46d-6e8c21777ddf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119650498 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2119650498
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.182798962
Short name T696
Test name
Test status
Simulation time 1631434500 ps
CPU time 67.47 seconds
Started Jun 27 05:16:44 PM PDT 24
Finished Jun 27 05:17:52 PM PDT 24
Peak memory 260936 kb
Host smart-26f1c53c-2a7c-466f-9586-bba79e3e9ff8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182798962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.182798962
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1715264269
Short name T779
Test name
Test status
Simulation time 69864500 ps
CPU time 13.41 seconds
Started Jun 27 05:16:45 PM PDT 24
Finished Jun 27 05:16:59 PM PDT 24
Peak memory 265212 kb
Host smart-f5f49de7-730e-48ac-b5cf-f148c12c7807
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715264269 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1715264269
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2237942402
Short name T553
Test name
Test status
Simulation time 5665808300 ps
CPU time 131.54 seconds
Started Jun 27 05:16:42 PM PDT 24
Finished Jun 27 05:18:54 PM PDT 24
Peak memory 264196 kb
Host smart-a25fd25b-5136-4ee4-b3c5-a4bdf91d2caf
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237942402 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.2237942402
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3973153194
Short name T79
Test name
Test status
Simulation time 73214900 ps
CPU time 132.64 seconds
Started Jun 27 05:16:43 PM PDT 24
Finished Jun 27 05:18:57 PM PDT 24
Peak memory 261432 kb
Host smart-64f9e0e2-d770-4a7d-ac56-139210cdce55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973153194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3973153194
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1829655128
Short name T209
Test name
Test status
Simulation time 715755600 ps
CPU time 424.97 seconds
Started Jun 27 05:16:26 PM PDT 24
Finished Jun 27 05:23:31 PM PDT 24
Peak memory 263472 kb
Host smart-25fdafa5-e2cb-4188-83f9-b398f951939f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1829655128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1829655128
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3858507195
Short name T646
Test name
Test status
Simulation time 134801900 ps
CPU time 13.85 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:17:01 PM PDT 24
Peak memory 259452 kb
Host smart-27674215-c574-42a9-bf52-23b53564c612
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858507195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.flash_ctrl_prog_reset.3858507195
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.3400663600
Short name T529
Test name
Test status
Simulation time 1677704000 ps
CPU time 697.37 seconds
Started Jun 27 05:16:24 PM PDT 24
Finished Jun 27 05:28:02 PM PDT 24
Peak memory 284192 kb
Host smart-fe12dd0b-4d80-4813-ac35-8f907423e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400663600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3400663600
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.2695639480
Short name T354
Test name
Test status
Simulation time 121924200 ps
CPU time 31.25 seconds
Started Jun 27 05:16:47 PM PDT 24
Finished Jun 27 05:17:19 PM PDT 24
Peak memory 275780 kb
Host smart-92cb3c2c-4ebe-4175-90da-6ee9cd4eb81a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695639480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.2695639480
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.497535038
Short name T723
Test name
Test status
Simulation time 558791100 ps
CPU time 93.83 seconds
Started Jun 27 05:16:50 PM PDT 24
Finished Jun 27 05:18:25 PM PDT 24
Peak memory 282220 kb
Host smart-4baf2276-36c0-45c6-bdd0-b29e1f77152e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497535038 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.497535038
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.33775147
Short name T211
Test name
Test status
Simulation time 24855506300 ps
CPU time 638.45 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:27:25 PM PDT 24
Peak memory 310300 kb
Host smart-9d131dd8-bdc3-471e-baed-f4c9ecb2ee0b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33775147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_rw.33775147
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.4055586549
Short name T828
Test name
Test status
Simulation time 113132800 ps
CPU time 30.24 seconds
Started Jun 27 05:16:50 PM PDT 24
Finished Jun 27 05:17:21 PM PDT 24
Peak memory 275840 kb
Host smart-747011d9-ac1e-4d3e-b219-0a465f25bff4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055586549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.4055586549
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.720013069
Short name T271
Test name
Test status
Simulation time 37350900 ps
CPU time 27.16 seconds
Started Jun 27 05:16:50 PM PDT 24
Finished Jun 27 05:17:18 PM PDT 24
Peak memory 275820 kb
Host smart-a101d1af-541e-4658-95f8-0c65aaa444f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720013069 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.720013069
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2058813489
Short name T552
Test name
Test status
Simulation time 86509800 ps
CPU time 221.75 seconds
Started Jun 27 05:16:27 PM PDT 24
Finished Jun 27 05:20:10 PM PDT 24
Peak memory 278420 kb
Host smart-f28eff68-4f24-4584-84f1-6eda994c619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058813489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2058813489
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.2393805422
Short name T468
Test name
Test status
Simulation time 13249297900 ps
CPU time 276.37 seconds
Started Jun 27 05:16:42 PM PDT 24
Finished Jun 27 05:21:19 PM PDT 24
Peak memory 260424 kb
Host smart-0174bf28-6f5f-4311-a37c-91f484039915
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393805422 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.2393805422
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.522883155
Short name T498
Test name
Test status
Simulation time 36344100 ps
CPU time 13.86 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:17:19 PM PDT 24
Peak memory 258580 kb
Host smart-477ee8dc-8ddc-4fa2-a36c-2f4998787067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522883155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.522883155
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.3081387812
Short name T628
Test name
Test status
Simulation time 71786300 ps
CPU time 15.76 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:17:21 PM PDT 24
Peak memory 275280 kb
Host smart-05d0ff7d-922d-4bf5-af59-0cc045e8b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081387812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.3081387812
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.3162506299
Short name T604
Test name
Test status
Simulation time 28945200 ps
CPU time 22.27 seconds
Started Jun 27 05:17:11 PM PDT 24
Finished Jun 27 05:17:34 PM PDT 24
Peak memory 274036 kb
Host smart-ce14a7ef-247c-467c-aad7-6be3a5015b1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162506299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.3162506299
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2473934607
Short name T183
Test name
Test status
Simulation time 10035138000 ps
CPU time 61.27 seconds
Started Jun 27 05:17:10 PM PDT 24
Finished Jun 27 05:18:12 PM PDT 24
Peak memory 293520 kb
Host smart-b58db161-1925-427d-9399-88a91b106f39
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473934607 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2473934607
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.643835986
Short name T647
Test name
Test status
Simulation time 47000400 ps
CPU time 13.62 seconds
Started Jun 27 05:17:05 PM PDT 24
Finished Jun 27 05:17:20 PM PDT 24
Peak memory 265236 kb
Host smart-87d07312-7bbb-4796-b6ba-21f0e38f0cd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643835986 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.643835986
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1354034117
Short name T105
Test name
Test status
Simulation time 40120804500 ps
CPU time 823.46 seconds
Started Jun 27 05:16:44 PM PDT 24
Finished Jun 27 05:30:28 PM PDT 24
Peak memory 264168 kb
Host smart-ff0b1f6e-989f-40fb-9512-c5a3877c3a25
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354034117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1354034117
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.1637774827
Short name T1001
Test name
Test status
Simulation time 4195765700 ps
CPU time 141.58 seconds
Started Jun 27 05:16:49 PM PDT 24
Finished Jun 27 05:19:11 PM PDT 24
Peak memory 262748 kb
Host smart-023ef5b1-98db-4d6e-b8af-8c8b29fa8b59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637774827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.1637774827
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3210050695
Short name T644
Test name
Test status
Simulation time 796107100 ps
CPU time 137.81 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:19:23 PM PDT 24
Peak memory 293836 kb
Host smart-9b51ad70-a9c2-498c-8c25-4e8a4f2a3264
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210050695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3210050695
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.3320798170
Short name T257
Test name
Test status
Simulation time 9068040600 ps
CPU time 67.51 seconds
Started Jun 27 05:17:11 PM PDT 24
Finished Jun 27 05:18:19 PM PDT 24
Peak memory 260928 kb
Host smart-e850e21d-42a7-44c3-8c77-91b1589e0d79
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320798170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3
320798170
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1280075592
Short name T543
Test name
Test status
Simulation time 128618200 ps
CPU time 13.75 seconds
Started Jun 27 05:17:02 PM PDT 24
Finished Jun 27 05:17:17 PM PDT 24
Peak memory 260208 kb
Host smart-0e6465c8-e0da-45f9-b8ec-e9bd340e7cdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280075592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1280075592
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3003204785
Short name T121
Test name
Test status
Simulation time 37363736300 ps
CPU time 687.66 seconds
Started Jun 27 05:17:02 PM PDT 24
Finished Jun 27 05:28:31 PM PDT 24
Peak memory 274684 kb
Host smart-1f912029-5df1-4f2b-a5d7-d14e4ee29f82
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003204785 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3003204785
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2917534705
Short name T830
Test name
Test status
Simulation time 145152800 ps
CPU time 134.47 seconds
Started Jun 27 05:16:46 PM PDT 24
Finished Jun 27 05:19:02 PM PDT 24
Peak memory 264804 kb
Host smart-148bc960-68e9-456d-9152-e045a97c1eb8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917534705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2917534705
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.3419311061
Short name T909
Test name
Test status
Simulation time 2690677000 ps
CPU time 567.58 seconds
Started Jun 27 05:16:43 PM PDT 24
Finished Jun 27 05:26:11 PM PDT 24
Peak memory 263496 kb
Host smart-e8e85f64-21c1-4cc4-b59f-280c2c314574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419311061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3419311061
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.234685286
Short name T946
Test name
Test status
Simulation time 166177800 ps
CPU time 13.56 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:17:19 PM PDT 24
Peak memory 265300 kb
Host smart-fe835b5e-10b5-4ebb-92b7-4e130956555f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234685286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 12.flash_ctrl_prog_reset.234685286
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.2845244363
Short name T702
Test name
Test status
Simulation time 53716900 ps
CPU time 54.48 seconds
Started Jun 27 05:16:43 PM PDT 24
Finished Jun 27 05:17:38 PM PDT 24
Peak memory 271652 kb
Host smart-3f9bbcb4-fd23-4f5e-8b3b-a9c84fef8758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845244363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2845244363
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1866940911
Short name T1020
Test name
Test status
Simulation time 343254800 ps
CPU time 35.79 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:17:41 PM PDT 24
Peak memory 273420 kb
Host smart-35f92b82-d91a-4062-95c4-12d0bb1f3d7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866940911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1866940911
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1896570375
Short name T574
Test name
Test status
Simulation time 553988000 ps
CPU time 128.08 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:19:13 PM PDT 24
Peak memory 282080 kb
Host smart-7cde2a14-dbef-4a88-9ce4-89f63f1ea127
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896570375 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.1896570375
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3026166993
Short name T878
Test name
Test status
Simulation time 7626579500 ps
CPU time 539.16 seconds
Started Jun 27 05:17:10 PM PDT 24
Finished Jun 27 05:26:10 PM PDT 24
Peak memory 310036 kb
Host smart-14478316-3614-4720-9ab4-3bbdf99912ff
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026166993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.3026166993
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.535005094
Short name T272
Test name
Test status
Simulation time 76582600 ps
CPU time 29.49 seconds
Started Jun 27 05:17:04 PM PDT 24
Finished Jun 27 05:17:35 PM PDT 24
Peak memory 270316 kb
Host smart-2221168f-e753-4661-999d-76bfee6c8a5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535005094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.535005094
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.4033535747
Short name T959
Test name
Test status
Simulation time 31785900 ps
CPU time 29.92 seconds
Started Jun 27 05:17:03 PM PDT 24
Finished Jun 27 05:17:34 PM PDT 24
Peak memory 277332 kb
Host smart-70445845-95bc-4e9f-a8e6-f948aae78c5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033535747 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.4033535747
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.3088590233
Short name T410
Test name
Test status
Simulation time 16345121300 ps
CPU time 72.76 seconds
Started Jun 27 05:17:02 PM PDT 24
Finished Jun 27 05:18:16 PM PDT 24
Peak memory 264168 kb
Host smart-a6928047-8038-42f5-a3f8-bd3d945ba5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088590233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3088590233
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2321869140
Short name T312
Test name
Test status
Simulation time 21959500 ps
CPU time 100.17 seconds
Started Jun 27 05:16:49 PM PDT 24
Finished Jun 27 05:18:30 PM PDT 24
Peak memory 277508 kb
Host smart-a2e28fe3-3085-4b75-8ce4-72d415b100ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321869140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2321869140
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.1565369589
Short name T876
Test name
Test status
Simulation time 20034418100 ps
CPU time 167.99 seconds
Started Jun 27 05:17:11 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 260344 kb
Host smart-8373bb0c-aceb-44f9-a90b-0d78b6d27287
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565369589 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.1565369589
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2735032343
Short name T1087
Test name
Test status
Simulation time 29798000 ps
CPU time 13.56 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:18:10 PM PDT 24
Peak memory 265668 kb
Host smart-422d54b1-6621-45dc-871e-ed7376dfe377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735032343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2735032343
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.4085936711
Short name T914
Test name
Test status
Simulation time 29256200 ps
CPU time 16.55 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:18:03 PM PDT 24
Peak memory 284700 kb
Host smart-507a492e-6ffe-486e-8847-68ee45d4f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085936711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.4085936711
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3915438428
Short name T873
Test name
Test status
Simulation time 10019057500 ps
CPU time 83.95 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:19:24 PM PDT 24
Peak memory 292488 kb
Host smart-e95dbfa8-efe5-42f8-95fd-d9861c35cfc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915438428 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3915438428
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3038139018
Short name T969
Test name
Test status
Simulation time 47474300 ps
CPU time 13.62 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:17:59 PM PDT 24
Peak memory 258836 kb
Host smart-d848fe98-7d7d-4e51-a049-e5d2b0bb084b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038139018 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3038139018
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1451330646
Short name T649
Test name
Test status
Simulation time 13843824200 ps
CPU time 103.21 seconds
Started Jun 27 05:17:43 PM PDT 24
Finished Jun 27 05:19:27 PM PDT 24
Peak memory 263176 kb
Host smart-8ed3067b-414f-46b0-b579-a380cf907eeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451330646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.1451330646
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3382402403
Short name T1014
Test name
Test status
Simulation time 6451289500 ps
CPU time 192.29 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:20:57 PM PDT 24
Peak memory 291672 kb
Host smart-f1f09e69-a3d7-4340-a4be-73806860d9a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382402403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3382402403
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1693057066
Short name T848
Test name
Test status
Simulation time 35892031300 ps
CPU time 253.15 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:21:58 PM PDT 24
Peak memory 293372 kb
Host smart-c4be413e-8848-41ec-a5a3-ce1668c9f648
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693057066 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.1693057066
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.966131561
Short name T560
Test name
Test status
Simulation time 4197699800 ps
CPU time 71.67 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:18:56 PM PDT 24
Peak memory 263056 kb
Host smart-ee622669-f022-475f-a080-9b0b6bcc7cd0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966131561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.966131561
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.1975166368
Short name T694
Test name
Test status
Simulation time 40456255100 ps
CPU time 659.86 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:28:46 PM PDT 24
Peak memory 275056 kb
Host smart-86f56e90-1ebc-4cad-9ea2-7e48b95fccfc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975166368 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.1975166368
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.3432621283
Short name T461
Test name
Test status
Simulation time 40709900 ps
CPU time 133.68 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:19:59 PM PDT 24
Peak memory 265412 kb
Host smart-5fb1015a-1f67-4aa2-9255-cd905dba8c6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432621283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.3432621283
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.683355376
Short name T189
Test name
Test status
Simulation time 41199000 ps
CPU time 154.09 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:20:19 PM PDT 24
Peak memory 263508 kb
Host smart-46875c4a-bd25-4c71-bb50-2b046af3eb43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683355376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.683355376
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3891771947
Short name T424
Test name
Test status
Simulation time 84071700 ps
CPU time 13.61 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:17:59 PM PDT 24
Peak memory 265372 kb
Host smart-604d7e9b-77fc-46f4-bf30-53bd4ce5c62c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891771947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 13.flash_ctrl_prog_reset.3891771947
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.555715006
Short name T131
Test name
Test status
Simulation time 131514400 ps
CPU time 155.28 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:20:21 PM PDT 24
Peak memory 272136 kb
Host smart-178d95b3-d5eb-481a-a013-a3a13a1486c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555715006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.555715006
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3749522909
Short name T559
Test name
Test status
Simulation time 121384000 ps
CPU time 31.85 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:18:16 PM PDT 24
Peak memory 278276 kb
Host smart-5396eecb-8828-4a79-b285-1fc1e963f50e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749522909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3749522909
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.2702223046
Short name T865
Test name
Test status
Simulation time 710747900 ps
CPU time 123.8 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:19:50 PM PDT 24
Peak memory 282260 kb
Host smart-ff68dc46-113e-43dd-9aff-f0e80a3b2644
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702223046 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.2702223046
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.307688016
Short name T691
Test name
Test status
Simulation time 31837000 ps
CPU time 31.31 seconds
Started Jun 27 05:17:44 PM PDT 24
Finished Jun 27 05:18:17 PM PDT 24
Peak memory 276080 kb
Host smart-f256ccbd-6d9f-48bb-87e7-da36904d0e1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307688016 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.307688016
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2983053996
Short name T32
Test name
Test status
Simulation time 1555253500 ps
CPU time 74.3 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:19:00 PM PDT 24
Peak memory 264776 kb
Host smart-aecdfd12-71bf-4ca8-98a3-284b58902b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983053996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2983053996
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.4143670096
Short name T427
Test name
Test status
Simulation time 33251600 ps
CPU time 169.24 seconds
Started Jun 27 05:17:45 PM PDT 24
Finished Jun 27 05:20:35 PM PDT 24
Peak memory 277612 kb
Host smart-a97e8120-683b-4f69-934a-fe431e6e973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143670096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.4143670096
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.2888969651
Short name T1030
Test name
Test status
Simulation time 344895100 ps
CPU time 14.44 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:18:14 PM PDT 24
Peak memory 258604 kb
Host smart-d1da9458-c769-40be-af9d-70c1b02dc907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888969651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
2888969651
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.666942454
Short name T107
Test name
Test status
Simulation time 46729600 ps
CPU time 15.78 seconds
Started Jun 27 05:17:54 PM PDT 24
Finished Jun 27 05:18:12 PM PDT 24
Peak memory 275304 kb
Host smart-e9a97742-de30-49f7-991d-094feb36794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666942454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.666942454
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.367440986
Short name T178
Test name
Test status
Simulation time 13720300 ps
CPU time 22.38 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:18:23 PM PDT 24
Peak memory 273948 kb
Host smart-c6ccc445-8c77-44dc-bd7e-7ee856228bd8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367440986 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.367440986
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.905520253
Short name T1036
Test name
Test status
Simulation time 10012185900 ps
CPU time 115.26 seconds
Started Jun 27 05:17:54 PM PDT 24
Finished Jun 27 05:19:51 PM PDT 24
Peak memory 305928 kb
Host smart-5ec38110-8bb0-445c-a9a4-f70435310169
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905520253 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.905520253
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1479890594
Short name T793
Test name
Test status
Simulation time 15763100 ps
CPU time 13.59 seconds
Started Jun 27 05:17:53 PM PDT 24
Finished Jun 27 05:18:09 PM PDT 24
Peak memory 258856 kb
Host smart-f6451ce1-2881-4abd-9a75-f33021820aaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479890594 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1479890594
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3361925492
Short name T821
Test name
Test status
Simulation time 40128091200 ps
CPU time 865.92 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:32:25 PM PDT 24
Peak memory 265376 kb
Host smart-829209c0-027f-4175-bd56-ad3675d66ec0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361925492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.3361925492
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2625612117
Short name T896
Test name
Test status
Simulation time 18622651500 ps
CPU time 135.34 seconds
Started Jun 27 05:17:53 PM PDT 24
Finished Jun 27 05:20:10 PM PDT 24
Peak memory 261316 kb
Host smart-21a65d6e-19c0-4923-b3c3-a267666d878d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625612117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2625612117
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.2355344117
Short name T1067
Test name
Test status
Simulation time 712190600 ps
CPU time 158.42 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:20:36 PM PDT 24
Peak memory 291876 kb
Host smart-6b64abd0-8661-4516-b774-295c377f29b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355344117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.2355344117
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1631981301
Short name T701
Test name
Test status
Simulation time 11629966600 ps
CPU time 287.73 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:22:49 PM PDT 24
Peak memory 285208 kb
Host smart-8919c063-e8a4-4343-8f88-99ad23e91844
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631981301 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1631981301
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3903256461
Short name T495
Test name
Test status
Simulation time 4241129100 ps
CPU time 75.74 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:19:13 PM PDT 24
Peak memory 263852 kb
Host smart-db1337e4-f66e-4682-880e-3006e5c269c0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903256461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
903256461
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.541700337
Short name T1049
Test name
Test status
Simulation time 109571800 ps
CPU time 13.73 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:18:13 PM PDT 24
Peak memory 265224 kb
Host smart-175d98ac-f73b-45bd-92d2-0803957ff0e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541700337 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.541700337
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1010109032
Short name T139
Test name
Test status
Simulation time 42819938800 ps
CPU time 840.41 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:32:00 PM PDT 24
Peak memory 275028 kb
Host smart-e500126c-1b36-4a3f-b28f-677d7a300ed4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010109032 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.1010109032
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.1670351222
Short name T706
Test name
Test status
Simulation time 137996800 ps
CPU time 112.26 seconds
Started Jun 27 05:17:54 PM PDT 24
Finished Jun 27 05:19:48 PM PDT 24
Peak memory 265708 kb
Host smart-b8dbbe07-163b-4052-89f6-3ee3423cd013
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670351222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.1670351222
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.144114268
Short name T567
Test name
Test status
Simulation time 94921800 ps
CPU time 69.42 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:19:09 PM PDT 24
Peak memory 263460 kb
Host smart-55abcd0d-d09d-453a-b117-f936d46265ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144114268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.144114268
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.242420965
Short name T690
Test name
Test status
Simulation time 31579700 ps
CPU time 14.28 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:18:15 PM PDT 24
Peak memory 265400 kb
Host smart-a506baaa-9d77-4ef8-82b9-da74105692e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242420965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.flash_ctrl_prog_reset.242420965
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3631066452
Short name T836
Test name
Test status
Simulation time 156927400 ps
CPU time 485.55 seconds
Started Jun 27 05:18:28 PM PDT 24
Finished Jun 27 05:26:34 PM PDT 24
Peak memory 284008 kb
Host smart-eb2c5a66-277d-4e86-9c78-61af35d663b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631066452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3631066452
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3066172405
Short name T550
Test name
Test status
Simulation time 362483400 ps
CPU time 34.65 seconds
Started Jun 27 05:17:53 PM PDT 24
Finished Jun 27 05:18:29 PM PDT 24
Peak memory 271112 kb
Host smart-515a9e41-776a-453a-a852-52cc3154e124
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066172405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3066172405
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.1674781882
Short name T7
Test name
Test status
Simulation time 866078900 ps
CPU time 120.61 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:20:01 PM PDT 24
Peak memory 282284 kb
Host smart-96d8f5ce-2983-4e1b-a770-1dffd0e602a2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674781882 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.1674781882
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1153778614
Short name T689
Test name
Test status
Simulation time 26808908800 ps
CPU time 572.33 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:27:29 PM PDT 24
Peak memory 314668 kb
Host smart-c3a6cfc5-9288-49d4-87ae-2892661e3a12
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153778614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1153778614
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.3336918650
Short name T605
Test name
Test status
Simulation time 56315500 ps
CPU time 31.16 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:18:28 PM PDT 24
Peak memory 275832 kb
Host smart-76939e5f-7dee-4248-b79e-8a9c80cf0ccc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336918650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.3336918650
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.2271773978
Short name T1025
Test name
Test status
Simulation time 28233100 ps
CPU time 28.46 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:18:27 PM PDT 24
Peak memory 275852 kb
Host smart-618d2bb9-d70b-477f-a004-4884540aa7e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271773978 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.2271773978
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.517892802
Short name T44
Test name
Test status
Simulation time 2488637800 ps
CPU time 93.06 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:19:31 PM PDT 24
Peak memory 264236 kb
Host smart-964c307b-3d85-4191-a9b5-deb92bba277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517892802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.517892802
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3569457812
Short name T847
Test name
Test status
Simulation time 117599600 ps
CPU time 214.67 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:21:32 PM PDT 24
Peak memory 278336 kb
Host smart-5b1bdc58-d45a-4c0b-9347-da84e4491980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569457812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3569457812
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3676831168
Short name T863
Test name
Test status
Simulation time 13135578300 ps
CPU time 213.86 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:21:31 PM PDT 24
Peak memory 265508 kb
Host smart-88b279a7-c019-40e9-aec7-2f7ff98a2681
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676831168 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3676831168
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.4198750111
Short name T600
Test name
Test status
Simulation time 204598600 ps
CPU time 14.05 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:18:28 PM PDT 24
Peak memory 265632 kb
Host smart-72609622-cf38-4ba1-9baf-a6f7c140383f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198750111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
4198750111
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1521891095
Short name T1017
Test name
Test status
Simulation time 14039300 ps
CPU time 16.86 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:18:30 PM PDT 24
Peak memory 275312 kb
Host smart-0b7fd661-c7e3-4af2-a693-c5d504570f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521891095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1521891095
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2686829924
Short name T80
Test name
Test status
Simulation time 13881700 ps
CPU time 20.67 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:18:34 PM PDT 24
Peak memory 265756 kb
Host smart-ab500652-55ba-4eac-a5b4-7b9efd22011d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686829924 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2686829924
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3935095885
Short name T524
Test name
Test status
Simulation time 10025061700 ps
CPU time 65.75 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:19:19 PM PDT 24
Peak memory 276596 kb
Host smart-b26c0ab1-ac4b-4dae-96a3-9f2476568f16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935095885 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3935095885
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.4008187731
Short name T522
Test name
Test status
Simulation time 25253900 ps
CPU time 13.49 seconds
Started Jun 27 05:18:20 PM PDT 24
Finished Jun 27 05:18:35 PM PDT 24
Peak memory 260368 kb
Host smart-78f254e9-90b4-4674-a2b6-2e071cc83888
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008187731 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.4008187731
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2768665509
Short name T952
Test name
Test status
Simulation time 80147505300 ps
CPU time 901.79 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:32:59 PM PDT 24
Peak memory 265424 kb
Host smart-772027ca-75cc-4131-8f02-babd7cb16457
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768665509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2768665509
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1066515124
Short name T313
Test name
Test status
Simulation time 8382753700 ps
CPU time 158.55 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:20:37 PM PDT 24
Peak memory 263624 kb
Host smart-05199d9d-5c06-48cc-b9c8-3380b4b7dbed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066515124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1066515124
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.1781565746
Short name T1029
Test name
Test status
Simulation time 6351525200 ps
CPU time 158.82 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:20:35 PM PDT 24
Peak memory 298016 kb
Host smart-b76a494d-8764-46de-ab9a-1746feb47026
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781565746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.1781565746
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.874178935
Short name T591
Test name
Test status
Simulation time 6068872100 ps
CPU time 148.49 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:20:28 PM PDT 24
Peak memory 292928 kb
Host smart-1d1e4073-5102-4abc-84df-427cfa19e527
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874178935 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.874178935
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.584225828
Short name T421
Test name
Test status
Simulation time 1943498000 ps
CPU time 62.04 seconds
Started Jun 27 05:17:53 PM PDT 24
Finished Jun 27 05:18:57 PM PDT 24
Peak memory 263124 kb
Host smart-0832adff-8444-4464-b0d4-a958a751318f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584225828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.584225828
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.4062656107
Short name T630
Test name
Test status
Simulation time 15023200 ps
CPU time 13.48 seconds
Started Jun 27 05:18:20 PM PDT 24
Finished Jun 27 05:18:35 PM PDT 24
Peak memory 260964 kb
Host smart-386c80e9-39cd-4868-a78a-dd1d5ae68d06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062656107 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.4062656107
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3304577577
Short name T744
Test name
Test status
Simulation time 11690272500 ps
CPU time 248.11 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:22:08 PM PDT 24
Peak memory 275020 kb
Host smart-6f416eb4-e131-482a-b7bc-9981afc37c73
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304577577 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.3304577577
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.478154705
Short name T956
Test name
Test status
Simulation time 156821700 ps
CPU time 132.65 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:20:13 PM PDT 24
Peak memory 260588 kb
Host smart-d224af49-67d7-4d5b-bcfe-dbb209226a96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478154705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.478154705
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.599468011
Short name T623
Test name
Test status
Simulation time 54395800 ps
CPU time 71.55 seconds
Started Jun 27 05:17:55 PM PDT 24
Finished Jun 27 05:19:09 PM PDT 24
Peak memory 263472 kb
Host smart-3fe58f0a-6627-4e52-abf1-33d87178dd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599468011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.599468011
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.4108401598
Short name T157
Test name
Test status
Simulation time 20140400 ps
CPU time 14.09 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:18:13 PM PDT 24
Peak memory 265336 kb
Host smart-e24a2b2a-2aef-46b4-a10f-9533a342068c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108401598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.flash_ctrl_prog_reset.4108401598
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3057073886
Short name T1015
Test name
Test status
Simulation time 217240200 ps
CPU time 148.09 seconds
Started Jun 27 05:17:59 PM PDT 24
Finished Jun 27 05:20:29 PM PDT 24
Peak memory 269300 kb
Host smart-2a688fa8-bd03-4387-8c7d-61cb7cf26c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057073886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3057073886
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2791939111
Short name T818
Test name
Test status
Simulation time 849941300 ps
CPU time 110.76 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:19:50 PM PDT 24
Peak memory 281300 kb
Host smart-6cb6c2bc-7534-4eaf-bab1-19bdcba4a8f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791939111 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2791939111
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1649939652
Short name T191
Test name
Test status
Simulation time 14676321700 ps
CPU time 611.4 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:28:10 PM PDT 24
Peak memory 314704 kb
Host smart-9beb5958-9df0-47ef-b5b1-6bad0f623f9a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649939652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.1649939652
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.666623071
Short name T612
Test name
Test status
Simulation time 69644500 ps
CPU time 31.92 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:18:31 PM PDT 24
Peak memory 275908 kb
Host smart-7be35e86-911f-4ba8-a7d2-ab92b0183faf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666623071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_rw_evict.666623071
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.4693851
Short name T142
Test name
Test status
Simulation time 25118357900 ps
CPU time 91.81 seconds
Started Jun 27 05:18:22 PM PDT 24
Finished Jun 27 05:19:55 PM PDT 24
Peak memory 264032 kb
Host smart-563b8835-b37b-4318-8f9d-d128f8e97fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4693851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.4693851
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.2986635227
Short name T759
Test name
Test status
Simulation time 160713600 ps
CPU time 121.18 seconds
Started Jun 27 05:17:57 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 276512 kb
Host smart-62719648-b62c-48e2-a6bc-3be264620bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986635227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2986635227
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2820605675
Short name T535
Test name
Test status
Simulation time 2393312000 ps
CPU time 181.62 seconds
Started Jun 27 05:17:56 PM PDT 24
Finished Jun 27 05:21:00 PM PDT 24
Peak memory 260356 kb
Host smart-79bdfbb5-5599-4cc6-aa70-4043e457c7f8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820605675 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.2820605675
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2362943356
Short name T1108
Test name
Test status
Simulation time 43131700 ps
CPU time 13.77 seconds
Started Jun 27 05:18:29 PM PDT 24
Finished Jun 27 05:18:44 PM PDT 24
Peak memory 258512 kb
Host smart-b91011dc-3ff3-4e41-8cbb-fe2b4983020b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362943356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2362943356
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.3311673139
Short name T891
Test name
Test status
Simulation time 28695400 ps
CPU time 15.72 seconds
Started Jun 27 05:18:32 PM PDT 24
Finished Jun 27 05:18:49 PM PDT 24
Peak memory 275448 kb
Host smart-916dae5f-b4a8-4a3b-af3b-d99e140f085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311673139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3311673139
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2490161046
Short name T501
Test name
Test status
Simulation time 10026106200 ps
CPU time 70.55 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:19:43 PM PDT 24
Peak memory 280296 kb
Host smart-8093c48e-197d-48d7-bf12-98e16ff4f67c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490161046 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2490161046
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2726859290
Short name T279
Test name
Test status
Simulation time 48263400 ps
CPU time 14.19 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:18:46 PM PDT 24
Peak memory 265256 kb
Host smart-cc0744ab-b7d9-452d-91a7-ae2e72c0dbf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726859290 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2726859290
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1406492207
Short name T12
Test name
Test status
Simulation time 160187330200 ps
CPU time 881.21 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:32:55 PM PDT 24
Peak memory 264684 kb
Host smart-0b08e492-345a-4157-b1b7-4392e4960886
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406492207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1406492207
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2058442918
Short name T860
Test name
Test status
Simulation time 1450825200 ps
CPU time 63.42 seconds
Started Jun 27 05:18:21 PM PDT 24
Finished Jun 27 05:19:26 PM PDT 24
Peak memory 261324 kb
Host smart-13715115-2a41-4859-8854-5ae7f101f45f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058442918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2058442918
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.443463817
Short name T8
Test name
Test status
Simulation time 91611966900 ps
CPU time 198.11 seconds
Started Jun 27 05:18:14 PM PDT 24
Finished Jun 27 05:21:33 PM PDT 24
Peak memory 293404 kb
Host smart-2ad691f8-bb55-4277-8e3b-ef9ddf646bce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443463817 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.443463817
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.4228813862
Short name T1011
Test name
Test status
Simulation time 1924148700 ps
CPU time 80.77 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:19:34 PM PDT 24
Peak memory 261008 kb
Host smart-b57df3a7-e5e0-4ab6-af07-94e97718a30b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228813862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.4
228813862
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.600273467
Short name T159
Test name
Test status
Simulation time 48605500 ps
CPU time 13.63 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:18:46 PM PDT 24
Peak memory 265656 kb
Host smart-11b007e5-5f10-47fc-af86-76ec178dd76e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600273467 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.600273467
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1151029748
Short name T120
Test name
Test status
Simulation time 13890243000 ps
CPU time 222.18 seconds
Started Jun 27 05:18:13 PM PDT 24
Finished Jun 27 05:21:56 PM PDT 24
Peak memory 272852 kb
Host smart-013bd328-3150-452d-9542-5ad1a282c86b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151029748 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.1151029748
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.299879695
Short name T817
Test name
Test status
Simulation time 171314700 ps
CPU time 113.44 seconds
Started Jun 27 05:18:11 PM PDT 24
Finished Jun 27 05:20:06 PM PDT 24
Peak memory 265324 kb
Host smart-632b511b-5275-40bf-8b84-cc929ea10c9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299879695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ot
p_reset.299879695
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.2235723955
Short name T823
Test name
Test status
Simulation time 104065200 ps
CPU time 282.8 seconds
Started Jun 27 05:18:20 PM PDT 24
Finished Jun 27 05:23:05 PM PDT 24
Peak memory 263336 kb
Host smart-5b6cb682-5349-45ab-8d24-8d53a790841e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2235723955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2235723955
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.3783105571
Short name T534
Test name
Test status
Simulation time 257062300 ps
CPU time 18.19 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:18:31 PM PDT 24
Peak memory 265260 kb
Host smart-07da5042-5024-4f77-90ec-5a39a3165cc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783105571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.flash_ctrl_prog_reset.3783105571
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2645953937
Short name T938
Test name
Test status
Simulation time 2171239800 ps
CPU time 1173.24 seconds
Started Jun 27 05:18:12 PM PDT 24
Finished Jun 27 05:37:47 PM PDT 24
Peak memory 287768 kb
Host smart-c187cdec-e6af-4d10-a284-d5159af62834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645953937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2645953937
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3291946869
Short name T196
Test name
Test status
Simulation time 130819500 ps
CPU time 34.87 seconds
Started Jun 27 05:18:32 PM PDT 24
Finished Jun 27 05:19:08 PM PDT 24
Peak memory 275796 kb
Host smart-0803f9d9-514f-4877-8a56-80aa8ec72afc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291946869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3291946869
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.460182160
Short name T506
Test name
Test status
Simulation time 507521400 ps
CPU time 118.05 seconds
Started Jun 27 05:18:11 PM PDT 24
Finished Jun 27 05:20:10 PM PDT 24
Peak memory 291620 kb
Host smart-95d36da1-d9f3-474d-b0a1-7654b764766b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460182160 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.flash_ctrl_ro.460182160
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2569944339
Short name T611
Test name
Test status
Simulation time 9181726300 ps
CPU time 605.98 seconds
Started Jun 27 05:18:22 PM PDT 24
Finished Jun 27 05:28:30 PM PDT 24
Peak memory 310776 kb
Host smart-f35fe001-f965-448f-b697-5da2454bbca3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569944339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2569944339
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.3907524591
Short name T470
Test name
Test status
Simulation time 44017500 ps
CPU time 31.92 seconds
Started Jun 27 05:18:13 PM PDT 24
Finished Jun 27 05:18:46 PM PDT 24
Peak memory 275900 kb
Host smart-e0617a19-9028-4800-ad0d-c498ca7b269c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907524591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.3907524591
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.178304033
Short name T841
Test name
Test status
Simulation time 102171200 ps
CPU time 31.33 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:19:03 PM PDT 24
Peak memory 276100 kb
Host smart-9187e58d-fd03-4cd8-a3ee-2f7d84663d50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178304033 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.178304033
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.254617825
Short name T1034
Test name
Test status
Simulation time 3016158700 ps
CPU time 81.52 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:19:54 PM PDT 24
Peak memory 264296 kb
Host smart-87cae2c0-37c6-46c2-acbd-bb4a760d564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254617825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.254617825
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.3156486400
Short name T431
Test name
Test status
Simulation time 92982900 ps
CPU time 74.92 seconds
Started Jun 27 05:18:20 PM PDT 24
Finished Jun 27 05:19:36 PM PDT 24
Peak memory 275700 kb
Host smart-05689022-bec9-4c2a-b1af-b3e7a5a5c0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156486400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3156486400
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.3462620748
Short name T1104
Test name
Test status
Simulation time 7010777300 ps
CPU time 128.96 seconds
Started Jun 27 05:18:14 PM PDT 24
Finished Jun 27 05:20:24 PM PDT 24
Peak memory 261236 kb
Host smart-710d969d-d05b-4a0d-bbb3-24b90393afd5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462620748 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.3462620748
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.116111490
Short name T967
Test name
Test status
Simulation time 78241100 ps
CPU time 13.84 seconds
Started Jun 27 05:18:51 PM PDT 24
Finished Jun 27 05:19:06 PM PDT 24
Peak memory 258604 kb
Host smart-20fca8e2-93be-4ced-8a7e-c62887682469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116111490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.116111490
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.3846902490
Short name T149
Test name
Test status
Simulation time 51391800 ps
CPU time 22.28 seconds
Started Jun 27 05:18:51 PM PDT 24
Finished Jun 27 05:19:14 PM PDT 24
Peak memory 274036 kb
Host smart-158da718-8140-4806-b63b-44b176fd34d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846902490 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.3846902490
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3933219808
Short name T1113
Test name
Test status
Simulation time 10011561900 ps
CPU time 152.64 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:21:24 PM PDT 24
Peak memory 398156 kb
Host smart-ddff1df1-7c9e-4ac1-836f-6f98d7370690
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933219808 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3933219808
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.435662353
Short name T1022
Test name
Test status
Simulation time 25686800 ps
CPU time 13.64 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:19:05 PM PDT 24
Peak memory 260464 kb
Host smart-21308a51-9813-4f98-8edb-4f57459ed310
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435662353 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.435662353
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2964947081
Short name T532
Test name
Test status
Simulation time 160179680900 ps
CPU time 815.61 seconds
Started Jun 27 05:18:36 PM PDT 24
Finished Jun 27 05:32:12 PM PDT 24
Peak memory 264092 kb
Host smart-3df32bab-e035-42b1-b61a-342ce552901b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964947081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2964947081
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.656795114
Short name T777
Test name
Test status
Simulation time 7298714800 ps
CPU time 40.64 seconds
Started Jun 27 05:18:28 PM PDT 24
Finished Jun 27 05:19:10 PM PDT 24
Peak memory 263248 kb
Host smart-876e0e7d-c33a-492c-8cd2-65c7c5f79755
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656795114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h
w_sec_otp.656795114
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.4096246134
Short name T859
Test name
Test status
Simulation time 3796708400 ps
CPU time 226.1 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:22:17 PM PDT 24
Peak memory 285176 kb
Host smart-5ab8b4bb-7c68-4b60-bb2f-9deb1497a947
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096246134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.4096246134
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1097708825
Short name T141
Test name
Test status
Simulation time 5929130200 ps
CPU time 128.3 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:20:39 PM PDT 24
Peak memory 293320 kb
Host smart-f8928e9c-2337-4d83-bfcd-bf82b24c61cd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097708825 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1097708825
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1319305137
Short name T284
Test name
Test status
Simulation time 3916746700 ps
CPU time 60.82 seconds
Started Jun 27 05:18:29 PM PDT 24
Finished Jun 27 05:19:31 PM PDT 24
Peak memory 263076 kb
Host smart-449055c9-32ba-47af-91e2-426dfcf30616
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319305137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
319305137
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.199351466
Short name T1021
Test name
Test status
Simulation time 14920600 ps
CPU time 13.88 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:19:04 PM PDT 24
Peak memory 260236 kb
Host smart-0b5dc1d3-173d-43cc-a0e8-646762e31e1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199351466 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.199351466
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.1030457200
Short name T125
Test name
Test status
Simulation time 14907965200 ps
CPU time 402.91 seconds
Started Jun 27 05:18:29 PM PDT 24
Finished Jun 27 05:25:13 PM PDT 24
Peak memory 274504 kb
Host smart-cb2de353-7e70-4903-966a-86e74bd7422f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030457200 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.1030457200
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.1267215650
Short name T708
Test name
Test status
Simulation time 288286400 ps
CPU time 130.71 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:20:44 PM PDT 24
Peak memory 260324 kb
Host smart-712acd65-1ccc-4461-bebf-89352d067522
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267215650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.1267215650
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1397818439
Short name T557
Test name
Test status
Simulation time 78478600 ps
CPU time 192.97 seconds
Started Jun 27 05:18:32 PM PDT 24
Finished Jun 27 05:21:46 PM PDT 24
Peak memory 263428 kb
Host smart-6a1f6585-876f-4638-a4c0-78279589931c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397818439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1397818439
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.3376524740
Short name T840
Test name
Test status
Simulation time 73035100 ps
CPU time 13.82 seconds
Started Jun 27 05:18:29 PM PDT 24
Finished Jun 27 05:18:44 PM PDT 24
Peak memory 265460 kb
Host smart-f31a3e00-4166-4e78-a29a-233bfd59d3b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376524740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.flash_ctrl_prog_reset.3376524740
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.1567365048
Short name T1098
Test name
Test status
Simulation time 1537742900 ps
CPU time 1507.39 seconds
Started Jun 27 05:18:32 PM PDT 24
Finished Jun 27 05:43:40 PM PDT 24
Peak memory 291172 kb
Host smart-4cdda408-6fbd-4d93-bd9f-9aea6580a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567365048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1567365048
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.1695477100
Short name T954
Test name
Test status
Simulation time 56145500 ps
CPU time 33.46 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:19:25 PM PDT 24
Peak memory 275672 kb
Host smart-e33fff83-fc95-4bed-84d0-d7a5ed432d1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695477100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.1695477100
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.272324090
Short name T68
Test name
Test status
Simulation time 9704413300 ps
CPU time 147.02 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:20:58 PM PDT 24
Peak memory 290368 kb
Host smart-3ca88c4d-5644-4aa0-88ee-6d70c99af3b2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272324090 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.flash_ctrl_ro.272324090
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.2284500096
Short name T210
Test name
Test status
Simulation time 4154520900 ps
CPU time 505.95 seconds
Started Jun 27 05:18:36 PM PDT 24
Finished Jun 27 05:27:02 PM PDT 24
Peak memory 309624 kb
Host smart-f79ab7b9-83c9-4480-8bd8-272e18131a0f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284500096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.2284500096
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.2108767858
Short name T359
Test name
Test status
Simulation time 29986000 ps
CPU time 31.44 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:19:03 PM PDT 24
Peak memory 275712 kb
Host smart-5ca4c21c-0d14-4e86-990b-8802cbd42c89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108767858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.2108767858
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2975490648
Short name T667
Test name
Test status
Simulation time 83335800 ps
CPU time 29.08 seconds
Started Jun 27 05:18:30 PM PDT 24
Finished Jun 27 05:19:01 PM PDT 24
Peak memory 277036 kb
Host smart-f400def0-3d02-4916-846e-e4cc6487dc4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975490648 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2975490648
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.567255920
Short name T1083
Test name
Test status
Simulation time 6028303000 ps
CPU time 73.34 seconds
Started Jun 27 05:18:51 PM PDT 24
Finished Jun 27 05:20:05 PM PDT 24
Peak memory 264224 kb
Host smart-50b1c96a-14e1-453a-b688-ad21524e7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567255920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.567255920
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.4076951729
Short name T785
Test name
Test status
Simulation time 3405298200 ps
CPU time 131.76 seconds
Started Jun 27 05:18:32 PM PDT 24
Finished Jun 27 05:20:45 PM PDT 24
Peak memory 281884 kb
Host smart-af71d072-500e-4c6a-8af0-fb9b0edc6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076951729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.4076951729
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.3739855401
Short name T861
Test name
Test status
Simulation time 2078600400 ps
CPU time 182.58 seconds
Started Jun 27 05:18:31 PM PDT 24
Finished Jun 27 05:21:35 PM PDT 24
Peak memory 260288 kb
Host smart-9d6a473a-f52b-43ae-a368-96aaf3f725ce
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739855401 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.3739855401
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2328280952
Short name T1071
Test name
Test status
Simulation time 277650500 ps
CPU time 15.11 seconds
Started Jun 27 05:19:08 PM PDT 24
Finished Jun 27 05:19:24 PM PDT 24
Peak memory 265436 kb
Host smart-8ddcca10-fc13-42b0-a0a1-c61518418006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328280952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2328280952
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2575949353
Short name T583
Test name
Test status
Simulation time 53477800 ps
CPU time 13.51 seconds
Started Jun 27 05:19:12 PM PDT 24
Finished Jun 27 05:19:26 PM PDT 24
Peak memory 275224 kb
Host smart-1d05cbf7-1997-4e6d-a70c-5703a0160ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575949353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2575949353
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.2933402237
Short name T980
Test name
Test status
Simulation time 12875500 ps
CPU time 22.03 seconds
Started Jun 27 05:19:11 PM PDT 24
Finished Jun 27 05:19:34 PM PDT 24
Peak memory 274032 kb
Host smart-fd0a097c-edb3-461e-adf7-9ca6f23da88c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933402237 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.2933402237
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3126789514
Short name T571
Test name
Test status
Simulation time 10014162800 ps
CPU time 113.97 seconds
Started Jun 27 05:19:09 PM PDT 24
Finished Jun 27 05:21:04 PM PDT 24
Peak memory 352324 kb
Host smart-0e9f2fb5-9bb7-4f85-ab68-1aab4467e25a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126789514 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3126789514
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.4168965013
Short name T1019
Test name
Test status
Simulation time 15115200 ps
CPU time 13.65 seconds
Started Jun 27 05:19:08 PM PDT 24
Finished Jun 27 05:19:23 PM PDT 24
Peak memory 258760 kb
Host smart-0ea0d6f4-55dc-406b-9445-392793437686
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168965013 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.4168965013
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3380012451
Short name T469
Test name
Test status
Simulation time 40121189700 ps
CPU time 811.73 seconds
Started Jun 27 05:18:53 PM PDT 24
Finished Jun 27 05:32:26 PM PDT 24
Peak memory 264680 kb
Host smart-005d100c-9202-40bf-b791-899c4a76cd98
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380012451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.3380012451
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2960013897
Short name T760
Test name
Test status
Simulation time 4980815800 ps
CPU time 53.37 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:19:44 PM PDT 24
Peak memory 263708 kb
Host smart-10d917e5-740e-4108-9e36-1a0820468319
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960013897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2960013897
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1846871282
Short name T746
Test name
Test status
Simulation time 1980302500 ps
CPU time 168.87 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:21:40 PM PDT 24
Peak memory 294316 kb
Host smart-5444ef53-6d87-48aa-9771-087f08655cbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846871282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1846871282
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.645710185
Short name T705
Test name
Test status
Simulation time 22690431900 ps
CPU time 147.99 seconds
Started Jun 27 05:19:12 PM PDT 24
Finished Jun 27 05:21:40 PM PDT 24
Peak memory 294564 kb
Host smart-86d5ad1f-fa51-45b3-9147-70410f78cfa1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645710185 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.645710185
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.2941886928
Short name T422
Test name
Test status
Simulation time 14842092500 ps
CPU time 69.52 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 263100 kb
Host smart-a989e41a-bc1b-4ca0-a2c7-ffcef2fe3cc5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941886928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2
941886928
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1123940467
Short name T456
Test name
Test status
Simulation time 18139500 ps
CPU time 13.92 seconds
Started Jun 27 05:19:07 PM PDT 24
Finished Jun 27 05:19:22 PM PDT 24
Peak memory 260208 kb
Host smart-0279faf9-74c3-43fd-8ae6-695c7b741dfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123940467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1123940467
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.1273404487
Short name T124
Test name
Test status
Simulation time 19392193100 ps
CPU time 919.42 seconds
Started Jun 27 05:18:50 PM PDT 24
Finished Jun 27 05:34:11 PM PDT 24
Peak memory 275612 kb
Host smart-b2cb87bf-bbd8-4218-983f-4a06786bb7eb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273404487 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.1273404487
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3192420720
Short name T961
Test name
Test status
Simulation time 137750700 ps
CPU time 131.06 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:21:02 PM PDT 24
Peak memory 260628 kb
Host smart-91142a14-13be-4560-a20f-d86d2d0a68d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192420720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3192420720
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1250173589
Short name T123
Test name
Test status
Simulation time 995827400 ps
CPU time 320.48 seconds
Started Jun 27 05:18:53 PM PDT 24
Finished Jun 27 05:24:14 PM PDT 24
Peak memory 263552 kb
Host smart-579d43f8-a573-466b-91f9-dee5e93ed6b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250173589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1250173589
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.2685717280
Short name T660
Test name
Test status
Simulation time 55875300 ps
CPU time 13.39 seconds
Started Jun 27 05:19:08 PM PDT 24
Finished Jun 27 05:19:23 PM PDT 24
Peak memory 265568 kb
Host smart-15656dc8-948e-4b8d-8551-43a1aeaaad51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685717280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.flash_ctrl_prog_reset.2685717280
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1767108055
Short name T582
Test name
Test status
Simulation time 5043219500 ps
CPU time 714.48 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:30:44 PM PDT 24
Peak memory 286600 kb
Host smart-a153bf05-6e86-4e78-89f4-316ad67f4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767108055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1767108055
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.337233179
Short name T527
Test name
Test status
Simulation time 109112500 ps
CPU time 31.76 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:19:43 PM PDT 24
Peak memory 278192 kb
Host smart-2313bac3-5d22-47e9-a675-65b5e450ee04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337233179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.337233179
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.201593184
Short name T1062
Test name
Test status
Simulation time 1012394300 ps
CPU time 109.08 seconds
Started Jun 27 05:18:51 PM PDT 24
Finished Jun 27 05:20:41 PM PDT 24
Peak memory 290336 kb
Host smart-5f272acc-c679-4065-b410-7637e4f2ded4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201593184 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.flash_ctrl_ro.201593184
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.4229858030
Short name T791
Test name
Test status
Simulation time 5042458700 ps
CPU time 581.74 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:28:33 PM PDT 24
Peak memory 314820 kb
Host smart-7f240905-a48a-46f1-91ec-c7fa3bc0e3ca
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229858030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.4229858030
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3191006996
Short name T1041
Test name
Test status
Simulation time 7374325500 ps
CPU time 71.28 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:20:22 PM PDT 24
Peak memory 265160 kb
Host smart-acf8d6c2-d941-4a7d-bb2f-96e5e454862a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191006996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3191006996
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2506777404
Short name T762
Test name
Test status
Simulation time 42480100 ps
CPU time 168.8 seconds
Started Jun 27 05:18:51 PM PDT 24
Finished Jun 27 05:21:41 PM PDT 24
Peak memory 277856 kb
Host smart-9e159792-8e32-42dc-835d-def5dbcae4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506777404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2506777404
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.3650985243
Short name T1045
Test name
Test status
Simulation time 4490459400 ps
CPU time 196.44 seconds
Started Jun 27 05:18:49 PM PDT 24
Finished Jun 27 05:22:07 PM PDT 24
Peak memory 265584 kb
Host smart-913c58a5-d33b-4b11-9204-8314a76285ce
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650985243 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.3650985243
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.2806404140
Short name T95
Test name
Test status
Simulation time 47459000 ps
CPU time 14.8 seconds
Started Jun 27 05:19:25 PM PDT 24
Finished Jun 27 05:19:41 PM PDT 24
Peak memory 265768 kb
Host smart-7b001a4c-5819-4c1c-bc86-888df9da18e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806404140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
2806404140
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.587284577
Short name T1080
Test name
Test status
Simulation time 39272900 ps
CPU time 13.34 seconds
Started Jun 27 05:19:29 PM PDT 24
Finished Jun 27 05:19:43 PM PDT 24
Peak memory 275216 kb
Host smart-2381514e-4e0b-4737-8d62-75f6ce478425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587284577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.587284577
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.4256948398
Short name T536
Test name
Test status
Simulation time 17519000 ps
CPU time 22.08 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:19:51 PM PDT 24
Peak memory 273988 kb
Host smart-3a9feb0d-4948-4a7d-aca6-9aaacf065408
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256948398 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.4256948398
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1781440191
Short name T167
Test name
Test status
Simulation time 10018381000 ps
CPU time 73.86 seconds
Started Jun 27 05:19:25 PM PDT 24
Finished Jun 27 05:20:39 PM PDT 24
Peak memory 282376 kb
Host smart-6592e374-a8c7-4a94-b8ef-db0c65f25c02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781440191 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1781440191
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2594221563
Short name T351
Test name
Test status
Simulation time 41073800 ps
CPU time 13.49 seconds
Started Jun 27 05:19:29 PM PDT 24
Finished Jun 27 05:19:43 PM PDT 24
Peak memory 260548 kb
Host smart-e985825c-5d69-493c-a503-26d65aac20c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594221563 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2594221563
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2819404963
Short name T551
Test name
Test status
Simulation time 50127271400 ps
CPU time 865.64 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:33:37 PM PDT 24
Peak memory 264116 kb
Host smart-85c5845d-b1fb-4301-81be-78a032c18212
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819404963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2819404963
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.823634607
Short name T722
Test name
Test status
Simulation time 3612310100 ps
CPU time 162.32 seconds
Started Jun 27 05:19:09 PM PDT 24
Finished Jun 27 05:21:53 PM PDT 24
Peak memory 263484 kb
Host smart-d0ae6ee0-1abc-473a-a4b2-39f2ed609a20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823634607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.823634607
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.4208844715
Short name T261
Test name
Test status
Simulation time 2600279400 ps
CPU time 216.01 seconds
Started Jun 27 05:19:11 PM PDT 24
Finished Jun 27 05:22:48 PM PDT 24
Peak memory 285244 kb
Host smart-1dfe26b5-d4a8-4e19-aa28-b9e9f1262bc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208844715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.4208844715
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.347330899
Short name T466
Test name
Test status
Simulation time 32285867900 ps
CPU time 145.84 seconds
Started Jun 27 05:19:11 PM PDT 24
Finished Jun 27 05:21:38 PM PDT 24
Peak memory 293272 kb
Host smart-00be9f08-4a3d-49fd-a4c6-1af2771cafcd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347330899 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.347330899
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2170424599
Short name T846
Test name
Test status
Simulation time 2685259300 ps
CPU time 62.75 seconds
Started Jun 27 05:19:07 PM PDT 24
Finished Jun 27 05:20:10 PM PDT 24
Peak memory 263036 kb
Host smart-c4194226-9d68-402d-b227-3a7b41f0998a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170424599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
170424599
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3150782737
Short name T977
Test name
Test status
Simulation time 46749900 ps
CPU time 13.67 seconds
Started Jun 27 05:19:24 PM PDT 24
Finished Jun 27 05:19:38 PM PDT 24
Peak memory 261048 kb
Host smart-59073230-9b0d-4ad5-8547-5e096b7f7e18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150782737 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3150782737
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2446431120
Short name T627
Test name
Test status
Simulation time 4207987500 ps
CPU time 206.53 seconds
Started Jun 27 05:19:11 PM PDT 24
Finished Jun 27 05:22:38 PM PDT 24
Peak memory 263736 kb
Host smart-e16aba21-9739-46f7-a9a1-f0273174d598
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446431120 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.2446431120
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.81095011
Short name T562
Test name
Test status
Simulation time 150728700 ps
CPU time 111.48 seconds
Started Jun 27 05:19:08 PM PDT 24
Finished Jun 27 05:21:00 PM PDT 24
Peak memory 260572 kb
Host smart-74e0378a-82b0-48d1-977d-f9295928b0d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81095011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp
_reset.81095011
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1805864776
Short name T1038
Test name
Test status
Simulation time 7749252600 ps
CPU time 262.16 seconds
Started Jun 27 05:19:11 PM PDT 24
Finished Jun 27 05:23:34 PM PDT 24
Peak memory 263500 kb
Host smart-32975f3b-2f90-40fd-949b-17eac76a9a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805864776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1805864776
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2023796264
Short name T666
Test name
Test status
Simulation time 67816300 ps
CPU time 13.74 seconds
Started Jun 27 05:19:08 PM PDT 24
Finished Jun 27 05:19:22 PM PDT 24
Peak memory 265624 kb
Host smart-b2cc0680-6a3b-4aa2-a543-40cb5adb91d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023796264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.flash_ctrl_prog_reset.2023796264
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1336907264
Short name T513
Test name
Test status
Simulation time 150220000 ps
CPU time 179.49 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:22:11 PM PDT 24
Peak memory 273640 kb
Host smart-4aef958b-753f-4600-88e9-3c9c2c83269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336907264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1336907264
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.4206133257
Short name T787
Test name
Test status
Simulation time 200985000 ps
CPU time 31.45 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:19:42 PM PDT 24
Peak memory 278088 kb
Host smart-d8ecad25-6dfb-4957-91c4-62930ee711d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206133257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.4206133257
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.1892791692
Short name T504
Test name
Test status
Simulation time 459602800 ps
CPU time 119.3 seconds
Started Jun 27 05:19:10 PM PDT 24
Finished Jun 27 05:21:11 PM PDT 24
Peak memory 281968 kb
Host smart-ae1ef6f5-526a-499f-b1c1-468f14c3ea22
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892791692 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.1892791692
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.270587214
Short name T1078
Test name
Test status
Simulation time 44110900 ps
CPU time 31.91 seconds
Started Jun 27 05:19:07 PM PDT 24
Finished Jun 27 05:19:40 PM PDT 24
Peak memory 275760 kb
Host smart-c555a5c0-2b5d-4f02-9ac6-47fd9a2f45f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270587214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_rw_evict.270587214
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3187680289
Short name T573
Test name
Test status
Simulation time 31251900 ps
CPU time 31.61 seconds
Started Jun 27 05:19:09 PM PDT 24
Finished Jun 27 05:19:41 PM PDT 24
Peak memory 277052 kb
Host smart-0e805d45-8743-449c-b5a1-9539d57655fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187680289 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3187680289
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.282428727
Short name T663
Test name
Test status
Simulation time 2685108200 ps
CPU time 75.65 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:20:42 PM PDT 24
Peak memory 264380 kb
Host smart-640b19c8-e99f-4a15-91d2-9c789887652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282428727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.282428727
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.3530602038
Short name T479
Test name
Test status
Simulation time 80054100 ps
CPU time 120.86 seconds
Started Jun 27 05:19:07 PM PDT 24
Finished Jun 27 05:21:09 PM PDT 24
Peak memory 276484 kb
Host smart-9e8b1043-6226-47c2-a6fb-8c90031c90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530602038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.3530602038
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.2398977555
Short name T45
Test name
Test status
Simulation time 13690800 ps
CPU time 13.76 seconds
Started Jun 27 05:12:05 PM PDT 24
Finished Jun 27 05:12:19 PM PDT 24
Peak memory 261832 kb
Host smart-bb01c580-f3be-4cd5-80a6-35dc3e88ee08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398977555 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.2398977555
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2376925554
Short name T786
Test name
Test status
Simulation time 53887400 ps
CPU time 13.73 seconds
Started Jun 27 05:12:37 PM PDT 24
Finished Jun 27 05:12:52 PM PDT 24
Peak memory 265648 kb
Host smart-61809ad2-d6b0-4022-82d3-b3a27321032d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376925554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
376925554
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3649403553
Short name T226
Test name
Test status
Simulation time 68720400 ps
CPU time 13.66 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:12:49 PM PDT 24
Peak memory 261936 kb
Host smart-69c2e0ba-50e8-4649-8e2a-c3335cc9ba4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649403553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3649403553
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1533871733
Short name T813
Test name
Test status
Simulation time 14022300 ps
CPU time 14.36 seconds
Started Jun 27 05:12:04 PM PDT 24
Finished Jun 27 05:12:20 PM PDT 24
Peak memory 275324 kb
Host smart-839bde1c-c1fe-46d0-abac-c178b6d57eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533871733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1533871733
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2534118794
Short name T426
Test name
Test status
Simulation time 192312600 ps
CPU time 106.61 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:13:38 PM PDT 24
Peak memory 275900 kb
Host smart-3aeae430-0f35-43f1-8aa5-e1b2f2d964c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534118794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2534118794
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1318170591
Short name T635
Test name
Test status
Simulation time 6704214600 ps
CPU time 549.01 seconds
Started Jun 27 05:11:49 PM PDT 24
Finished Jun 27 05:20:59 PM PDT 24
Peak memory 263688 kb
Host smart-c2dcafe6-c71d-4019-b543-115f20088929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318170591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1318170591
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3562345262
Short name T602
Test name
Test status
Simulation time 4711652800 ps
CPU time 2220.42 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:48:52 PM PDT 24
Peak memory 263196 kb
Host smart-cedee809-1c29-4f9e-b28c-4417f1aab841
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3562345262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3562345262
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1641452821
Short name T985
Test name
Test status
Simulation time 2916009300 ps
CPU time 3072.08 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 06:03:04 PM PDT 24
Peak memory 265468 kb
Host smart-aa31bcf9-b05b-45e8-97da-08cee324a067
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641452821 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1641452821
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2497104924
Short name T86
Test name
Test status
Simulation time 1732964500 ps
CPU time 43.74 seconds
Started Jun 27 05:12:35 PM PDT 24
Finished Jun 27 05:13:20 PM PDT 24
Peak memory 265544 kb
Host smart-fb53757c-a4f6-4af1-8ddc-ce767a4f11f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497104924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2497104924
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.1402347117
Short name T753
Test name
Test status
Simulation time 418328557200 ps
CPU time 2658.99 seconds
Started Jun 27 05:11:53 PM PDT 24
Finished Jun 27 05:56:13 PM PDT 24
Peak memory 264664 kb
Host smart-fa07b32b-6879-436b-9a73-260e6b06f0fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402347117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.1402347117
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.2655288189
Short name T745
Test name
Test status
Simulation time 254278500 ps
CPU time 114.59 seconds
Started Jun 27 05:11:53 PM PDT 24
Finished Jun 27 05:13:48 PM PDT 24
Peak memory 263012 kb
Host smart-9da8367d-4323-4de2-8080-2978cebfb4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655288189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2655288189
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1379263987
Short name T875
Test name
Test status
Simulation time 47658900 ps
CPU time 14.1 seconds
Started Jun 27 05:12:35 PM PDT 24
Finished Jun 27 05:12:50 PM PDT 24
Peak memory 265180 kb
Host smart-684b62fe-7f96-4f65-a609-661e3894538b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379263987 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1379263987
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3266494044
Short name T1056
Test name
Test status
Simulation time 170494198000 ps
CPU time 1749.45 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:41:06 PM PDT 24
Peak memory 260936 kb
Host smart-bc2e8f60-e921-476d-b916-2dbbbfb0dc13
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266494044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3266494044
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2027426161
Short name T897
Test name
Test status
Simulation time 60136614900 ps
CPU time 826.1 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:25:42 PM PDT 24
Peak memory 264808 kb
Host smart-75eb029b-5ad4-49e7-b111-47c14ec47243
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027426161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.2027426161
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.159631703
Short name T319
Test name
Test status
Simulation time 3617955100 ps
CPU time 65.73 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:13:01 PM PDT 24
Peak memory 261316 kb
Host smart-7d5047ad-6703-4ae7-bc8f-cc068e83b326
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159631703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.159631703
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.146775192
Short name T986
Test name
Test status
Simulation time 1634059000 ps
CPU time 139.8 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:14:11 PM PDT 24
Peak memory 291768 kb
Host smart-1fb16101-706a-4149-94f1-3a9467c4e1f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146775192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash
_ctrl_intr_rd.146775192
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.860928591
Short name T1018
Test name
Test status
Simulation time 12296282800 ps
CPU time 263.55 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:16:16 PM PDT 24
Peak memory 285020 kb
Host smart-14be5325-01e0-4c36-8f70-19cb1982edfe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860928591 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.860928591
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.874514870
Short name T564
Test name
Test status
Simulation time 8815139800 ps
CPU time 67.11 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:13:03 PM PDT 24
Peak memory 260768 kb
Host smart-b1cd9b91-f967-4cd7-a076-7f12328b3044
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874514870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.874514870
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2901121014
Short name T1050
Test name
Test status
Simulation time 78269598000 ps
CPU time 212.82 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:15:24 PM PDT 24
Peak memory 260636 kb
Host smart-8d19b6ba-9882-48cb-8132-3102d77ac22b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290
1121014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2901121014
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3914099943
Short name T1060
Test name
Test status
Simulation time 8301079900 ps
CPU time 68.04 seconds
Started Jun 27 05:11:52 PM PDT 24
Finished Jun 27 05:13:02 PM PDT 24
Peak memory 263000 kb
Host smart-67ae14ed-d7b0-49b0-acbc-8b037b62cfe9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914099943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3914099943
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.648646797
Short name T521
Test name
Test status
Simulation time 149887500 ps
CPU time 13.78 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:12:49 PM PDT 24
Peak memory 261040 kb
Host smart-79f46e23-dca9-4a57-a5e4-e6ba2469c3ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648646797 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.648646797
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.3845959888
Short name T420
Test name
Test status
Simulation time 4003075700 ps
CPU time 141.04 seconds
Started Jun 27 05:11:52 PM PDT 24
Finished Jun 27 05:14:14 PM PDT 24
Peak memory 265540 kb
Host smart-49958ce5-293c-4204-b4cf-01abcf76d94c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845959888 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.3845959888
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.3954370057
Short name T544
Test name
Test status
Simulation time 40941000 ps
CPU time 131.73 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:14:04 PM PDT 24
Peak memory 260192 kb
Host smart-b450ffdd-c624-49d5-9a93-7cc9d7213af3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954370057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.3954370057
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.3055492258
Short name T624
Test name
Test status
Simulation time 4605439600 ps
CPU time 168.79 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:14:41 PM PDT 24
Peak memory 282240 kb
Host smart-b0285a6b-f890-4fdd-8b77-5243685ac450
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055492258 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.3055492258
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3771172190
Short name T214
Test name
Test status
Simulation time 304685700 ps
CPU time 18.98 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:12:54 PM PDT 24
Peak memory 262164 kb
Host smart-b731d613-e6cc-405a-9205-aa879e5c1300
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3771172190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3771172190
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.1216477412
Short name T720
Test name
Test status
Simulation time 4925377500 ps
CPU time 205.69 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:15:21 PM PDT 24
Peak memory 263448 kb
Host smart-09bb6b0d-28fb-4737-aaaa-8b3b93da4921
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216477412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1216477412
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2331991527
Short name T193
Test name
Test status
Simulation time 15238400 ps
CPU time 14.07 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:12:49 PM PDT 24
Peak memory 265824 kb
Host smart-7ce4288f-e882-483a-9b1a-eab6de82c4ac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331991527 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2331991527
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2428948318
Short name T218
Test name
Test status
Simulation time 5290485800 ps
CPU time 210.2 seconds
Started Jun 27 05:11:55 PM PDT 24
Finished Jun 27 05:15:26 PM PDT 24
Peak memory 260312 kb
Host smart-d012b4d9-4d90-42e4-8e97-02c8ec89eb44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428948318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.flash_ctrl_prog_reset.2428948318
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1958630700
Short name T733
Test name
Test status
Simulation time 6760961300 ps
CPU time 1067.3 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:29:38 PM PDT 24
Peak memory 286508 kb
Host smart-874039f9-f7ba-49f1-8150-08140f801df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958630700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1958630700
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.113779701
Short name T712
Test name
Test status
Simulation time 1413670400 ps
CPU time 181.6 seconds
Started Jun 27 05:11:48 PM PDT 24
Finished Jun 27 05:14:50 PM PDT 24
Peak memory 263240 kb
Host smart-2e3907e8-1280-43be-811e-7cc3637ccd1d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113779701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.113779701
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.4219133575
Short name T825
Test name
Test status
Simulation time 65345900 ps
CPU time 31.8 seconds
Started Jun 27 05:12:04 PM PDT 24
Finished Jun 27 05:12:37 PM PDT 24
Peak memory 275352 kb
Host smart-2fcfba67-8e66-4dd7-a136-694dcd715f1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219133575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.4219133575
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1691961595
Short name T949
Test name
Test status
Simulation time 80721400 ps
CPU time 33.99 seconds
Started Jun 27 05:12:03 PM PDT 24
Finished Jun 27 05:12:38 PM PDT 24
Peak memory 275824 kb
Host smart-3cadc993-96bb-49ee-91e8-b959268faec5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691961595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1691961595
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.710304020
Short name T942
Test name
Test status
Simulation time 79474800 ps
CPU time 26.68 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:12:18 PM PDT 24
Peak memory 273756 kb
Host smart-a752a872-495f-44d0-8a9f-a8f05815f957
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710304020 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.710304020
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.138848865
Short name T436
Test name
Test status
Simulation time 311825000 ps
CPU time 27.16 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:12:19 PM PDT 24
Peak memory 265720 kb
Host smart-aa76d619-1393-4fc9-94a6-b08d1e329e18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138848865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_read_word_sweep_serr.138848865
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.55184032
Short name T662
Test name
Test status
Simulation time 1806460700 ps
CPU time 118.67 seconds
Started Jun 27 05:11:52 PM PDT 24
Finished Jun 27 05:13:52 PM PDT 24
Peak memory 291620 kb
Host smart-dd46673c-1b71-4002-9acb-18e64ffdfc33
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55184032 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.flash_ctrl_ro.55184032
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.3360709155
Short name T186
Test name
Test status
Simulation time 633381000 ps
CPU time 169.77 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:14:41 PM PDT 24
Peak memory 290188 kb
Host smart-ee6e2e4b-f20c-4dd0-bb1d-9e8f1bd24f6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3360709155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3360709155
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1569943057
Short name T195
Test name
Test status
Simulation time 1015398200 ps
CPU time 140.66 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:14:13 PM PDT 24
Peak memory 297564 kb
Host smart-3cce6691-26b8-4805-93ea-aeca43545567
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569943057 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1569943057
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.3496443321
Short name T589
Test name
Test status
Simulation time 72263354900 ps
CPU time 613.32 seconds
Started Jun 27 05:11:50 PM PDT 24
Finished Jun 27 05:22:05 PM PDT 24
Peak memory 309780 kb
Host smart-e067fe29-f990-461b-a8f5-111a3ffcc759
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496443321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.3496443321
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.2780604475
Short name T133
Test name
Test status
Simulation time 51137800 ps
CPU time 28.07 seconds
Started Jun 27 05:11:53 PM PDT 24
Finished Jun 27 05:12:22 PM PDT 24
Peak memory 275836 kb
Host smart-f894917e-16fd-401c-a814-2397d6827804
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780604475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.2780604475
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.344620098
Short name T39
Test name
Test status
Simulation time 83805400 ps
CPU time 31.42 seconds
Started Jun 27 05:12:05 PM PDT 24
Finished Jun 27 05:12:37 PM PDT 24
Peak memory 277084 kb
Host smart-1ebbd5ac-a7e0-4275-9b1d-e6102dd1781e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344620098 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.344620098
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.897727392
Short name T931
Test name
Test status
Simulation time 4426015200 ps
CPU time 729.07 seconds
Started Jun 27 05:11:49 PM PDT 24
Finished Jun 27 05:23:59 PM PDT 24
Peak memory 313760 kb
Host smart-d08d6d6b-3b26-478a-b0be-9de1708a8bfb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897727392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_se
rr.897727392
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.509764463
Short name T432
Test name
Test status
Simulation time 5495482600 ps
CPU time 68.78 seconds
Started Jun 27 05:12:04 PM PDT 24
Finished Jun 27 05:13:14 PM PDT 24
Peak memory 264144 kb
Host smart-fd63a7b6-5359-441f-9aa9-7413d69174af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509764463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.509764463
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3043234211
Short name T578
Test name
Test status
Simulation time 3566324800 ps
CPU time 91.07 seconds
Started Jun 27 05:11:48 PM PDT 24
Finished Jun 27 05:13:19 PM PDT 24
Peak memory 265852 kb
Host smart-64d44300-6149-4705-a74e-536cff002166
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043234211 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3043234211
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.886128792
Short name T494
Test name
Test status
Simulation time 2293972700 ps
CPU time 106.18 seconds
Started Jun 27 05:11:54 PM PDT 24
Finished Jun 27 05:13:41 PM PDT 24
Peak memory 274364 kb
Host smart-728c67c2-7014-4607-af93-87943ded2ceb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886128792 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_counter.886128792
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.2842053763
Short name T434
Test name
Test status
Simulation time 23124200 ps
CPU time 99.38 seconds
Started Jun 27 05:11:51 PM PDT 24
Finished Jun 27 05:13:31 PM PDT 24
Peak memory 276088 kb
Host smart-acdc7e5c-353b-4cd4-985f-1cde691fd779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842053763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2842053763
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1429249410
Short name T65
Test name
Test status
Simulation time 40028800 ps
CPU time 23.66 seconds
Started Jun 27 05:11:48 PM PDT 24
Finished Jun 27 05:12:13 PM PDT 24
Peak memory 260132 kb
Host smart-dae35812-5f94-4c79-8935-87a3cc2c6328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429249410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1429249410
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2966554054
Short name T64
Test name
Test status
Simulation time 920843400 ps
CPU time 1030.17 seconds
Started Jun 27 05:12:04 PM PDT 24
Finished Jun 27 05:29:16 PM PDT 24
Peak memory 285220 kb
Host smart-8b1721c8-8306-4e7a-a72d-f860663da6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966554054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2966554054
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3790597599
Short name T443
Test name
Test status
Simulation time 45752400 ps
CPU time 26.26 seconds
Started Jun 27 05:11:47 PM PDT 24
Finished Jun 27 05:12:14 PM PDT 24
Peak memory 262716 kb
Host smart-a5efac92-ee2a-434f-895b-2a8e469e11ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790597599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3790597599
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.492630544
Short name T511
Test name
Test status
Simulation time 2115452100 ps
CPU time 171.26 seconds
Started Jun 27 05:11:56 PM PDT 24
Finished Jun 27 05:14:48 PM PDT 24
Peak memory 265600 kb
Host smart-fe9e2e08-89fd-4417-bb27-72fd63b66b33
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492630544 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_wo.492630544
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1931835768
Short name T483
Test name
Test status
Simulation time 37343000 ps
CPU time 13.66 seconds
Started Jun 27 05:19:30 PM PDT 24
Finished Jun 27 05:19:44 PM PDT 24
Peak memory 258712 kb
Host smart-1196fffe-bdd4-4fe5-9f5a-c8fd9737f138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931835768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1931835768
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.1967273287
Short name T962
Test name
Test status
Simulation time 48313300 ps
CPU time 16.08 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:19:43 PM PDT 24
Peak memory 275324 kb
Host smart-07f6b931-575e-4cc3-b482-8b21304de543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967273287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1967273287
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2885237256
Short name T1016
Test name
Test status
Simulation time 10962800 ps
CPU time 20.94 seconds
Started Jun 27 05:19:27 PM PDT 24
Finished Jun 27 05:19:48 PM PDT 24
Peak memory 274064 kb
Host smart-fa6fe8d9-9c2b-4899-b598-46efeda1a3e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885237256 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2885237256
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3779466990
Short name T418
Test name
Test status
Simulation time 1770996300 ps
CPU time 214.71 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:23:03 PM PDT 24
Peak memory 291632 kb
Host smart-08e94fca-042b-4844-b1bd-819b8f24236f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779466990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3779466990
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4284071518
Short name T707
Test name
Test status
Simulation time 12171394800 ps
CPU time 276.08 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:24:05 PM PDT 24
Peak memory 291236 kb
Host smart-f667eb09-1d67-4857-ae28-517e6b1b5439
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284071518 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.4284071518
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2080460691
Short name T533
Test name
Test status
Simulation time 73468900 ps
CPU time 133.76 seconds
Started Jun 27 05:19:25 PM PDT 24
Finished Jun 27 05:21:40 PM PDT 24
Peak memory 260336 kb
Host smart-c1bca4b2-1c52-4f82-a6f6-2478b516fe36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080460691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2080460691
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.1138262156
Short name T2
Test name
Test status
Simulation time 19925100 ps
CPU time 14.37 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:19:41 PM PDT 24
Peak memory 259308 kb
Host smart-cc28c9a6-1f6e-4827-8fca-59bffe996174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138262156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.flash_ctrl_prog_reset.1138262156
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1401716645
Short name T361
Test name
Test status
Simulation time 77877200 ps
CPU time 28.61 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:19:58 PM PDT 24
Peak memory 275912 kb
Host smart-5f9916ec-943f-4a3a-baba-f104463e26b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401716645 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1401716645
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3337257479
Short name T415
Test name
Test status
Simulation time 8325936500 ps
CPU time 91.01 seconds
Started Jun 27 05:19:25 PM PDT 24
Finished Jun 27 05:20:57 PM PDT 24
Peak memory 264184 kb
Host smart-08ee059e-8d6a-430d-afe5-5649b8cbd793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337257479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3337257479
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2325888652
Short name T945
Test name
Test status
Simulation time 105221200 ps
CPU time 148 seconds
Started Jun 27 05:19:27 PM PDT 24
Finished Jun 27 05:21:56 PM PDT 24
Peak memory 280884 kb
Host smart-1fada91b-8ad5-43dc-98fb-b7dba78ed79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325888652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2325888652
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2600362823
Short name T853
Test name
Test status
Simulation time 20629800 ps
CPU time 13.74 seconds
Started Jun 27 05:19:51 PM PDT 24
Finished Jun 27 05:20:06 PM PDT 24
Peak memory 265480 kb
Host smart-5578fe5d-339a-4c6a-b9eb-5b84be18a837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600362823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2600362823
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.4116135174
Short name T389
Test name
Test status
Simulation time 55880700 ps
CPU time 13.5 seconds
Started Jun 27 05:19:51 PM PDT 24
Finished Jun 27 05:20:06 PM PDT 24
Peak memory 275336 kb
Host smart-63bd3049-3832-42c2-96cd-eaea26d6c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116135174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.4116135174
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2863356863
Short name T757
Test name
Test status
Simulation time 19604906900 ps
CPU time 230.66 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:23:20 PM PDT 24
Peak memory 261228 kb
Host smart-d2772c5f-3d1b-4b09-8432-510dd8a77227
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863356863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2863356863
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.3437021726
Short name T907
Test name
Test status
Simulation time 2048485900 ps
CPU time 210.63 seconds
Started Jun 27 05:19:29 PM PDT 24
Finished Jun 27 05:23:00 PM PDT 24
Peak memory 291760 kb
Host smart-3c0fe000-6845-4978-a07c-6b42a03f6fbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437021726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.3437021726
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.692061721
Short name T338
Test name
Test status
Simulation time 49514173400 ps
CPU time 402.08 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:26:11 PM PDT 24
Peak memory 285008 kb
Host smart-08f52968-17d9-41ba-b32c-82441c814795
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692061721 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.692061721
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.1174769610
Short name T1052
Test name
Test status
Simulation time 391675500 ps
CPU time 134.04 seconds
Started Jun 27 05:19:25 PM PDT 24
Finished Jun 27 05:21:40 PM PDT 24
Peak memory 261412 kb
Host smart-277cfb31-b540-4959-b328-3d6a368e1c7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174769610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.1174769610
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1566818705
Short name T670
Test name
Test status
Simulation time 547135000 ps
CPU time 14.94 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:19:42 PM PDT 24
Peak memory 260236 kb
Host smart-1ddc4995-340a-4bf1-af68-01ea0228704f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566818705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.flash_ctrl_prog_reset.1566818705
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3849942050
Short name T790
Test name
Test status
Simulation time 101031200 ps
CPU time 30.78 seconds
Started Jun 27 05:19:28 PM PDT 24
Finished Jun 27 05:20:00 PM PDT 24
Peak memory 275876 kb
Host smart-cfd06fd8-f546-40a9-9338-c06a66caa4a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849942050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3849942050
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.992185274
Short name T358
Test name
Test status
Simulation time 95479000 ps
CPU time 28.87 seconds
Started Jun 27 05:19:26 PM PDT 24
Finished Jun 27 05:19:55 PM PDT 24
Peak memory 276040 kb
Host smart-bff4591f-223e-4693-b3b5-6455fe87e4bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992185274 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.992185274
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1185688483
Short name T500
Test name
Test status
Simulation time 90742200 ps
CPU time 144.83 seconds
Started Jun 27 05:19:29 PM PDT 24
Finished Jun 27 05:21:55 PM PDT 24
Peak memory 277212 kb
Host smart-481c4b7d-c390-464d-9681-77947b7d852e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185688483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1185688483
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.4150871224
Short name T1035
Test name
Test status
Simulation time 20896200 ps
CPU time 13.52 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:04 PM PDT 24
Peak memory 258740 kb
Host smart-9b0f5c68-f23b-4a3e-a514-7be2d7245466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150871224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
4150871224
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.536568497
Short name T898
Test name
Test status
Simulation time 27599200 ps
CPU time 15.97 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:06 PM PDT 24
Peak memory 284720 kb
Host smart-7051a067-673d-4cdb-a38e-f0fdc2c5b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536568497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.536568497
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.1040207592
Short name T1024
Test name
Test status
Simulation time 21836100 ps
CPU time 22.19 seconds
Started Jun 27 05:19:48 PM PDT 24
Finished Jun 27 05:20:12 PM PDT 24
Peak memory 273748 kb
Host smart-f36a4e34-2eb7-4386-970e-02383e033f08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040207592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.1040207592
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1905400821
Short name T640
Test name
Test status
Simulation time 1858331100 ps
CPU time 150.5 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:22:21 PM PDT 24
Peak memory 261444 kb
Host smart-ef9979c5-106d-46a6-bda8-f97f27ad1243
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905400821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.1905400821
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3139732546
Short name T1103
Test name
Test status
Simulation time 8090129000 ps
CPU time 146.79 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:22:18 PM PDT 24
Peak memory 294412 kb
Host smart-16d621f3-e220-4815-9a43-8f1af8e06147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139732546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3139732546
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1407507903
Short name T144
Test name
Test status
Simulation time 50725921600 ps
CPU time 345.04 seconds
Started Jun 27 05:19:52 PM PDT 24
Finished Jun 27 05:25:38 PM PDT 24
Peak memory 290204 kb
Host smart-f24c444d-8027-44ce-b96c-3543c4fcf3bb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407507903 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1407507903
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.3548721675
Short name T590
Test name
Test status
Simulation time 26432700 ps
CPU time 31.37 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:20:24 PM PDT 24
Peak memory 275924 kb
Host smart-2c80e67d-7f08-48e2-811e-55c6f964c266
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548721675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.3548721675
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2528603843
Short name T369
Test name
Test status
Simulation time 27948500 ps
CPU time 31.14 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:22 PM PDT 24
Peak memory 276152 kb
Host smart-72e1a61c-3233-41e1-b31c-e65631d94c44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528603843 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2528603843
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3583894009
Short name T659
Test name
Test status
Simulation time 77203500 ps
CPU time 99.35 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:21:31 PM PDT 24
Peak memory 276272 kb
Host smart-a7d63759-bc59-467e-80ab-c1370f4956aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583894009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3583894009
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.770109465
Short name T429
Test name
Test status
Simulation time 65843200 ps
CPU time 14.52 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:20:29 PM PDT 24
Peak memory 265548 kb
Host smart-32a45543-61ff-449e-9dce-48acf6a5a4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770109465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.770109465
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3443818049
Short name T1074
Test name
Test status
Simulation time 41429400 ps
CPU time 13.48 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:20:28 PM PDT 24
Peak memory 275192 kb
Host smart-b863e70d-5132-4df0-bb9f-092821293e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443818049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3443818049
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3661472483
Short name T26
Test name
Test status
Simulation time 112935600 ps
CPU time 22.38 seconds
Started Jun 27 05:19:48 PM PDT 24
Finished Jun 27 05:20:12 PM PDT 24
Peak memory 274024 kb
Host smart-c38d7f7b-18a1-49f2-a4c2-9ebe319168c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661472483 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3661472483
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1954791672
Short name T109
Test name
Test status
Simulation time 1130190200 ps
CPU time 82.28 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:21:12 PM PDT 24
Peak memory 261560 kb
Host smart-118f8c36-71eb-4b8d-b9d8-8aa5893f76dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954791672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1954791672
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.2387333323
Short name T773
Test name
Test status
Simulation time 941776300 ps
CPU time 116.56 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:21:49 PM PDT 24
Peak memory 294508 kb
Host smart-bc5225ec-bfc3-4bfe-8291-f3beb101c8d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387333323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.2387333323
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2366643362
Short name T215
Test name
Test status
Simulation time 112776141000 ps
CPU time 349.94 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:25:41 PM PDT 24
Peak memory 290480 kb
Host smart-a83ff6aa-915e-4588-83ea-8bae10e24809
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366643362 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2366643362
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.1978578160
Short name T75
Test name
Test status
Simulation time 41205900 ps
CPU time 132.13 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:22:04 PM PDT 24
Peak memory 261260 kb
Host smart-f1187313-0a3d-481d-ba56-a3584fd7411b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978578160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.1978578160
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.107739381
Short name T867
Test name
Test status
Simulation time 5800743400 ps
CPU time 186.98 seconds
Started Jun 27 05:19:50 PM PDT 24
Finished Jun 27 05:22:59 PM PDT 24
Peak memory 260892 kb
Host smart-fee21640-a985-4ee1-91cf-ae82c0c3416f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107739381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.flash_ctrl_prog_reset.107739381
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.3407071850
Short name T38
Test name
Test status
Simulation time 30897300 ps
CPU time 29.08 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:20 PM PDT 24
Peak memory 277176 kb
Host smart-51f64c9b-042a-492c-9ce6-4d2c24f4f37c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407071850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.3407071850
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3072737824
Short name T678
Test name
Test status
Simulation time 47256900 ps
CPU time 31.6 seconds
Started Jun 27 05:19:49 PM PDT 24
Finished Jun 27 05:20:23 PM PDT 24
Peak memory 275828 kb
Host smart-a448f073-e8f9-4d43-ae33-dc6d644da7fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072737824 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3072737824
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1287396536
Short name T1082
Test name
Test status
Simulation time 1096054300 ps
CPU time 61.41 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:21:17 PM PDT 24
Peak memory 265268 kb
Host smart-bbc47952-103d-4b2c-9fb8-48394f182d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287396536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1287396536
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.555586598
Short name T668
Test name
Test status
Simulation time 706488200 ps
CPU time 149.55 seconds
Started Jun 27 05:19:52 PM PDT 24
Finished Jun 27 05:22:23 PM PDT 24
Peak memory 281696 kb
Host smart-7a03d985-8c43-49a9-a3f3-ab6daf8d54ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555586598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.555586598
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.55695749
Short name T446
Test name
Test status
Simulation time 115104700 ps
CPU time 13.73 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:20:29 PM PDT 24
Peak memory 265584 kb
Host smart-bdcaac27-a4fb-45a5-be8a-9fc3d351cb71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55695749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.55695749
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3203435779
Short name T906
Test name
Test status
Simulation time 42651200 ps
CPU time 13.58 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:20:29 PM PDT 24
Peak memory 275408 kb
Host smart-40986149-7c52-4a92-a2a7-99dfd3c6227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203435779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3203435779
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3709736320
Short name T923
Test name
Test status
Simulation time 10401800 ps
CPU time 21.11 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:20:35 PM PDT 24
Peak memory 273864 kb
Host smart-211e2cf2-22ca-481a-a390-e12c83a2e831
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709736320 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3709736320
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.4205071028
Short name T323
Test name
Test status
Simulation time 8973047400 ps
CPU time 113.6 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:22:09 PM PDT 24
Peak memory 263020 kb
Host smart-4e61997d-c733-4bfe-8878-25e0c1d6baa7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205071028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.4205071028
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1129400952
Short name T964
Test name
Test status
Simulation time 1778067700 ps
CPU time 185.8 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:23:19 PM PDT 24
Peak memory 291792 kb
Host smart-28734139-2484-46a4-b01c-4b92279e587d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129400952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1129400952
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.1011491835
Short name T981
Test name
Test status
Simulation time 77912100 ps
CPU time 131.18 seconds
Started Jun 27 05:20:11 PM PDT 24
Finished Jun 27 05:22:23 PM PDT 24
Peak memory 260688 kb
Host smart-b6557154-e3cb-48d6-9efd-1149c7534e2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011491835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.1011491835
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.2767645111
Short name T1069
Test name
Test status
Simulation time 2198135300 ps
CPU time 189.56 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:23:24 PM PDT 24
Peak memory 260320 kb
Host smart-0ace9731-4ac0-412c-ae44-771a449d0a32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767645111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.flash_ctrl_prog_reset.2767645111
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.118225742
Short name T264
Test name
Test status
Simulation time 28294300 ps
CPU time 31.14 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:20:46 PM PDT 24
Peak memory 275924 kb
Host smart-a9e78e33-4a0d-478e-a582-fab7e6667632
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118225742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.118225742
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1776192133
Short name T892
Test name
Test status
Simulation time 168542200 ps
CPU time 28.17 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:20:42 PM PDT 24
Peak memory 275796 kb
Host smart-90df7109-b7fe-4d66-b54d-1bf7f6924654
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776192133 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.1776192133
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2906817753
Short name T407
Test name
Test status
Simulation time 1124957000 ps
CPU time 58.73 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:21:13 PM PDT 24
Peak memory 263516 kb
Host smart-6dd9e1bb-f6a8-4f44-9c3e-78da0e0db757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906817753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2906817753
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3780692092
Short name T305
Test name
Test status
Simulation time 22118000 ps
CPU time 53.33 seconds
Started Jun 27 05:20:16 PM PDT 24
Finished Jun 27 05:21:10 PM PDT 24
Peak memory 271660 kb
Host smart-2c613eba-7279-4b68-9961-09110498b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780692092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3780692092
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.711236779
Short name T871
Test name
Test status
Simulation time 41702200 ps
CPU time 13.73 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:20:27 PM PDT 24
Peak memory 258668 kb
Host smart-8285ed12-c219-4638-b0fa-2c4af232c262
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711236779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.711236779
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.708193677
Short name T439
Test name
Test status
Simulation time 15417600 ps
CPU time 16.23 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:20:30 PM PDT 24
Peak memory 275256 kb
Host smart-17653a51-fe4e-4933-8692-1e988d2379e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708193677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.708193677
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1169657089
Short name T569
Test name
Test status
Simulation time 29717800 ps
CPU time 22.21 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:20:35 PM PDT 24
Peak memory 273984 kb
Host smart-a06c03cd-aea1-428f-91d3-91acc1b7176a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169657089 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1169657089
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1428970561
Short name T321
Test name
Test status
Simulation time 4276363600 ps
CPU time 137.87 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:22:32 PM PDT 24
Peak memory 263208 kb
Host smart-096518da-0ab9-4b67-afb1-8f67dfe097b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428970561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1428970561
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.864898782
Short name T642
Test name
Test status
Simulation time 1270174000 ps
CPU time 233.45 seconds
Started Jun 27 05:20:16 PM PDT 24
Finished Jun 27 05:24:11 PM PDT 24
Peak memory 291856 kb
Host smart-7903f1bf-acde-4f38-9653-8ae1618dc25c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864898782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.864898782
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.1008262838
Short name T343
Test name
Test status
Simulation time 104433199200 ps
CPU time 304.1 seconds
Started Jun 27 05:20:14 PM PDT 24
Finished Jun 27 05:25:20 PM PDT 24
Peak memory 291228 kb
Host smart-2d78aa64-ae73-4fa5-8e18-37439e5c09e0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008262838 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.1008262838
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.3634489502
Short name T1070
Test name
Test status
Simulation time 77091800 ps
CPU time 113.56 seconds
Started Jun 27 05:20:12 PM PDT 24
Finished Jun 27 05:22:07 PM PDT 24
Peak memory 262736 kb
Host smart-eab04f87-8d1d-495d-9a78-3222e464263c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634489502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.3634489502
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.1843568756
Short name T425
Test name
Test status
Simulation time 64953500 ps
CPU time 13.79 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:20:28 PM PDT 24
Peak memory 259364 kb
Host smart-6b1d8ed7-2fa7-4447-ae4b-b00eddca8e7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843568756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.flash_ctrl_prog_reset.1843568756
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3359507482
Short name T594
Test name
Test status
Simulation time 28563600 ps
CPU time 98.86 seconds
Started Jun 27 05:20:13 PM PDT 24
Finished Jun 27 05:21:53 PM PDT 24
Peak memory 276340 kb
Host smart-74bc4df7-60e5-41c8-8611-b400e17a4835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359507482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3359507482
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.916851255
Short name T1054
Test name
Test status
Simulation time 100218800 ps
CPU time 13.57 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:20:45 PM PDT 24
Peak memory 258668 kb
Host smart-845a29b1-176e-4b6b-90b3-e0e8d64e402d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916851255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.916851255
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.2885881225
Short name T941
Test name
Test status
Simulation time 52771700 ps
CPU time 16.48 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:20:51 PM PDT 24
Peak memory 275484 kb
Host smart-592eed2b-2830-4b71-98b4-8f1933b50735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885881225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2885881225
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.281742704
Short name T755
Test name
Test status
Simulation time 155658400 ps
CPU time 22.03 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:20:54 PM PDT 24
Peak memory 265092 kb
Host smart-3e0b58fd-2cc9-4a56-abfd-6890d49f2057
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281742704 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.281742704
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.1333712192
Short name T738
Test name
Test status
Simulation time 3232720900 ps
CPU time 95.78 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:22:08 PM PDT 24
Peak memory 261288 kb
Host smart-405caec2-b8ec-4c9e-850d-12839427597e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333712192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.1333712192
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.1967903810
Short name T336
Test name
Test status
Simulation time 557867500 ps
CPU time 183.01 seconds
Started Jun 27 05:20:32 PM PDT 24
Finished Jun 27 05:23:36 PM PDT 24
Peak memory 293732 kb
Host smart-a2a63a01-0fda-4356-9e5c-711d57f56232
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967903810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.1967903810
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3988322943
Short name T348
Test name
Test status
Simulation time 12715496400 ps
CPU time 252.84 seconds
Started Jun 27 05:20:44 PM PDT 24
Finished Jun 27 05:24:58 PM PDT 24
Peak memory 291204 kb
Host smart-5c44f106-b06c-4c5d-bb66-96f235f4a8e6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988322943 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.3988322943
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.1743554337
Short name T656
Test name
Test status
Simulation time 71605900 ps
CPU time 132.56 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:22:45 PM PDT 24
Peak memory 265552 kb
Host smart-bfcbee16-f493-485b-aeab-683877593616
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743554337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.1743554337
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.1226658359
Short name T769
Test name
Test status
Simulation time 2894159900 ps
CPU time 194.97 seconds
Started Jun 27 05:20:36 PM PDT 24
Finished Jun 27 05:23:52 PM PDT 24
Peak memory 260888 kb
Host smart-dd640548-7c1f-448b-8151-1c685038b4cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226658359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.flash_ctrl_prog_reset.1226658359
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.1835633001
Short name T27
Test name
Test status
Simulation time 47020400 ps
CPU time 28.89 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:21:01 PM PDT 24
Peak memory 276132 kb
Host smart-260e3698-cba0-43cd-850d-8afafb52a060
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835633001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.1835633001
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.3361069980
Short name T258
Test name
Test status
Simulation time 28241400 ps
CPU time 28.64 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:21:01 PM PDT 24
Peak memory 276092 kb
Host smart-6371703c-e681-44f7-9a23-64d4bfc23710
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361069980 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.3361069980
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.165410410
Short name T1065
Test name
Test status
Simulation time 1402044200 ps
CPU time 65.65 seconds
Started Jun 27 05:20:45 PM PDT 24
Finished Jun 27 05:21:52 PM PDT 24
Peak memory 263700 kb
Host smart-9efde723-aa59-4157-b150-2da9e63122f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165410410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.165410410
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.1160927292
Short name T747
Test name
Test status
Simulation time 35687400 ps
CPU time 99.45 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:22:11 PM PDT 24
Peak memory 277516 kb
Host smart-2a05f11d-a475-487c-8ed7-2cfb8b6fb078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160927292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1160927292
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.539217733
Short name T1090
Test name
Test status
Simulation time 52122900 ps
CPU time 13.62 seconds
Started Jun 27 05:20:41 PM PDT 24
Finished Jun 27 05:20:56 PM PDT 24
Peak memory 265436 kb
Host smart-04932468-329a-4a28-a5d6-c2238601ae9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539217733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.539217733
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.1433987665
Short name T148
Test name
Test status
Simulation time 49373200 ps
CPU time 13.93 seconds
Started Jun 27 05:20:35 PM PDT 24
Finished Jun 27 05:20:50 PM PDT 24
Peak memory 275372 kb
Host smart-fa7a572a-c8b3-4224-9591-53487984ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433987665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1433987665
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.490865854
Short name T890
Test name
Test status
Simulation time 52764900 ps
CPU time 20.92 seconds
Started Jun 27 05:20:36 PM PDT 24
Finished Jun 27 05:20:58 PM PDT 24
Peak memory 273916 kb
Host smart-22f0b2dd-69bb-4e04-8244-60bb78a0b609
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490865854 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.490865854
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.993735693
Short name T491
Test name
Test status
Simulation time 4328690700 ps
CPU time 147.81 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:23:02 PM PDT 24
Peak memory 263132 kb
Host smart-313a0664-43ff-4c0d-9ba7-d23ca8fd857b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993735693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h
w_sec_otp.993735693
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.2386527722
Short name T843
Test name
Test status
Simulation time 6462193600 ps
CPU time 254.22 seconds
Started Jun 27 05:20:44 PM PDT 24
Finished Jun 27 05:24:59 PM PDT 24
Peak memory 291596 kb
Host smart-e9e93474-ec03-4bee-8dd0-2cc2d4b46a2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386527722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.2386527722
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1347210609
Short name T1068
Test name
Test status
Simulation time 8719754500 ps
CPU time 125.77 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:22:42 PM PDT 24
Peak memory 292808 kb
Host smart-e265d748-c46c-4f6b-9c64-3a40a50d8e1a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347210609 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1347210609
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.38131112
Short name T1084
Test name
Test status
Simulation time 9398160100 ps
CPU time 191.93 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:23:47 PM PDT 24
Peak memory 260812 kb
Host smart-08150dd6-69b1-412f-8ecf-f4bd2b642bad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.flash_ctrl_prog_reset.38131112
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.264629202
Short name T1058
Test name
Test status
Simulation time 132152700 ps
CPU time 30.9 seconds
Started Jun 27 05:20:32 PM PDT 24
Finished Jun 27 05:21:04 PM PDT 24
Peak memory 276124 kb
Host smart-14728277-13ae-4ff9-a91c-3c1357db2ca7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264629202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.264629202
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1680380328
Short name T493
Test name
Test status
Simulation time 38827300 ps
CPU time 30.34 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:21:05 PM PDT 24
Peak memory 275916 kb
Host smart-701c440f-5817-4b5a-96a1-dd92d7a1bffa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680380328 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1680380328
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.3171389859
Short name T1077
Test name
Test status
Simulation time 2667803500 ps
CPU time 71.26 seconds
Started Jun 27 05:20:36 PM PDT 24
Finished Jun 27 05:21:48 PM PDT 24
Peak memory 265576 kb
Host smart-b49205f2-3162-4fdb-804e-f36c8001fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171389859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.3171389859
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3333446936
Short name T438
Test name
Test status
Simulation time 20968800 ps
CPU time 97.7 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:22:13 PM PDT 24
Peak memory 277564 kb
Host smart-496c6207-94d9-4a68-a745-0e9dd0450005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333446936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3333446936
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.556385794
Short name T800
Test name
Test status
Simulation time 83633000 ps
CPU time 13.86 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:20:49 PM PDT 24
Peak memory 258672 kb
Host smart-10398af7-ec90-48a3-b808-a77802c22a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556385794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.556385794
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1462218221
Short name T728
Test name
Test status
Simulation time 13551500 ps
CPU time 15.9 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:20:52 PM PDT 24
Peak memory 275356 kb
Host smart-cbc70876-2d17-4ede-8a1a-7a7b04fb1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462218221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1462218221
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.3391965068
Short name T442
Test name
Test status
Simulation time 24182700 ps
CPU time 21.97 seconds
Started Jun 27 05:20:44 PM PDT 24
Finished Jun 27 05:21:07 PM PDT 24
Peak memory 273728 kb
Host smart-0e34c4ca-e20a-4ab5-b5bd-19d6a6147b8f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391965068 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.3391965068
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3646243878
Short name T987
Test name
Test status
Simulation time 1806922700 ps
CPU time 96.17 seconds
Started Jun 27 05:20:32 PM PDT 24
Finished Jun 27 05:22:09 PM PDT 24
Peak memory 261364 kb
Host smart-6787c949-75e5-4b7a-ab38-3fb6c8ecf65c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646243878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.3646243878
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.323767783
Short name T337
Test name
Test status
Simulation time 1131000400 ps
CPU time 153.24 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:23:08 PM PDT 24
Peak memory 296840 kb
Host smart-2b1fc383-6941-42cb-88d9-21e332f2c240
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323767783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flas
h_ctrl_intr_rd.323767783
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2586846124
Short name T654
Test name
Test status
Simulation time 5742747600 ps
CPU time 117.38 seconds
Started Jun 27 05:20:31 PM PDT 24
Finished Jun 27 05:22:29 PM PDT 24
Peak memory 293124 kb
Host smart-f3adc24b-dab1-44fb-a900-bf15c4340201
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586846124 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2586846124
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2839369672
Short name T765
Test name
Test status
Simulation time 74641500 ps
CPU time 135.12 seconds
Started Jun 27 05:20:38 PM PDT 24
Finished Jun 27 05:22:54 PM PDT 24
Peak memory 260332 kb
Host smart-e846ed13-e741-41aa-b03b-e78e43ddb61d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839369672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2839369672
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.202187522
Short name T1075
Test name
Test status
Simulation time 209556500 ps
CPU time 15.57 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:20:51 PM PDT 24
Peak memory 265436 kb
Host smart-63594031-20ad-4652-b504-e4b3f92de4cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202187522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 28.flash_ctrl_prog_reset.202187522
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1883804906
Short name T1106
Test name
Test status
Simulation time 68437200 ps
CPU time 31.14 seconds
Started Jun 27 05:20:32 PM PDT 24
Finished Jun 27 05:21:04 PM PDT 24
Peak memory 275892 kb
Host smart-7ee25e94-341a-48ef-8bea-1d751b20143a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883804906 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1883804906
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.2077529115
Short name T405
Test name
Test status
Simulation time 1081832500 ps
CPU time 59.52 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:21:35 PM PDT 24
Peak memory 265408 kb
Host smart-f77b217e-e6cb-4b74-a00b-2bf2a945c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077529115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2077529115
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.594859597
Short name T908
Test name
Test status
Simulation time 167295600 ps
CPU time 100.66 seconds
Started Jun 27 05:20:32 PM PDT 24
Finished Jun 27 05:22:14 PM PDT 24
Peak memory 276100 kb
Host smart-d2f06ebd-c4ec-43c3-a855-d8e86c89f993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594859597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.594859597
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2469269823
Short name T819
Test name
Test status
Simulation time 45609200 ps
CPU time 13.61 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:21:11 PM PDT 24
Peak memory 265476 kb
Host smart-59fd8207-fdba-472b-a712-6b808effcabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469269823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2469269823
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1809568286
Short name T1037
Test name
Test status
Simulation time 43274400 ps
CPU time 15.97 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:21:12 PM PDT 24
Peak memory 284848 kb
Host smart-511ed041-4143-4295-ab27-fbe3305d5e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809568286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1809568286
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2194423448
Short name T572
Test name
Test status
Simulation time 14414900 ps
CPU time 21.18 seconds
Started Jun 27 05:20:36 PM PDT 24
Finished Jun 27 05:20:58 PM PDT 24
Peak memory 265812 kb
Host smart-3f7d665d-2cae-4c4e-ae2b-674410f735e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194423448 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2194423448
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.151165348
Short name T781
Test name
Test status
Simulation time 7223372100 ps
CPU time 187.11 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:23:41 PM PDT 24
Peak memory 261380 kb
Host smart-ab7ece24-bc69-4244-9769-b233b2ba4379
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151165348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_h
w_sec_otp.151165348
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.679173393
Short name T673
Test name
Test status
Simulation time 9670237500 ps
CPU time 143.07 seconds
Started Jun 27 05:20:38 PM PDT 24
Finished Jun 27 05:23:02 PM PDT 24
Peak memory 294408 kb
Host smart-8bd7263c-5c64-4627-a3bf-45826ab49f71
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679173393 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.679173393
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1436155752
Short name T978
Test name
Test status
Simulation time 273432100 ps
CPU time 133.46 seconds
Started Jun 27 05:20:43 PM PDT 24
Finished Jun 27 05:22:57 PM PDT 24
Peak memory 260552 kb
Host smart-ee4215a0-4850-491e-8916-ba1ec9576e99
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436155752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1436155752
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1492659952
Short name T507
Test name
Test status
Simulation time 227905100 ps
CPU time 29.12 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:21:05 PM PDT 24
Peak memory 259464 kb
Host smart-eb99501e-c56d-4b84-b526-95986b4cd606
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492659952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.flash_ctrl_prog_reset.1492659952
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.1066664547
Short name T924
Test name
Test status
Simulation time 64271500 ps
CPU time 30.84 seconds
Started Jun 27 05:20:34 PM PDT 24
Finished Jun 27 05:21:06 PM PDT 24
Peak memory 277052 kb
Host smart-b5680c21-611d-4018-95e3-fbdbfc0da73f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066664547 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.1066664547
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3603549127
Short name T412
Test name
Test status
Simulation time 6092802700 ps
CPU time 73.54 seconds
Started Jun 27 05:20:33 PM PDT 24
Finished Jun 27 05:21:48 PM PDT 24
Peak memory 264628 kb
Host smart-af88c204-a344-42b7-81d0-1477d4509530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603549127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3603549127
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3697225205
Short name T827
Test name
Test status
Simulation time 44634500 ps
CPU time 73.15 seconds
Started Jun 27 05:20:35 PM PDT 24
Finished Jun 27 05:21:49 PM PDT 24
Peak memory 277044 kb
Host smart-dac2887e-e44f-4859-9641-bd841c6b50a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697225205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3697225205
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.687874752
Short name T1043
Test name
Test status
Simulation time 55150200 ps
CPU time 14.1 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:13:12 PM PDT 24
Peak memory 265540 kb
Host smart-d44640ec-d9a0-4193-ae8b-dc72fade7138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687874752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.687874752
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2977697175
Short name T458
Test name
Test status
Simulation time 14053100 ps
CPU time 16.28 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:13:13 PM PDT 24
Peak memory 275332 kb
Host smart-64ff27d6-afa3-474d-9a2c-b7e3793b8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977697175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2977697175
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.1504225781
Short name T155
Test name
Test status
Simulation time 504422700 ps
CPU time 105.85 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:14:44 PM PDT 24
Peak memory 274464 kb
Host smart-0e9b90fd-61da-43a9-8cd0-338873c832c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504225781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.1504225781
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.368012028
Short name T930
Test name
Test status
Simulation time 16843100 ps
CPU time 21.86 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:13:17 PM PDT 24
Peak memory 274060 kb
Host smart-d55fb02a-df70-4fe5-a188-59cda7097394
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368012028 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.368012028
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.2971558896
Short name T153
Test name
Test status
Simulation time 2840770100 ps
CPU time 343.23 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:18:18 PM PDT 24
Peak memory 263840 kb
Host smart-a2d7f9d3-2581-4631-b888-040f2a646ae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2971558896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2971558896
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.4118052520
Short name T679
Test name
Test status
Simulation time 9971870000 ps
CPU time 2226.57 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:50:02 PM PDT 24
Peak memory 265564 kb
Host smart-bb984189-81a4-4c87-af2b-e096de04d5e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4118052520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.4118052520
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2015383195
Short name T1053
Test name
Test status
Simulation time 678098900 ps
CPU time 882.59 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:27:38 PM PDT 24
Peak memory 273740 kb
Host smart-01293994-b2b7-4954-991e-a6969fc5b29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015383195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2015383195
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.752701360
Short name T831
Test name
Test status
Simulation time 281365400 ps
CPU time 24.43 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:13:19 PM PDT 24
Peak memory 263952 kb
Host smart-fe41fcc1-c07e-4ce9-8e38-dfc03146f180
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752701360 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_fetch_code.752701360
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.2093864235
Short name T85
Test name
Test status
Simulation time 308985200 ps
CPU time 40.31 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:13:34 PM PDT 24
Peak memory 265600 kb
Host smart-c6bd3dbc-a7bb-490e-9335-64217aed197c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093864235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.2093864235
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.1066675304
Short name T126
Test name
Test status
Simulation time 148692484000 ps
CPU time 4114.78 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 06:21:33 PM PDT 24
Peak memory 265424 kb
Host smart-3ace3e69-3083-42e9-a7f6-333670c59aab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066675304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.1066675304
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1607367047
Short name T497
Test name
Test status
Simulation time 283906585200 ps
CPU time 1748.51 seconds
Started Jun 27 05:12:57 PM PDT 24
Finished Jun 27 05:42:07 PM PDT 24
Peak memory 264488 kb
Host smart-f7df48e5-66a0-43f9-90fd-0f0f044bd0e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607367047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1607367047
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2606943466
Short name T259
Test name
Test status
Simulation time 143382100 ps
CPU time 130.16 seconds
Started Jun 27 05:12:33 PM PDT 24
Finished Jun 27 05:14:44 PM PDT 24
Peak memory 262940 kb
Host smart-d5dcef50-3988-49c0-be14-182eeaf9721b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2606943466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2606943466
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2436968483
Short name T570
Test name
Test status
Simulation time 10012548000 ps
CPU time 88.48 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:14:27 PM PDT 24
Peak memory 282844 kb
Host smart-a9bd1b99-2ceb-4e8e-815c-ccb63ecd3a69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436968483 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2436968483
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3350258635
Short name T1055
Test name
Test status
Simulation time 180191090800 ps
CPU time 912.81 seconds
Started Jun 27 05:12:35 PM PDT 24
Finished Jun 27 05:27:49 PM PDT 24
Peak memory 261168 kb
Host smart-88ce12fe-78eb-4adf-a302-8cccb765385b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350258635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.3350258635
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.3458382157
Short name T43
Test name
Test status
Simulation time 3936084700 ps
CPU time 123.05 seconds
Started Jun 27 05:12:37 PM PDT 24
Finished Jun 27 05:14:40 PM PDT 24
Peak memory 263056 kb
Host smart-7c82a0b4-c290-4854-9611-635a5952e432
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458382157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.3458382157
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.104719361
Short name T480
Test name
Test status
Simulation time 1287578300 ps
CPU time 136.64 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:15:12 PM PDT 24
Peak memory 291744 kb
Host smart-4cdec55e-e6bd-41b2-9c18-463da6996a13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104719361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.104719361
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.415921852
Short name T67
Test name
Test status
Simulation time 28330876800 ps
CPU time 148.05 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:15:22 PM PDT 24
Peak memory 293152 kb
Host smart-d17f7519-3c10-49bc-968e-a2a19d379b9b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415921852 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.415921852
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.1389408956
Short name T1085
Test name
Test status
Simulation time 7202860800 ps
CPU time 72.22 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:14:08 PM PDT 24
Peak memory 260880 kb
Host smart-ce12278d-3519-44f8-b8af-0880a7fafd32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389408956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.1389408956
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2336295292
Short name T450
Test name
Test status
Simulation time 21809672200 ps
CPU time 194.15 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:16:10 PM PDT 24
Peak memory 265344 kb
Host smart-9456fd30-2da1-4ee1-96d9-f98415363227
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233
6295292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2336295292
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.242855078
Short name T927
Test name
Test status
Simulation time 3921257500 ps
CPU time 82.45 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:14:19 PM PDT 24
Peak memory 263004 kb
Host smart-246d83c8-63d2-48bb-b091-ba4d04de5bd3
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242855078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.242855078
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3918235298
Short name T858
Test name
Test status
Simulation time 46779000 ps
CPU time 13.36 seconds
Started Jun 27 05:12:57 PM PDT 24
Finished Jun 27 05:13:12 PM PDT 24
Peak memory 265124 kb
Host smart-cf5c4257-c068-4ca4-a847-10651a48c40e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918235298 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3918235298
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1914790715
Short name T152
Test name
Test status
Simulation time 951427500 ps
CPU time 76.46 seconds
Started Jun 27 05:12:53 PM PDT 24
Finished Jun 27 05:14:10 PM PDT 24
Peak memory 261096 kb
Host smart-7580fdd9-6013-4c74-ad30-081abe2b2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914790715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1914790715
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.768196556
Short name T490
Test name
Test status
Simulation time 8170676000 ps
CPU time 150.48 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:15:28 PM PDT 24
Peak memory 265604 kb
Host smart-38026bd7-78f9-45d5-be15-88fd0bc4cb60
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768196556 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.768196556
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.508613745
Short name T62
Test name
Test status
Simulation time 57162800 ps
CPU time 14.18 seconds
Started Jun 27 05:12:52 PM PDT 24
Finished Jun 27 05:13:07 PM PDT 24
Peak memory 275528 kb
Host smart-4a989b91-fafb-49c1-9a4b-55eecfda182a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=508613745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.508613745
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1606178591
Short name T699
Test name
Test status
Simulation time 58374300 ps
CPU time 239.07 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:16:34 PM PDT 24
Peak memory 263832 kb
Host smart-18291a82-5592-4b3c-b69b-946ed9fc731e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606178591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1606178591
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3777476011
Short name T1009
Test name
Test status
Simulation time 30979500 ps
CPU time 14.51 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:13:11 PM PDT 24
Peak memory 265924 kb
Host smart-a88b75a4-1408-4773-b2f7-0f5c1ac367da
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777476011 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3777476011
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3196694761
Short name T110
Test name
Test status
Simulation time 8947951700 ps
CPU time 205.56 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:16:22 PM PDT 24
Peak memory 265324 kb
Host smart-ce6b76db-7c1e-4169-b32b-f686d5c794d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196694761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_prog_reset.3196694761
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.2949293611
Short name T960
Test name
Test status
Simulation time 273256900 ps
CPU time 352.33 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:18:27 PM PDT 24
Peak memory 281968 kb
Host smart-27ab8e72-b942-4c6e-80a2-d4c39f4b661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949293611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2949293611
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3206611792
Short name T595
Test name
Test status
Simulation time 56202800 ps
CPU time 104.66 seconds
Started Jun 27 05:12:34 PM PDT 24
Finished Jun 27 05:14:20 PM PDT 24
Peak memory 263288 kb
Host smart-d136b91c-7e1b-4a42-8172-536a4f9cd469
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206611792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3206611792
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3642454152
Short name T618
Test name
Test status
Simulation time 238702700 ps
CPU time 32.1 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:13:30 PM PDT 24
Peak memory 275752 kb
Host smart-8d605f02-8cbb-4539-8f1b-bec0c1d2d836
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642454152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3642454152
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3849333390
Short name T36
Test name
Test status
Simulation time 151380900 ps
CPU time 26.1 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:13:22 PM PDT 24
Peak memory 265832 kb
Host smart-9938f9d5-fe16-404b-ad2b-b3a3525314c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849333390 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3849333390
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.2956399034
Short name T390
Test name
Test status
Simulation time 578624300 ps
CPU time 25.47 seconds
Started Jun 27 05:12:52 PM PDT 24
Finished Jun 27 05:13:18 PM PDT 24
Peak memory 265804 kb
Host smart-b7aa5c2e-0a51-497c-8518-810095d614c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956399034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.2956399034
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3553187223
Short name T197
Test name
Test status
Simulation time 6440013700 ps
CPU time 128.11 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:15:05 PM PDT 24
Peak memory 290404 kb
Host smart-4c79bd3f-6133-42a1-bd8f-06b3c241e54b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553187223 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.3553187223
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2514942916
Short name T615
Test name
Test status
Simulation time 1604701700 ps
CPU time 151.14 seconds
Started Jun 27 05:12:55 PM PDT 24
Finished Jun 27 05:15:27 PM PDT 24
Peak memory 284456 kb
Host smart-89684ab5-a527-4223-9e07-bc5e9861544a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2514942916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2514942916
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1094273586
Short name T37
Test name
Test status
Simulation time 2371785200 ps
CPU time 140.27 seconds
Started Jun 27 05:12:58 PM PDT 24
Finished Jun 27 05:15:19 PM PDT 24
Peak memory 282248 kb
Host smart-c5f0e744-5cc3-45e2-8a55-fc4f2589ad4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094273586 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1094273586
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.148381696
Short name T802
Test name
Test status
Simulation time 29836800 ps
CPU time 31.38 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:13:27 PM PDT 24
Peak memory 273548 kb
Host smart-3942534c-e847-4b03-8bfa-231051a624e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148381696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.148381696
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3926748761
Short name T697
Test name
Test status
Simulation time 134010100 ps
CPU time 31.06 seconds
Started Jun 27 05:12:58 PM PDT 24
Finished Jun 27 05:13:30 PM PDT 24
Peak memory 276092 kb
Host smart-e1f990e2-f1a1-42c8-987f-aef3bb7ec92f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926748761 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3926748761
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.1282210523
Short name T129
Test name
Test status
Simulation time 615213700 ps
CPU time 78.28 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:14:14 PM PDT 24
Peak memory 265816 kb
Host smart-630561b3-8108-4241-9d6f-b232fc091651
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282210523 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.1282210523
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.2740233862
Short name T485
Test name
Test status
Simulation time 677965500 ps
CPU time 70.59 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:14:07 PM PDT 24
Peak memory 273620 kb
Host smart-5b9b54a6-b844-4195-9ba9-ebbd3f7435f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740233862 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.2740233862
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.1120025869
Short name T220
Test name
Test status
Simulation time 2104506000 ps
CPU time 103.32 seconds
Started Jun 27 05:12:35 PM PDT 24
Finished Jun 27 05:14:19 PM PDT 24
Peak memory 281528 kb
Host smart-b0e2cfd1-98a2-43b9-a130-26b400482adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120025869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1120025869
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3069567242
Short name T563
Test name
Test status
Simulation time 13970400 ps
CPU time 26.82 seconds
Started Jun 27 05:12:36 PM PDT 24
Finished Jun 27 05:13:04 PM PDT 24
Peak memory 259932 kb
Host smart-d75a5ec5-7ef0-4475-a72d-5eb32a4bdc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069567242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3069567242
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2773194664
Short name T520
Test name
Test status
Simulation time 25826800 ps
CPU time 27.16 seconds
Started Jun 27 05:12:33 PM PDT 24
Finished Jun 27 05:13:01 PM PDT 24
Peak memory 262716 kb
Host smart-ae1d8e25-b5ba-49aa-bc99-87f5707b7406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773194664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2773194664
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.3734041353
Short name T1066
Test name
Test status
Simulation time 5309061400 ps
CPU time 219.57 seconds
Started Jun 27 05:12:52 PM PDT 24
Finished Jun 27 05:16:32 PM PDT 24
Peak memory 265552 kb
Host smart-b028159c-2075-4a3b-bc0e-86a00e02d70d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734041353 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.3734041353
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.3199069539
Short name T579
Test name
Test status
Simulation time 38429100 ps
CPU time 13.79 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:21:10 PM PDT 24
Peak memory 265496 kb
Host smart-e2fe855e-037e-4066-8a11-14f736d6dfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199069539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
3199069539
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2725853029
Short name T710
Test name
Test status
Simulation time 47874300 ps
CPU time 16.43 seconds
Started Jun 27 05:20:56 PM PDT 24
Finished Jun 27 05:21:15 PM PDT 24
Peak memory 284752 kb
Host smart-53da1e8e-f567-45f5-a143-f9d4d1b7830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725853029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2725853029
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2014197514
Short name T674
Test name
Test status
Simulation time 10694400 ps
CPU time 21.76 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:21:19 PM PDT 24
Peak memory 274164 kb
Host smart-dedca703-d3c9-4d5b-a100-1b37fb11cbef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014197514 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2014197514
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1837307735
Short name T989
Test name
Test status
Simulation time 1011067300 ps
CPU time 44.27 seconds
Started Jun 27 05:20:51 PM PDT 24
Finished Jun 27 05:21:36 PM PDT 24
Peak memory 261340 kb
Host smart-94add38c-e579-4e8b-a421-a8afe0282856
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837307735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1837307735
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2307087567
Short name T342
Test name
Test status
Simulation time 6524486800 ps
CPU time 282.28 seconds
Started Jun 27 05:20:51 PM PDT 24
Finished Jun 27 05:25:34 PM PDT 24
Peak memory 285208 kb
Host smart-d9c46008-cb3e-4a89-8aa1-7ab04527922b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307087567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2307087567
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3668636410
Short name T617
Test name
Test status
Simulation time 12651117000 ps
CPU time 336.02 seconds
Started Jun 27 05:20:57 PM PDT 24
Finished Jun 27 05:26:35 PM PDT 24
Peak memory 285084 kb
Host smart-18208c28-bac6-468a-bfc5-3b221135c1f2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668636410 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3668636410
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1335074368
Short name T950
Test name
Test status
Simulation time 38817000 ps
CPU time 131.36 seconds
Started Jun 27 05:20:53 PM PDT 24
Finished Jun 27 05:23:06 PM PDT 24
Peak memory 262732 kb
Host smart-ed1f6950-aac1-453e-88a7-0268c3fcdf1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335074368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1335074368
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.1785119027
Short name T364
Test name
Test status
Simulation time 45414300 ps
CPU time 30.52 seconds
Started Jun 27 05:20:54 PM PDT 24
Finished Jun 27 05:21:27 PM PDT 24
Peak memory 275856 kb
Host smart-5af4e9dd-5975-4616-9e1a-483fb8b41365
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785119027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.1785119027
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2623521242
Short name T684
Test name
Test status
Simulation time 29007300 ps
CPU time 30.66 seconds
Started Jun 27 05:20:52 PM PDT 24
Finished Jun 27 05:21:24 PM PDT 24
Peak memory 275940 kb
Host smart-d7267d7b-1f1d-4261-83a9-46f87eb58b0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623521242 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2623521242
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.813301397
Short name T441
Test name
Test status
Simulation time 1014450100 ps
CPU time 61.05 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:21:58 PM PDT 24
Peak memory 264676 kb
Host smart-e7e850d2-b3fc-4fd1-b704-6550d7a7fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813301397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.813301397
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.3258367798
Short name T725
Test name
Test status
Simulation time 25374000 ps
CPU time 123.28 seconds
Started Jun 27 05:20:56 PM PDT 24
Finished Jun 27 05:23:02 PM PDT 24
Peak memory 277512 kb
Host smart-0cbf4c80-82d4-4f81-93e4-308a7e797815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258367798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3258367798
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.3353549285
Short name T416
Test name
Test status
Simulation time 23384000 ps
CPU time 13.66 seconds
Started Jun 27 05:20:54 PM PDT 24
Finished Jun 27 05:21:09 PM PDT 24
Peak memory 258604 kb
Host smart-28f4ed39-198a-46b0-8222-872f56eb09fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353549285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
3353549285
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.1637472610
Short name T108
Test name
Test status
Simulation time 68643800 ps
CPU time 15.85 seconds
Started Jun 27 05:20:54 PM PDT 24
Finished Jun 27 05:21:11 PM PDT 24
Peak memory 275304 kb
Host smart-a290c1b7-ec50-428e-bad6-07bdaa647103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637472610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1637472610
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.4255743139
Short name T316
Test name
Test status
Simulation time 38108500 ps
CPU time 22.3 seconds
Started Jun 27 05:20:53 PM PDT 24
Finished Jun 27 05:21:17 PM PDT 24
Peak memory 273856 kb
Host smart-6ca879c1-6165-4174-a93d-25ddacf4e84d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255743139 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.4255743139
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3329684951
Short name T709
Test name
Test status
Simulation time 3053149100 ps
CPU time 168.54 seconds
Started Jun 27 05:20:58 PM PDT 24
Finished Jun 27 05:23:48 PM PDT 24
Peak memory 263652 kb
Host smart-3d0bb0c9-ae68-4f89-ab47-4d4e877cbf9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329684951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3329684951
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2984036281
Short name T715
Test name
Test status
Simulation time 53927282100 ps
CPU time 421.86 seconds
Started Jun 27 05:20:57 PM PDT 24
Finished Jun 27 05:28:01 PM PDT 24
Peak memory 291796 kb
Host smart-a21e0a0e-2465-48a6-97f0-306c469db94c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984036281 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2984036281
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.2427463919
Short name T991
Test name
Test status
Simulation time 134750900 ps
CPU time 132.53 seconds
Started Jun 27 05:20:56 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 260648 kb
Host smart-11d2003d-bf9c-4293-8939-edbd1aa63276
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427463919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.2427463919
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.559983995
Short name T184
Test name
Test status
Simulation time 181412200 ps
CPU time 31.54 seconds
Started Jun 27 05:20:56 PM PDT 24
Finished Jun 27 05:21:30 PM PDT 24
Peak memory 275832 kb
Host smart-46772472-6fdf-40d2-9757-778e57be9d25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559983995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.559983995
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2469247866
Short name T680
Test name
Test status
Simulation time 65359100 ps
CPU time 28.81 seconds
Started Jun 27 05:20:56 PM PDT 24
Finished Jun 27 05:21:27 PM PDT 24
Peak memory 275876 kb
Host smart-5dfc295e-2144-44d2-a34c-c9d26af88590
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469247866 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2469247866
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.4038110563
Short name T943
Test name
Test status
Simulation time 8060046900 ps
CPU time 74.62 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:22:12 PM PDT 24
Peak memory 264148 kb
Host smart-a5114191-ee9a-4228-90d2-d4fb5f6b8a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038110563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.4038110563
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.2464589766
Short name T40
Test name
Test status
Simulation time 30360000 ps
CPU time 194.27 seconds
Started Jun 27 05:20:54 PM PDT 24
Finished Jun 27 05:24:10 PM PDT 24
Peak memory 277760 kb
Host smart-06e14902-78cf-41f8-a7c5-0ebae4bce00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464589766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2464589766
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3950626048
Short name T430
Test name
Test status
Simulation time 87179900 ps
CPU time 13.93 seconds
Started Jun 27 05:21:10 PM PDT 24
Finished Jun 27 05:21:26 PM PDT 24
Peak memory 258640 kb
Host smart-72b6486a-e88c-4a4d-95bb-a236a844cb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950626048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3950626048
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2555647809
Short name T784
Test name
Test status
Simulation time 28026400 ps
CPU time 15.85 seconds
Started Jun 27 05:21:07 PM PDT 24
Finished Jun 27 05:21:24 PM PDT 24
Peak memory 275328 kb
Host smart-bb80c6ee-f679-4a26-8cca-b749c169bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555647809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2555647809
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1884438780
Short name T396
Test name
Test status
Simulation time 27459300 ps
CPU time 21.8 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:21:31 PM PDT 24
Peak memory 265572 kb
Host smart-ba26e1e5-cf28-4204-9560-450eaf2ab426
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884438780 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1884438780
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3924403134
Short name T481
Test name
Test status
Simulation time 1281067300 ps
CPU time 50.36 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:22:01 PM PDT 24
Peak memory 263728 kb
Host smart-44b1778a-f488-49d6-ac9d-59644e5aea3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924403134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3924403134
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1219321903
Short name T347
Test name
Test status
Simulation time 3545084800 ps
CPU time 221.93 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:24:53 PM PDT 24
Peak memory 291676 kb
Host smart-2d9dc2dd-c1c4-4703-b733-bfcf60eda89b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219321903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.1219321903
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2519374879
Short name T739
Test name
Test status
Simulation time 11642632100 ps
CPU time 118.96 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:23:10 PM PDT 24
Peak memory 293004 kb
Host smart-adaa4283-4e7b-4faf-9697-9e186a0c3f25
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519374879 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2519374879
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.2733046090
Short name T166
Test name
Test status
Simulation time 39922700 ps
CPU time 112.12 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:23:01 PM PDT 24
Peak memory 265644 kb
Host smart-dd4d74d2-73b1-46fa-9c89-2321f3a376a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733046090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.2733046090
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.773738124
Short name T1105
Test name
Test status
Simulation time 27031800 ps
CPU time 31.49 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:21:42 PM PDT 24
Peak memory 275900 kb
Host smart-1c02f360-0a0c-4c00-8c5a-bf6c8c958164
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773738124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_rw_evict.773738124
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.2264686132
Short name T862
Test name
Test status
Simulation time 31087900 ps
CPU time 31.17 seconds
Started Jun 27 05:21:11 PM PDT 24
Finished Jun 27 05:21:44 PM PDT 24
Peak memory 275880 kb
Host smart-f33f720c-7c96-4bb1-be1f-cafed3bd45aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264686132 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.2264686132
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.58013682
Short name T577
Test name
Test status
Simulation time 2517067400 ps
CPU time 61.98 seconds
Started Jun 27 05:21:10 PM PDT 24
Finished Jun 27 05:22:14 PM PDT 24
Peak memory 263612 kb
Host smart-315de2c8-7e5f-4537-92af-35d0b18023e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58013682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.58013682
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.609234728
Short name T1044
Test name
Test status
Simulation time 25525300 ps
CPU time 76.25 seconds
Started Jun 27 05:20:55 PM PDT 24
Finished Jun 27 05:22:13 PM PDT 24
Peak memory 276880 kb
Host smart-caa2eb47-4e8d-4aab-be6f-5cfe478c4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609234728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.609234728
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.3519622224
Short name T556
Test name
Test status
Simulation time 505867700 ps
CPU time 14.3 seconds
Started Jun 27 05:21:12 PM PDT 24
Finished Jun 27 05:21:27 PM PDT 24
Peak memory 265528 kb
Host smart-e9c6c059-c2a3-4c9c-9a81-c4f0d87b44d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519622224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
3519622224
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.725629085
Short name T473
Test name
Test status
Simulation time 21957200 ps
CPU time 16.43 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:21:27 PM PDT 24
Peak memory 284784 kb
Host smart-37f75593-4594-43e0-8e6e-77a6abc3de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725629085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.725629085
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.878645855
Short name T741
Test name
Test status
Simulation time 29360200 ps
CPU time 21.97 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:21:31 PM PDT 24
Peak memory 273848 kb
Host smart-e6575c4e-c252-4023-b4e6-80af58de6dd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878645855 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.878645855
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1498369411
Short name T1081
Test name
Test status
Simulation time 5405263100 ps
CPU time 212.19 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:24:42 PM PDT 24
Peak memory 263280 kb
Host smart-4e691d47-f282-40f6-a2bb-72f3e69cf424
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498369411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1498369411
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2489903543
Short name T934
Test name
Test status
Simulation time 524273400 ps
CPU time 126.16 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:23:16 PM PDT 24
Peak memory 293672 kb
Host smart-7f46b738-64d8-4380-a253-5a47db7bfc97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489903543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2489903543
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1778264986
Short name T1101
Test name
Test status
Simulation time 39553342800 ps
CPU time 241.71 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:25:12 PM PDT 24
Peak memory 291764 kb
Host smart-e6838592-c445-4121-b50d-e2ed4bb6bd3e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778264986 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.1778264986
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1959267165
Short name T965
Test name
Test status
Simulation time 281002900 ps
CPU time 112.95 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:23:04 PM PDT 24
Peak memory 265600 kb
Host smart-b09ec87c-1a99-44e6-9b76-6b50b43cdc8d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959267165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1959267165
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.4147540074
Short name T780
Test name
Test status
Simulation time 151862400 ps
CPU time 31.5 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:21:42 PM PDT 24
Peak memory 276096 kb
Host smart-f40b1e57-b42f-4e00-8816-92c5a3427af5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147540074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.4147540074
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.1903181259
Short name T729
Test name
Test status
Simulation time 64375500 ps
CPU time 30.38 seconds
Started Jun 27 05:21:11 PM PDT 24
Finished Jun 27 05:21:43 PM PDT 24
Peak memory 275816 kb
Host smart-1836193a-3132-4bcd-adae-6389c3831140
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903181259 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.1903181259
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1873308992
Short name T525
Test name
Test status
Simulation time 5246847500 ps
CPU time 64.47 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:22:16 PM PDT 24
Peak memory 265272 kb
Host smart-b782e555-7e8d-4826-b150-c745607db9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873308992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1873308992
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.104689159
Short name T911
Test name
Test status
Simulation time 25830300 ps
CPU time 123.29 seconds
Started Jun 27 05:21:07 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 278352 kb
Host smart-ac77e625-7b49-4097-8727-71db12d307df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104689159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.104689159
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2152597820
Short name T93
Test name
Test status
Simulation time 58755600 ps
CPU time 13.68 seconds
Started Jun 27 05:21:27 PM PDT 24
Finished Jun 27 05:21:42 PM PDT 24
Peak memory 258808 kb
Host smart-095ad187-3499-4c55-b64d-169422797358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152597820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2152597820
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3901154964
Short name T805
Test name
Test status
Simulation time 52562000 ps
CPU time 16 seconds
Started Jun 27 05:21:27 PM PDT 24
Finished Jun 27 05:21:44 PM PDT 24
Peak memory 275324 kb
Host smart-494f0634-fb14-4418-8e94-e9f1e263d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901154964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3901154964
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1644402716
Short name T526
Test name
Test status
Simulation time 7798193800 ps
CPU time 153.01 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 263656 kb
Host smart-c5192e0b-218c-4b72-8bae-bffe38794629
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644402716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1644402716
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.861892282
Short name T263
Test name
Test status
Simulation time 736181500 ps
CPU time 138.6 seconds
Started Jun 27 05:21:12 PM PDT 24
Finished Jun 27 05:23:32 PM PDT 24
Peak memory 294684 kb
Host smart-8064c2b6-1036-43cd-810a-bf505ad55034
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861892282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.861892282
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.4146721954
Short name T308
Test name
Test status
Simulation time 5976633700 ps
CPU time 128.69 seconds
Started Jun 27 05:21:09 PM PDT 24
Finished Jun 27 05:23:19 PM PDT 24
Peak memory 294372 kb
Host smart-36f45d43-ea0c-4ae5-b95d-7a29ce7764eb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146721954 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.4146721954
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.1338626833
Short name T588
Test name
Test status
Simulation time 84766600 ps
CPU time 133.05 seconds
Started Jun 27 05:21:11 PM PDT 24
Finished Jun 27 05:23:26 PM PDT 24
Peak memory 260448 kb
Host smart-d57c0bc4-a583-4490-a5d8-06248e871040
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338626833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.1338626833
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1866218861
Short name T910
Test name
Test status
Simulation time 80912700 ps
CPU time 31.74 seconds
Started Jun 27 05:21:27 PM PDT 24
Finished Jun 27 05:22:00 PM PDT 24
Peak memory 276180 kb
Host smart-5793e90c-a218-4bcd-a5f8-28b567e2e6f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866218861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1866218861
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2118679080
Short name T1061
Test name
Test status
Simulation time 46340000 ps
CPU time 27.91 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:21:58 PM PDT 24
Peak memory 275908 kb
Host smart-4a352594-d1b9-4f81-a0e5-beb202ab9be2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118679080 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2118679080
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.4070088871
Short name T401
Test name
Test status
Simulation time 541522300 ps
CPU time 66.52 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:22:36 PM PDT 24
Peak memory 265248 kb
Host smart-7b3689ba-6019-4d32-9790-2cc37dc454e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070088871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.4070088871
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.609923687
Short name T944
Test name
Test status
Simulation time 20145200 ps
CPU time 72.76 seconds
Started Jun 27 05:21:08 PM PDT 24
Finished Jun 27 05:22:21 PM PDT 24
Peak memory 275856 kb
Host smart-a0c5cbfe-0efa-4ae8-ae6b-5737fd67e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609923687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.609923687
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.1423020729
Short name T864
Test name
Test status
Simulation time 418439100 ps
CPU time 14.09 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:21:44 PM PDT 24
Peak memory 265460 kb
Host smart-dd7edf3b-dd8f-4453-89a3-347c5331f3f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423020729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
1423020729
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.3744310945
Short name T700
Test name
Test status
Simulation time 17323400 ps
CPU time 16.34 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:21:46 PM PDT 24
Peak memory 275276 kb
Host smart-fa7f737c-8ba2-483f-bc1d-ebbb71ba4caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744310945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3744310945
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2081839619
Short name T56
Test name
Test status
Simulation time 22111700 ps
CPU time 21.17 seconds
Started Jun 27 05:21:29 PM PDT 24
Finished Jun 27 05:21:51 PM PDT 24
Peak memory 265284 kb
Host smart-6400685a-f784-495d-b1b0-392e0ae92034
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081839619 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2081839619
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3390904770
Short name T601
Test name
Test status
Simulation time 17559335800 ps
CPU time 150.53 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:24:00 PM PDT 24
Peak memory 261264 kb
Host smart-b3e31652-1948-472a-9ab9-242b8f5f2d49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390904770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3390904770
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.570816776
Short name T35
Test name
Test status
Simulation time 781547500 ps
CPU time 132.89 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:23:42 PM PDT 24
Peak memory 293376 kb
Host smart-7b0393e2-cfb9-44df-9e06-80a0f9881b0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570816776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.570816776
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1389550993
Short name T474
Test name
Test status
Simulation time 23078748100 ps
CPU time 293.55 seconds
Started Jun 27 05:21:29 PM PDT 24
Finished Jun 27 05:26:25 PM PDT 24
Peak memory 285036 kb
Host smart-d5779973-b736-40b2-afa1-ebd7f8d45f27
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389550993 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1389550993
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.1661746298
Short name T555
Test name
Test status
Simulation time 70132600 ps
CPU time 111.57 seconds
Started Jun 27 05:21:27 PM PDT 24
Finished Jun 27 05:23:20 PM PDT 24
Peak memory 261548 kb
Host smart-3d778663-c63e-4fd1-8e14-8d4b5570365a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661746298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.1661746298
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.4092575337
Short name T130
Test name
Test status
Simulation time 32093500 ps
CPU time 31.21 seconds
Started Jun 27 05:21:29 PM PDT 24
Finished Jun 27 05:22:02 PM PDT 24
Peak memory 275872 kb
Host smart-6eedc360-819a-44a5-9865-7dfe3261e977
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092575337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.4092575337
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.704468561
Short name T368
Test name
Test status
Simulation time 68454700 ps
CPU time 30.65 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:22:00 PM PDT 24
Peak memory 277068 kb
Host smart-f46b517e-3c10-411b-8978-7ef934404ee5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704468561 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.704468561
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.4018353882
Short name T487
Test name
Test status
Simulation time 520623200 ps
CPU time 61.07 seconds
Started Jun 27 05:21:29 PM PDT 24
Finished Jun 27 05:22:31 PM PDT 24
Peak memory 263676 kb
Host smart-eb7c344f-68e9-45cf-b59a-660c8c189ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018353882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.4018353882
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3678859845
Short name T743
Test name
Test status
Simulation time 245250300 ps
CPU time 97.3 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:23:07 PM PDT 24
Peak memory 276324 kb
Host smart-1ef0a115-a688-46d2-811d-296e14f69ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678859845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3678859845
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3667696402
Short name T883
Test name
Test status
Simulation time 90925200 ps
CPU time 13.64 seconds
Started Jun 27 05:21:44 PM PDT 24
Finished Jun 27 05:21:59 PM PDT 24
Peak memory 258716 kb
Host smart-c50424ea-6b4e-4f73-9086-8400f1abec27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667696402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3667696402
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3267650969
Short name T634
Test name
Test status
Simulation time 21823000 ps
CPU time 16.39 seconds
Started Jun 27 05:21:44 PM PDT 24
Finished Jun 27 05:22:02 PM PDT 24
Peak memory 275328 kb
Host smart-070130ed-c211-4435-b2d6-c8205cccd8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267650969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3267650969
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.2527417511
Short name T881
Test name
Test status
Simulation time 29568900 ps
CPU time 21.96 seconds
Started Jun 27 05:21:33 PM PDT 24
Finished Jun 27 05:21:56 PM PDT 24
Peak memory 265224 kb
Host smart-b2f20157-26e5-42ed-ae04-c39cf4f8a67d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527417511 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.2527417511
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.434725175
Short name T471
Test name
Test status
Simulation time 9167912600 ps
CPU time 87.15 seconds
Started Jun 27 05:21:30 PM PDT 24
Finished Jun 27 05:22:58 PM PDT 24
Peak memory 261384 kb
Host smart-35fcded5-44c8-4c30-bacd-13ec5b687b8a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434725175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_h
w_sec_otp.434725175
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.951567068
Short name T581
Test name
Test status
Simulation time 3332297200 ps
CPU time 195.38 seconds
Started Jun 27 05:21:32 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 291616 kb
Host smart-b027faf6-4c36-4fac-a1bd-32089402a2e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951567068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas
h_ctrl_intr_rd.951567068
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2825526982
Short name T995
Test name
Test status
Simulation time 20554877500 ps
CPU time 130.08 seconds
Started Jun 27 05:21:33 PM PDT 24
Finished Jun 27 05:23:44 PM PDT 24
Peak memory 295468 kb
Host smart-eb47977d-801a-4d74-887f-c0736a8c0c13
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825526982 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2825526982
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2150134017
Short name T657
Test name
Test status
Simulation time 38693200 ps
CPU time 131.96 seconds
Started Jun 27 05:21:33 PM PDT 24
Finished Jun 27 05:23:46 PM PDT 24
Peak memory 261400 kb
Host smart-d0c704a8-5d13-4cf6-b3a9-629075d9da2c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150134017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2150134017
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.4081398022
Short name T1076
Test name
Test status
Simulation time 31577000 ps
CPU time 31.66 seconds
Started Jun 27 05:21:30 PM PDT 24
Finished Jun 27 05:22:03 PM PDT 24
Peak memory 275780 kb
Host smart-c6da5493-4eca-4c6b-930a-798f61b55106
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081398022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.4081398022
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.1055103086
Short name T452
Test name
Test status
Simulation time 31571900 ps
CPU time 31.2 seconds
Started Jun 27 05:21:29 PM PDT 24
Finished Jun 27 05:22:02 PM PDT 24
Peak memory 275904 kb
Host smart-c1c3e5cf-240e-43ff-b17a-474aaaf95ec4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055103086 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.1055103086
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1425003616
Short name T982
Test name
Test status
Simulation time 7029427000 ps
CPU time 89.44 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:14 PM PDT 24
Peak memory 263660 kb
Host smart-bf4980ee-d742-43ca-8947-a807c72513e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425003616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1425003616
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.474372770
Short name T1004
Test name
Test status
Simulation time 152185900 ps
CPU time 121.78 seconds
Started Jun 27 05:21:28 PM PDT 24
Finished Jun 27 05:23:31 PM PDT 24
Peak memory 277132 kb
Host smart-4774838b-f2b1-49c2-abf8-3a6776fd97c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474372770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.474372770
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2628945457
Short name T94
Test name
Test status
Simulation time 31672600 ps
CPU time 13.76 seconds
Started Jun 27 05:21:46 PM PDT 24
Finished Jun 27 05:22:02 PM PDT 24
Peak memory 258596 kb
Host smart-a16d23c3-2717-4e14-a185-1b617795c77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628945457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2628945457
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1050789908
Short name T455
Test name
Test status
Simulation time 48400200 ps
CPU time 15.96 seconds
Started Jun 27 05:21:46 PM PDT 24
Finished Jun 27 05:22:03 PM PDT 24
Peak memory 275312 kb
Host smart-6f6a9a43-ed1b-40e5-b6d3-8b83c7c65ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050789908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1050789908
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.3380174973
Short name T688
Test name
Test status
Simulation time 16650000 ps
CPU time 21.98 seconds
Started Jun 27 05:21:44 PM PDT 24
Finished Jun 27 05:22:07 PM PDT 24
Peak memory 265756 kb
Host smart-db8e03ca-c0dc-4190-b5a4-ea697f19b118
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380174973 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.3380174973
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.2194025449
Short name T310
Test name
Test status
Simulation time 6623179100 ps
CPU time 92.87 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:17 PM PDT 24
Peak memory 262544 kb
Host smart-166ef0b6-fc51-45af-92b1-125bc34319f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194025449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.2194025449
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.3548140045
Short name T1057
Test name
Test status
Simulation time 1552283700 ps
CPU time 157.72 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:24:23 PM PDT 24
Peak memory 294476 kb
Host smart-2d33f82a-59d2-4654-90e5-12b3601178b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548140045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.3548140045
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1181477500
Short name T339
Test name
Test status
Simulation time 47848388500 ps
CPU time 318.23 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:27:03 PM PDT 24
Peak memory 291296 kb
Host smart-6027d494-e94a-4a22-b45b-447b842076a6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181477500 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1181477500
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2839748458
Short name T460
Test name
Test status
Simulation time 253145500 ps
CPU time 131.75 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:56 PM PDT 24
Peak memory 260308 kb
Host smart-80abc71f-0461-4dca-8471-bba87af31bbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839748458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2839748458
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.581420130
Short name T465
Test name
Test status
Simulation time 84773300 ps
CPU time 30.72 seconds
Started Jun 27 05:21:45 PM PDT 24
Finished Jun 27 05:22:17 PM PDT 24
Peak memory 277052 kb
Host smart-39be36ed-2f6f-4a0f-80fb-cebbc1c07758
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581420130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_rw_evict.581420130
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.532846825
Short name T621
Test name
Test status
Simulation time 28047800 ps
CPU time 30.57 seconds
Started Jun 27 05:21:46 PM PDT 24
Finished Jun 27 05:22:18 PM PDT 24
Peak memory 275776 kb
Host smart-239d05e3-a2cf-43ce-9785-fa75f181f63a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532846825 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.532846825
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1780289192
Short name T816
Test name
Test status
Simulation time 492498500 ps
CPU time 61.38 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:22:46 PM PDT 24
Peak memory 263644 kb
Host smart-473764e2-949f-489d-be31-0b507ca5604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780289192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1780289192
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.1799139668
Short name T904
Test name
Test status
Simulation time 28798500 ps
CPU time 122.86 seconds
Started Jun 27 05:21:46 PM PDT 24
Finished Jun 27 05:23:51 PM PDT 24
Peak memory 276508 kb
Host smart-f89f43b7-dd90-495b-8ad0-d43b4dee5253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799139668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1799139668
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2167783740
Short name T445
Test name
Test status
Simulation time 28733100 ps
CPU time 13.64 seconds
Started Jun 27 05:21:42 PM PDT 24
Finished Jun 27 05:21:58 PM PDT 24
Peak memory 258528 kb
Host smart-f540959b-dd5b-43d3-aaa4-6bef526cadf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167783740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2167783740
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.4249165385
Short name T568
Test name
Test status
Simulation time 73198400 ps
CPU time 13.55 seconds
Started Jun 27 05:21:46 PM PDT 24
Finished Jun 27 05:22:01 PM PDT 24
Peak memory 275196 kb
Host smart-9d0da2d6-4783-40d2-becd-e4f7ab55c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249165385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.4249165385
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.805724247
Short name T385
Test name
Test status
Simulation time 16900200 ps
CPU time 22.55 seconds
Started Jun 27 05:21:44 PM PDT 24
Finished Jun 27 05:22:08 PM PDT 24
Peak memory 274028 kb
Host smart-725f3dba-6443-4501-bda5-e2d6d6cdd6e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805724247 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.805724247
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3294066549
Short name T322
Test name
Test status
Simulation time 2925051200 ps
CPU time 91.39 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:16 PM PDT 24
Peak memory 263688 kb
Host smart-ac0dd047-b2d0-4f1a-a0de-fb017bcbddbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294066549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.3294066549
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.3036221932
Short name T346
Test name
Test status
Simulation time 707746300 ps
CPU time 157.62 seconds
Started Jun 27 05:21:45 PM PDT 24
Finished Jun 27 05:24:25 PM PDT 24
Peak memory 294592 kb
Host smart-5a2eed54-1a09-4269-b9b3-02ded110cc00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036221932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.3036221932
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3187697063
Short name T554
Test name
Test status
Simulation time 31572870700 ps
CPU time 149.1 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:24:14 PM PDT 24
Peak memory 293332 kb
Host smart-215b1452-aed5-4260-8047-54e2b94b81d7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187697063 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.3187697063
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1077585305
Short name T395
Test name
Test status
Simulation time 152780500 ps
CPU time 110.79 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:36 PM PDT 24
Peak memory 261516 kb
Host smart-b441e231-7f92-4d2f-992a-6d0d8417703b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077585305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1077585305
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.669292018
Short name T929
Test name
Test status
Simulation time 27980900 ps
CPU time 31.48 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:22:16 PM PDT 24
Peak memory 274288 kb
Host smart-3c720f08-d696-4df1-900b-0414d99444a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669292018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_rw_evict.669292018
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1123859002
Short name T730
Test name
Test status
Simulation time 31753900 ps
CPU time 31.33 seconds
Started Jun 27 05:21:44 PM PDT 24
Finished Jun 27 05:22:17 PM PDT 24
Peak memory 275784 kb
Host smart-ff2c8f41-b1c8-4b68-8134-45bfb67aec87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123859002 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1123859002
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1776802325
Short name T406
Test name
Test status
Simulation time 10029931300 ps
CPU time 72.7 seconds
Started Jun 27 05:21:45 PM PDT 24
Finished Jun 27 05:22:59 PM PDT 24
Peak memory 264308 kb
Host smart-b1ffee10-cba2-4712-b867-2c71cf223a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776802325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1776802325
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.4021825581
Short name T758
Test name
Test status
Simulation time 64577900 ps
CPU time 124.04 seconds
Started Jun 27 05:21:43 PM PDT 24
Finished Jun 27 05:23:49 PM PDT 24
Peak memory 276492 kb
Host smart-c55035e6-bcb5-4bb3-9708-e920075d5b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021825581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.4021825581
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.1938684177
Short name T607
Test name
Test status
Simulation time 63097900 ps
CPU time 14.3 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:18 PM PDT 24
Peak memory 258468 kb
Host smart-40cfd994-77eb-4739-a264-18203bf43f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938684177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
1938684177
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3720280574
Short name T1023
Test name
Test status
Simulation time 15064700 ps
CPU time 16.63 seconds
Started Jun 27 05:22:03 PM PDT 24
Finished Jun 27 05:22:21 PM PDT 24
Peak memory 284828 kb
Host smart-cae63964-1fbd-4489-9e29-aae684abcec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720280574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3720280574
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3148737123
Short name T317
Test name
Test status
Simulation time 4217496100 ps
CPU time 80.97 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:23:24 PM PDT 24
Peak memory 261052 kb
Host smart-41960743-6618-4ee0-a350-f775475de810
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148737123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3148737123
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.3991888081
Short name T216
Test name
Test status
Simulation time 1117695900 ps
CPU time 155 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:24:38 PM PDT 24
Peak memory 293244 kb
Host smart-5ece779c-1cb9-4812-a530-2e545aeddfa9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991888081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.3991888081
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1077599522
Short name T341
Test name
Test status
Simulation time 8442044100 ps
CPU time 228.58 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:25:52 PM PDT 24
Peak memory 292084 kb
Host smart-fe99d8b0-4462-498c-a6dd-8e77f79c65d3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077599522 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1077599522
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.2889366676
Short name T866
Test name
Test status
Simulation time 41783100 ps
CPU time 132.55 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 260544 kb
Host smart-6f89bb58-f899-4346-8477-90ec1bbdd488
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889366676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.2889366676
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.4099882399
Short name T363
Test name
Test status
Simulation time 72357100 ps
CPU time 31.82 seconds
Started Jun 27 05:21:59 PM PDT 24
Finished Jun 27 05:22:33 PM PDT 24
Peak memory 270124 kb
Host smart-eeb4cdf0-96a4-4e35-9b2a-cc522fa1e527
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099882399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.4099882399
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.4130650312
Short name T920
Test name
Test status
Simulation time 28659100 ps
CPU time 30.89 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:34 PM PDT 24
Peak memory 274068 kb
Host smart-60d5dd28-52bb-4376-ac87-15511639a3a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130650312 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.4130650312
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.3570075558
Short name T413
Test name
Test status
Simulation time 7003420500 ps
CPU time 70.61 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:23:13 PM PDT 24
Peak memory 264160 kb
Host smart-e4b1d7f8-9d4c-4b74-906f-bc9d0c1bde82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570075558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3570075558
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1113932267
Short name T5
Test name
Test status
Simulation time 119893900 ps
CPU time 145.53 seconds
Started Jun 27 05:21:47 PM PDT 24
Finished Jun 27 05:24:13 PM PDT 24
Peak memory 277172 kb
Host smart-c5dd9546-bf98-433e-ae7a-e850a20d02b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113932267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1113932267
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3459190640
Short name T596
Test name
Test status
Simulation time 18188300 ps
CPU time 13.68 seconds
Started Jun 27 05:13:51 PM PDT 24
Finished Jun 27 05:14:05 PM PDT 24
Peak memory 265512 kb
Host smart-3ff84556-ffd1-46fc-8c00-f0765ed0174b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459190640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
459190640
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.339718836
Short name T979
Test name
Test status
Simulation time 38416200 ps
CPU time 14.25 seconds
Started Jun 27 05:13:49 PM PDT 24
Finished Jun 27 05:14:04 PM PDT 24
Peak memory 261832 kb
Host smart-1b7b0ffc-05e2-48b6-aa9e-fed61ec9d218
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339718836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.339718836
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1677340019
Short name T537
Test name
Test status
Simulation time 110689800 ps
CPU time 16.08 seconds
Started Jun 27 05:13:51 PM PDT 24
Finished Jun 27 05:14:07 PM PDT 24
Peak memory 275388 kb
Host smart-2ca703b5-7cf5-4ee3-b9c0-173a1f531b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677340019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1677340019
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1009322640
Short name T158
Test name
Test status
Simulation time 116353300 ps
CPU time 104.94 seconds
Started Jun 27 05:13:33 PM PDT 24
Finished Jun 27 05:15:19 PM PDT 24
Peak memory 282192 kb
Host smart-fae89771-1765-4fb3-bacf-dab2237094a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009322640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1009322640
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1083642553
Short name T665
Test name
Test status
Simulation time 37349900 ps
CPU time 22.31 seconds
Started Jun 27 05:13:30 PM PDT 24
Finished Jun 27 05:13:53 PM PDT 24
Peak memory 273796 kb
Host smart-88d3d250-cf99-49af-9fcf-5196924267a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083642553 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1083642553
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3153577351
Short name T895
Test name
Test status
Simulation time 11225469100 ps
CPU time 469.43 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:21:03 PM PDT 24
Peak memory 263796 kb
Host smart-0a786f33-0641-4609-930a-8362fad74449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3153577351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3153577351
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.667954510
Short name T502
Test name
Test status
Simulation time 14786479900 ps
CPU time 2403.99 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:53:17 PM PDT 24
Peak memory 263128 kb
Host smart-ebceb83a-8cc5-4a31-bc9f-e01842eae763
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=667954510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.667954510
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.875863820
Short name T653
Test name
Test status
Simulation time 971609800 ps
CPU time 1720.26 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:41:52 PM PDT 24
Peak memory 265432 kb
Host smart-f4e7c979-748e-40b9-9301-210b51762497
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875863820 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.875863820
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.1329169423
Short name T947
Test name
Test status
Simulation time 1913005300 ps
CPU time 756.1 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:25:49 PM PDT 24
Peak memory 273712 kb
Host smart-862f38db-336c-4ca9-bddc-94d8d1032cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329169423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1329169423
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1584221755
Short name T47
Test name
Test status
Simulation time 766126100 ps
CPU time 29.49 seconds
Started Jun 27 05:13:13 PM PDT 24
Finished Jun 27 05:13:43 PM PDT 24
Peak memory 262820 kb
Host smart-9c1b269b-c646-468b-9013-4989a9db29e8
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584221755 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_fetch_code.1584221755
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.690340118
Short name T868
Test name
Test status
Simulation time 344704500 ps
CPU time 40.54 seconds
Started Jun 27 05:13:53 PM PDT 24
Finished Jun 27 05:14:34 PM PDT 24
Peak memory 263304 kb
Host smart-9e886801-1360-451a-9fac-ade129015761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690340118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_fs_sup.690340118
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1418592792
Short name T737
Test name
Test status
Simulation time 244133714800 ps
CPU time 2933.13 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 06:02:07 PM PDT 24
Peak memory 265632 kb
Host smart-9e7f0ba3-7cc1-49a2-9f6a-81686f1da731
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418592792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1418592792
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.532500824
Short name T104
Test name
Test status
Simulation time 243874353500 ps
CPU time 2515.15 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:55:07 PM PDT 24
Peak memory 264464 kb
Host smart-a8f0cfb1-7170-4d3d-97c2-8c193210c6ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532500824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_host_ctrl_arb.532500824
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2519580911
Short name T637
Test name
Test status
Simulation time 103636700 ps
CPU time 78.19 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:14:31 PM PDT 24
Peak memory 265512 kb
Host smart-1260bae4-41e7-4257-86a9-866f133f0a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519580911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2519580911
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2165634197
Short name T281
Test name
Test status
Simulation time 10052988600 ps
CPU time 78.72 seconds
Started Jun 27 05:13:54 PM PDT 24
Finished Jun 27 05:15:14 PM PDT 24
Peak memory 266184 kb
Host smart-b752df15-ecc8-48d7-ab6f-e179eff014c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165634197 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2165634197
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2433329436
Short name T832
Test name
Test status
Simulation time 15242600 ps
CPU time 13.75 seconds
Started Jun 27 05:13:48 PM PDT 24
Finished Jun 27 05:14:03 PM PDT 24
Peak memory 258900 kb
Host smart-0582c399-afa0-42e6-a402-22d5281a9d5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433329436 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2433329436
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2683875646
Short name T808
Test name
Test status
Simulation time 180191198300 ps
CPU time 829.8 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:27:01 PM PDT 24
Peak memory 261540 kb
Host smart-91a727c4-8696-4afd-8a7e-3ebd4aa446c6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683875646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2683875646
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3913879326
Short name T320
Test name
Test status
Simulation time 4939175500 ps
CPU time 62.1 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:14:15 PM PDT 24
Peak memory 263268 kb
Host smart-eeab245f-dc20-4b16-88bc-24baed6cfada
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913879326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.3913879326
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.2341868393
Short name T275
Test name
Test status
Simulation time 4044152900 ps
CPU time 663.42 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:24:36 PM PDT 24
Peak memory 325720 kb
Host smart-4ad657fb-3562-48f1-9f5e-b4c301633f36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341868393 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.2341868393
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2671031085
Short name T6
Test name
Test status
Simulation time 1720061800 ps
CPU time 266 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:17:58 PM PDT 24
Peak memory 285412 kb
Host smart-4baef82d-bf33-40b9-ae92-3ab4955e5a2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671031085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2671031085
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1038113803
Short name T776
Test name
Test status
Simulation time 5743133300 ps
CPU time 128.71 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:15:41 PM PDT 24
Peak memory 293320 kb
Host smart-a8564112-ad45-4cc3-be3a-a54f634601c1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038113803 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.1038113803
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.367275717
Short name T958
Test name
Test status
Simulation time 8431661500 ps
CPU time 74.57 seconds
Started Jun 27 05:13:30 PM PDT 24
Finished Jun 27 05:14:46 PM PDT 24
Peak memory 265324 kb
Host smart-fd9751d9-10f9-48a4-8c9c-869ee6d6d289
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367275717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.367275717
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1519393945
Short name T717
Test name
Test status
Simulation time 8676843100 ps
CPU time 81.78 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:14:35 PM PDT 24
Peak memory 263056 kb
Host smart-26fca30d-515c-485f-a14a-130f3e3419b0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519393945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1519393945
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3048518312
Short name T1111
Test name
Test status
Simulation time 45655300 ps
CPU time 13.79 seconds
Started Jun 27 05:13:50 PM PDT 24
Finished Jun 27 05:14:05 PM PDT 24
Peak memory 261044 kb
Host smart-93196768-f32b-463e-865d-d7df99b8ddd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048518312 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3048518312
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1731394430
Short name T91
Test name
Test status
Simulation time 1930209200 ps
CPU time 68.74 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:14:22 PM PDT 24
Peak memory 260908 kb
Host smart-44249034-5d8b-463a-af52-52da4e60291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731394430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1731394430
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.2843474808
Short name T992
Test name
Test status
Simulation time 30529324700 ps
CPU time 725.09 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:25:17 PM PDT 24
Peak memory 275124 kb
Host smart-c84b58c6-17bb-4cc6-ac3d-3c5526018e44
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843474808 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.2843474808
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2282428465
Short name T778
Test name
Test status
Simulation time 40039400 ps
CPU time 133.42 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:15:25 PM PDT 24
Peak memory 265624 kb
Host smart-5e1ec1a0-ff73-40ea-b0b1-68beddfd2e00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282428465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2282428465
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.2413057971
Short name T558
Test name
Test status
Simulation time 1792989200 ps
CPU time 146.61 seconds
Started Jun 27 05:13:30 PM PDT 24
Finished Jun 27 05:15:58 PM PDT 24
Peak memory 282260 kb
Host smart-12a1eb12-6543-4b30-9876-0f3c0b03c147
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413057971 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2413057971
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1983805089
Short name T61
Test name
Test status
Simulation time 20103900 ps
CPU time 14.11 seconds
Started Jun 27 05:13:50 PM PDT 24
Finished Jun 27 05:14:05 PM PDT 24
Peak memory 279328 kb
Host smart-643ef5fd-45e4-4d29-9bb4-2f5ab1d8dfba
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1983805089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1983805089
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.2110636734
Short name T775
Test name
Test status
Simulation time 256516600 ps
CPU time 323.93 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:18:36 PM PDT 24
Peak memory 263492 kb
Host smart-c10a65f2-0bb4-430a-a383-4cbfbed25d6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110636734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.2110636734
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.220271891
Short name T114
Test name
Test status
Simulation time 848827100 ps
CPU time 17.73 seconds
Started Jun 27 05:13:50 PM PDT 24
Finished Jun 27 05:14:08 PM PDT 24
Peak memory 264608 kb
Host smart-b07a1769-193f-40f2-aec9-3564eeb0c0be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220271891 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.220271891
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.3739446150
Short name T212
Test name
Test status
Simulation time 44303400 ps
CPU time 14.35 seconds
Started Jun 27 05:13:49 PM PDT 24
Finished Jun 27 05:14:04 PM PDT 24
Peak memory 265856 kb
Host smart-d9c21568-8b84-47c6-b394-90b7a13b3080
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739446150 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.3739446150
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.4256479516
Short name T826
Test name
Test status
Simulation time 29425100 ps
CPU time 13.57 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:13:46 PM PDT 24
Peak memory 259180 kb
Host smart-04ef6a97-6b89-467b-8e66-879fc231e1e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256479516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_prog_reset.4256479516
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.843985170
Short name T146
Test name
Test status
Simulation time 444449200 ps
CPU time 475.92 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:20:51 PM PDT 24
Peak memory 282924 kb
Host smart-2976083b-1f15-4e9c-892d-37ca1e2920a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843985170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.843985170
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3056248890
Short name T599
Test name
Test status
Simulation time 96246500 ps
CPU time 102.72 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:14:54 PM PDT 24
Peak memory 263120 kb
Host smart-94d66c94-30a2-43f4-a9c4-b961e1f28157
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3056248890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3056248890
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.1462219545
Short name T955
Test name
Test status
Simulation time 72045800 ps
CPU time 34.58 seconds
Started Jun 27 05:13:33 PM PDT 24
Finished Jun 27 05:14:08 PM PDT 24
Peak memory 270424 kb
Host smart-4bfe4afc-2822-4e77-b761-6acb6d89fd68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462219545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.1462219545
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1965360104
Short name T936
Test name
Test status
Simulation time 294770000 ps
CPU time 26.62 seconds
Started Jun 27 05:13:33 PM PDT 24
Finished Jun 27 05:14:00 PM PDT 24
Peak memory 265428 kb
Host smart-025d04d7-2ef0-4d2c-aaad-e75c8d58957d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965360104 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.1965360104
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.1404735527
Short name T683
Test name
Test status
Simulation time 97094200 ps
CPU time 27.42 seconds
Started Jun 27 05:13:13 PM PDT 24
Finished Jun 27 05:13:41 PM PDT 24
Peak memory 265220 kb
Host smart-7df2d618-f43d-48bc-9a93-6a4ac4017e44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404735527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.1404735527
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.4164709099
Short name T55
Test name
Test status
Simulation time 435684800 ps
CPU time 102.03 seconds
Started Jun 27 05:13:10 PM PDT 24
Finished Jun 27 05:14:53 PM PDT 24
Peak memory 296960 kb
Host smart-f88ce8ea-c7fc-4f01-9e8b-364af9da4518
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164709099 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.4164709099
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.594563642
Short name T735
Test name
Test status
Simulation time 668104400 ps
CPU time 163.94 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:16:16 PM PDT 24
Peak memory 282324 kb
Host smart-e6335a50-d31d-4ff9-a80f-ddf8b05cfb2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
594563642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.594563642
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3759875588
Short name T903
Test name
Test status
Simulation time 1137113200 ps
CPU time 127.28 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:15:40 PM PDT 24
Peak memory 295696 kb
Host smart-85ea9bef-e0f9-4df0-9fa8-b8b0e72aa2fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759875588 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3759875588
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.2851297530
Short name T789
Test name
Test status
Simulation time 19451510500 ps
CPU time 651.65 seconds
Started Jun 27 05:13:11 PM PDT 24
Finished Jun 27 05:24:05 PM PDT 24
Peak memory 318128 kb
Host smart-6d76c1e4-d8da-475f-b9af-46f7ac002336
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851297530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.2851297530
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2982967220
Short name T669
Test name
Test status
Simulation time 30995500 ps
CPU time 32.18 seconds
Started Jun 27 05:13:30 PM PDT 24
Finished Jun 27 05:14:03 PM PDT 24
Peak memory 276016 kb
Host smart-c750cabc-2807-4893-90cb-f8269d60feae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982967220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2982967220
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.4286661984
Short name T360
Test name
Test status
Simulation time 32086500 ps
CPU time 32.2 seconds
Started Jun 27 05:13:30 PM PDT 24
Finished Jun 27 05:14:03 PM PDT 24
Peak memory 276968 kb
Host smart-f63320bc-a415-4dd5-bf88-905b9a5a5217
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286661984 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.4286661984
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3556100933
Short name T17
Test name
Test status
Simulation time 3021623400 ps
CPU time 4783.18 seconds
Started Jun 27 05:13:48 PM PDT 24
Finished Jun 27 06:33:32 PM PDT 24
Peak memory 286420 kb
Host smart-01fde4e8-1c6c-4a16-8432-a9e1bf515d36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556100933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3556100933
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.454732982
Short name T488
Test name
Test status
Simulation time 1604075100 ps
CPU time 66.74 seconds
Started Jun 27 05:13:50 PM PDT 24
Finished Jun 27 05:14:58 PM PDT 24
Peak memory 265356 kb
Host smart-036296e8-ed44-4273-9ca8-f64d37db957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454732982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.454732982
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2533682672
Short name T517
Test name
Test status
Simulation time 1285927600 ps
CPU time 58.09 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:14:30 PM PDT 24
Peak memory 265768 kb
Host smart-4a402a51-417c-45d0-9ebd-cf998a892180
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533682672 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2533682672
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.1623154366
Short name T724
Test name
Test status
Simulation time 3791392300 ps
CPU time 91.64 seconds
Started Jun 27 05:13:31 PM PDT 24
Finished Jun 27 05:15:03 PM PDT 24
Peak memory 276388 kb
Host smart-01df6a4c-efec-443a-8359-42bf4face7fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623154366 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.1623154366
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.75819581
Short name T622
Test name
Test status
Simulation time 28470100 ps
CPU time 122.87 seconds
Started Jun 27 05:12:54 PM PDT 24
Finished Jun 27 05:14:59 PM PDT 24
Peak memory 277564 kb
Host smart-5afe42fa-5cff-4744-b24b-eb0110ebf787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75819581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.75819581
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1808815697
Short name T1006
Test name
Test status
Simulation time 38535400 ps
CPU time 26.39 seconds
Started Jun 27 05:12:56 PM PDT 24
Finished Jun 27 05:13:24 PM PDT 24
Peak memory 260100 kb
Host smart-7720fd0d-65bb-49d4-a1f1-fe6618b068cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808815697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1808815697
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.687690385
Short name T845
Test name
Test status
Simulation time 464451900 ps
CPU time 576.8 seconds
Started Jun 27 05:13:52 PM PDT 24
Finished Jun 27 05:23:29 PM PDT 24
Peak memory 290276 kb
Host smart-718f77de-aa3a-4710-ac00-1730575d77be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687690385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.687690385
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.1797425734
Short name T1039
Test name
Test status
Simulation time 20802000 ps
CPU time 26.27 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:13:40 PM PDT 24
Peak memory 262716 kb
Host smart-53b10bd8-3400-4977-8940-672dd6d75f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797425734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1797425734
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1812707947
Short name T273
Test name
Test status
Simulation time 10973616800 ps
CPU time 145.72 seconds
Started Jun 27 05:13:12 PM PDT 24
Finished Jun 27 05:15:39 PM PDT 24
Peak memory 260244 kb
Host smart-9ab04331-185c-4e94-adb6-dfd2a5d9b7ab
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812707947 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.1812707947
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.730912415
Short name T528
Test name
Test status
Simulation time 63951400 ps
CPU time 13.69 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:22:16 PM PDT 24
Peak memory 265612 kb
Host smart-bc07bb61-f386-46dc-a873-89653c136996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730912415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.730912415
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.4257446461
Short name T925
Test name
Test status
Simulation time 45956500 ps
CPU time 15.72 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:20 PM PDT 24
Peak memory 275408 kb
Host smart-21165c54-6ef8-44ea-a95a-a919071838b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257446461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.4257446461
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1124339962
Short name T440
Test name
Test status
Simulation time 14086200 ps
CPU time 22.25 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:26 PM PDT 24
Peak memory 273772 kb
Host smart-8ad81c9c-cb97-48bd-83c8-c6125bcfc01d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124339962 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1124339962
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1133219877
Short name T870
Test name
Test status
Simulation time 4886855000 ps
CPU time 212.12 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:25:36 PM PDT 24
Peak memory 263800 kb
Host smart-5c61262b-2021-42a3-9f1d-fb5763b29a41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133219877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1133219877
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.422016205
Short name T1096
Test name
Test status
Simulation time 147972400 ps
CPU time 112.18 seconds
Started Jun 27 05:21:59 PM PDT 24
Finished Jun 27 05:23:52 PM PDT 24
Peak memory 260404 kb
Host smart-603e113f-1c3d-4036-a222-bdb87748949c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422016205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_ot
p_reset.422016205
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.355150533
Short name T872
Test name
Test status
Simulation time 1339189100 ps
CPU time 69.64 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 263544 kb
Host smart-8a3abaad-62d5-4efe-b577-3366b14f0f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355150533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.355150533
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2784537489
Short name T652
Test name
Test status
Simulation time 109277500 ps
CPU time 149.05 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:24:32 PM PDT 24
Peak memory 277244 kb
Host smart-7d33ff36-0193-4ed4-8fc8-f4a60b7fa168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784537489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2784537489
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.539650671
Short name T912
Test name
Test status
Simulation time 198927800 ps
CPU time 15.02 seconds
Started Jun 27 05:21:58 PM PDT 24
Finished Jun 27 05:22:14 PM PDT 24
Peak memory 258716 kb
Host smart-6c1e20f1-a5c7-40a0-a89c-588a53b62d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539650671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.539650671
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2058515230
Short name T462
Test name
Test status
Simulation time 13679700 ps
CPU time 17.05 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:21 PM PDT 24
Peak memory 275192 kb
Host smart-ada36a9e-846e-4ff7-8ebc-0a109582eaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058515230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2058515230
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.589574599
Short name T98
Test name
Test status
Simulation time 28264900 ps
CPU time 22.26 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:22:24 PM PDT 24
Peak memory 274044 kb
Host smart-b30adfcc-7f2f-43f7-992a-5544497a4366
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589574599 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.589574599
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.534926189
Short name T716
Test name
Test status
Simulation time 4456962700 ps
CPU time 95.63 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:23:39 PM PDT 24
Peak memory 263716 kb
Host smart-812a23fb-4523-48cf-b128-2a77341074aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534926189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_h
w_sec_otp.534926189
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2742370104
Short name T174
Test name
Test status
Simulation time 72420600 ps
CPU time 111.05 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:23:55 PM PDT 24
Peak memory 260600 kb
Host smart-34bbbb9a-d571-441c-88d9-04bdf5d5fbf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742370104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2742370104
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.3514610859
Short name T221
Test name
Test status
Simulation time 314738600 ps
CPU time 73.06 seconds
Started Jun 27 05:21:58 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 275848 kb
Host smart-6d9c7fa3-111c-4ddc-910e-53ce58e6613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514610859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3514610859
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.268836305
Short name T477
Test name
Test status
Simulation time 499546800 ps
CPU time 14.79 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:18 PM PDT 24
Peak memory 258600 kb
Host smart-3b390788-4226-40ba-941d-cc3b60267b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268836305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.268836305
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.2216612846
Short name T812
Test name
Test status
Simulation time 45876500 ps
CPU time 16.36 seconds
Started Jun 27 05:22:04 PM PDT 24
Finished Jun 27 05:22:22 PM PDT 24
Peak memory 275480 kb
Host smart-75ab5cb9-2be7-4524-b2ab-123b24dfad0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216612846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2216612846
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3992424018
Short name T381
Test name
Test status
Simulation time 16606800 ps
CPU time 20.57 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:22:24 PM PDT 24
Peak memory 273908 kb
Host smart-4c512a50-a221-4b85-8709-a20f35d3a96b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992424018 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3992424018
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.824387965
Short name T1094
Test name
Test status
Simulation time 8322240500 ps
CPU time 144.86 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:24:29 PM PDT 24
Peak memory 261280 kb
Host smart-7b5e03a2-d70c-4b7e-8ae9-0625fdb0e20b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824387965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h
w_sec_otp.824387965
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.658356199
Short name T751
Test name
Test status
Simulation time 34743700 ps
CPU time 116.53 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:24:00 PM PDT 24
Peak memory 265252 kb
Host smart-bf17ae6b-f8af-4817-b250-6761d86eee31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658356199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_ot
p_reset.658356199
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.812177097
Short name T940
Test name
Test status
Simulation time 14990320300 ps
CPU time 275.2 seconds
Started Jun 27 05:22:01 PM PDT 24
Finished Jun 27 05:26:39 PM PDT 24
Peak memory 281864 kb
Host smart-268327c8-3c48-4bab-a90c-dfa2a1d80180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812177097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.812177097
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.852541193
Short name T677
Test name
Test status
Simulation time 111753200 ps
CPU time 14.05 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:22:48 PM PDT 24
Peak memory 265556 kb
Host smart-41e991c3-1ef6-4ee1-b76e-18a1407aab04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852541193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.852541193
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.2418862754
Short name T921
Test name
Test status
Simulation time 48268600 ps
CPU time 13.29 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:22:46 PM PDT 24
Peak memory 284864 kb
Host smart-398b4b67-8392-44fd-a77b-b8d702b3e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418862754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2418862754
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3431590440
Short name T383
Test name
Test status
Simulation time 15558300 ps
CPU time 20.89 seconds
Started Jun 27 05:22:35 PM PDT 24
Finished Jun 27 05:22:57 PM PDT 24
Peak memory 273956 kb
Host smart-89063984-817a-498c-acc9-9c30290ae38d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431590440 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3431590440
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1307963273
Short name T844
Test name
Test status
Simulation time 10302435100 ps
CPU time 92.07 seconds
Started Jun 27 05:22:02 PM PDT 24
Finished Jun 27 05:23:36 PM PDT 24
Peak memory 261472 kb
Host smart-687be9ed-ef00-4e2a-8544-5b1318ca1c5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307963273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1307963273
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2735883828
Short name T792
Test name
Test status
Simulation time 41168300 ps
CPU time 133.3 seconds
Started Jun 27 05:22:00 PM PDT 24
Finished Jun 27 05:24:16 PM PDT 24
Peak memory 260340 kb
Host smart-10845126-7456-4fb6-a526-4a34da44a382
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735883828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2735883828
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2172899001
Short name T1026
Test name
Test status
Simulation time 3431571400 ps
CPU time 70.51 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:23:46 PM PDT 24
Peak memory 263844 kb
Host smart-b6677d68-491b-4042-bfd5-4c3035417d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172899001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2172899001
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.688151856
Short name T435
Test name
Test status
Simulation time 60290000 ps
CPU time 97.56 seconds
Started Jun 27 05:22:04 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 276152 kb
Host smart-2ce02d9f-7097-402e-9a6f-ea18a1a108ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688151856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.688151856
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.4006045764
Short name T1002
Test name
Test status
Simulation time 27623700 ps
CPU time 13.68 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:22:46 PM PDT 24
Peak memory 258444 kb
Host smart-a9e5002d-9c35-480a-a9f7-9a97819e5297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006045764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
4006045764
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3509298332
Short name T625
Test name
Test status
Simulation time 15235900 ps
CPU time 15.93 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:22:52 PM PDT 24
Peak memory 275332 kb
Host smart-1b5ce78a-bb6c-4a88-8a3f-c3b845261e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509298332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3509298332
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.651563320
Short name T386
Test name
Test status
Simulation time 68502200 ps
CPU time 22.39 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:22:57 PM PDT 24
Peak memory 273940 kb
Host smart-169c042a-29fa-410a-b553-8d6d1d64796a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651563320 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.651563320
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3791255651
Short name T993
Test name
Test status
Simulation time 935630800 ps
CPU time 37.26 seconds
Started Jun 27 05:22:31 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 261416 kb
Host smart-3ce61246-3f38-401a-8c9c-228f1baf5031
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791255651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3791255651
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.3839477476
Short name T539
Test name
Test status
Simulation time 130473300 ps
CPU time 133.05 seconds
Started Jun 27 05:22:35 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 260176 kb
Host smart-990128e7-d385-4bf5-b087-f023323a0d0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839477476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.3839477476
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2157634923
Short name T409
Test name
Test status
Simulation time 3421624100 ps
CPU time 67.45 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:23:42 PM PDT 24
Peak memory 264116 kb
Host smart-eccfcb31-f041-4211-9a53-14c9e0946352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157634923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2157634923
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.4169742693
Short name T576
Test name
Test status
Simulation time 105819000 ps
CPU time 148.72 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:25:04 PM PDT 24
Peak memory 277396 kb
Host smart-47621e1e-9804-48ba-941c-16df6581953a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169742693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.4169742693
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.3424849059
Short name T643
Test name
Test status
Simulation time 56462100 ps
CPU time 14.1 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:22:49 PM PDT 24
Peak memory 265564 kb
Host smart-3b5d2e23-018e-48ea-981e-1ded9be19004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424849059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
3424849059
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2595696532
Short name T616
Test name
Test status
Simulation time 93325100 ps
CPU time 15.88 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:22:52 PM PDT 24
Peak memory 284888 kb
Host smart-e8a741fb-cc80-4e61-be8c-368fbe560412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595696532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2595696532
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.159157001
Short name T384
Test name
Test status
Simulation time 16783200 ps
CPU time 21.86 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:22:55 PM PDT 24
Peak memory 274000 kb
Host smart-ba5e95df-4a56-42db-8552-dcda9268a926
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159157001 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.159157001
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.1699562346
Short name T311
Test name
Test status
Simulation time 7190148600 ps
CPU time 133.12 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:24:47 PM PDT 24
Peak memory 262492 kb
Host smart-aba41e1b-27de-4111-84c1-34df64a82e59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699562346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.1699562346
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1196238280
Short name T888
Test name
Test status
Simulation time 135975500 ps
CPU time 113.65 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:24:27 PM PDT 24
Peak memory 261416 kb
Host smart-faa6562c-d1b6-41f4-9bd5-6e61ef574ec2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196238280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1196238280
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1069752077
Short name T631
Test name
Test status
Simulation time 4688829200 ps
CPU time 51.69 seconds
Started Jun 27 05:22:35 PM PDT 24
Finished Jun 27 05:23:28 PM PDT 24
Peak memory 265116 kb
Host smart-570ce1bb-43e8-4fa2-bf17-792c6c946810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069752077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1069752077
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1001778487
Short name T641
Test name
Test status
Simulation time 24566600 ps
CPU time 75.04 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:23:48 PM PDT 24
Peak memory 269068 kb
Host smart-54f3ba14-31ce-4c19-be5d-e4a5eb47ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001778487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1001778487
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1625488744
Short name T650
Test name
Test status
Simulation time 33105900 ps
CPU time 14.17 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:22:50 PM PDT 24
Peak memory 265564 kb
Host smart-9e8aecc8-18fa-420b-a2eb-0dc279e9e6e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625488744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1625488744
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2948066699
Short name T1089
Test name
Test status
Simulation time 13760300 ps
CPU time 13.4 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:22:48 PM PDT 24
Peak memory 275396 kb
Host smart-896e0032-223f-486d-831d-a9c7d6fbb709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948066699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2948066699
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.1005158587
Short name T1086
Test name
Test status
Simulation time 67381400 ps
CPU time 20.51 seconds
Started Jun 27 05:22:31 PM PDT 24
Finished Jun 27 05:22:53 PM PDT 24
Peak memory 273800 kb
Host smart-39ba2359-ac87-4624-85b4-8238a0bde826
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005158587 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.1005158587
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.2269922350
Short name T112
Test name
Test status
Simulation time 15505907600 ps
CPU time 137.62 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:24:54 PM PDT 24
Peak memory 263380 kb
Host smart-0f525837-acde-46ac-a439-080e382cced1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269922350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.2269922350
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3187822022
Short name T399
Test name
Test status
Simulation time 39992200 ps
CPU time 110.92 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:24:25 PM PDT 24
Peak memory 265572 kb
Host smart-f44d4d9f-a848-426a-8a24-35759771f437
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187822022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3187822022
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.1342627489
Short name T889
Test name
Test status
Simulation time 2553366200 ps
CPU time 60.93 seconds
Started Jun 27 05:22:33 PM PDT 24
Finished Jun 27 05:23:35 PM PDT 24
Peak memory 265328 kb
Host smart-0b98be91-e066-45de-b295-1a7113b7fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342627489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1342627489
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.1784592261
Short name T932
Test name
Test status
Simulation time 20075400 ps
CPU time 54.17 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:23:29 PM PDT 24
Peak memory 271612 kb
Host smart-85612735-c9e9-4ff6-8ba0-816fe190f1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784592261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1784592261
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.298798284
Short name T693
Test name
Test status
Simulation time 66405400 ps
CPU time 13.63 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 265596 kb
Host smart-c282951a-8e7f-447c-a4c1-b002ca0b76e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298798284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.298798284
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.3794189049
Short name T829
Test name
Test status
Simulation time 55184500 ps
CPU time 16.11 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:23:16 PM PDT 24
Peak memory 275360 kb
Host smart-3a032315-ef84-409a-b023-80065c2854f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794189049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.3794189049
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2743399939
Short name T484
Test name
Test status
Simulation time 25760000 ps
CPU time 20.96 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:17 PM PDT 24
Peak memory 265796 kb
Host smart-83d82c6b-25e7-4386-8be4-9da7dd0a98a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743399939 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2743399939
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1417024858
Short name T303
Test name
Test status
Simulation time 6496785200 ps
CPU time 72.18 seconds
Started Jun 27 05:22:32 PM PDT 24
Finished Jun 27 05:23:45 PM PDT 24
Peak memory 261448 kb
Host smart-da50c7b2-dea5-4293-9088-d8366200de5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417024858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1417024858
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.1810578282
Short name T170
Test name
Test status
Simulation time 66682000 ps
CPU time 115.22 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:24:55 PM PDT 24
Peak memory 261480 kb
Host smart-8326cb5b-d499-474f-b870-82d30118becf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810578282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.1810578282
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.253423753
Short name T732
Test name
Test status
Simulation time 18310089900 ps
CPU time 96.53 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:24:35 PM PDT 24
Peak memory 264472 kb
Host smart-f1cb1d91-4797-4334-9872-38206ebc85fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253423753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.253423753
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.888417466
Short name T951
Test name
Test status
Simulation time 51007300 ps
CPU time 98.66 seconds
Started Jun 27 05:22:34 PM PDT 24
Finished Jun 27 05:24:15 PM PDT 24
Peak memory 277388 kb
Host smart-a4499df2-6a16-43bd-a99e-9f6f9abf3307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888417466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.888417466
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.2816423806
Short name T885
Test name
Test status
Simulation time 55280400 ps
CPU time 14.04 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 265660 kb
Host smart-a840615f-4db9-46b8-bce2-c7a055430cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816423806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
2816423806
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.4231363423
Short name T518
Test name
Test status
Simulation time 30345200 ps
CPU time 16.26 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 275312 kb
Host smart-e06ff2c2-4130-4c35-a230-799904b2b119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231363423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.4231363423
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.2945685859
Short name T973
Test name
Test status
Simulation time 37214100 ps
CPU time 22.36 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:21 PM PDT 24
Peak memory 273964 kb
Host smart-3f673fe1-fc68-49f3-9aa8-cfff962eafab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945685859 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.2945685859
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2115840558
Short name T486
Test name
Test status
Simulation time 42056800 ps
CPU time 110.83 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:24:49 PM PDT 24
Peak memory 261576 kb
Host smart-2ab10e92-c02f-4f53-8e18-0f708c77a026
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115840558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2115840558
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.3991328030
Short name T1007
Test name
Test status
Simulation time 4808538200 ps
CPU time 58.74 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:53 PM PDT 24
Peak memory 263772 kb
Host smart-fb133c17-b8a1-4940-b4fe-03070d2423e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991328030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.3991328030
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2811556094
Short name T763
Test name
Test status
Simulation time 165466000 ps
CPU time 100.58 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:24:40 PM PDT 24
Peak memory 276104 kb
Host smart-73da3504-4440-43b6-b0ac-52df7255a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811556094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2811556094
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.3083087817
Short name T1112
Test name
Test status
Simulation time 16731800 ps
CPU time 15.95 seconds
Started Jun 27 05:22:53 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 275720 kb
Host smart-01838759-1b32-40f4-a294-e17b262546d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083087817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3083087817
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.4218257948
Short name T97
Test name
Test status
Simulation time 33830900 ps
CPU time 21.86 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:16 PM PDT 24
Peak memory 265888 kb
Host smart-9f38fbf4-c661-4ced-a614-9d6b531d6676
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218257948 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.4218257948
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2234358050
Short name T314
Test name
Test status
Simulation time 552882600 ps
CPU time 46.02 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:43 PM PDT 24
Peak memory 263656 kb
Host smart-34719f44-c72e-46fb-b3cb-1bbed8d53a4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234358050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2234358050
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.315905272
Short name T713
Test name
Test status
Simulation time 34794000 ps
CPU time 131.31 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:25:08 PM PDT 24
Peak memory 260656 kb
Host smart-76d34117-5b90-420d-81b0-038af89c405e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315905272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ot
p_reset.315905272
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.87564971
Short name T408
Test name
Test status
Simulation time 7498230600 ps
CPU time 75.58 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:24:08 PM PDT 24
Peak memory 265524 kb
Host smart-ec8cd60a-fa44-4fef-9180-13e48b447a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87564971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.87564971
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3682242728
Short name T718
Test name
Test status
Simulation time 68753700 ps
CPU time 98.08 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:24:35 PM PDT 24
Peak memory 269036 kb
Host smart-386880ad-d3e2-4894-893e-ba58db26293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682242728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3682242728
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.3066313483
Short name T457
Test name
Test status
Simulation time 104405900 ps
CPU time 14.24 seconds
Started Jun 27 05:14:25 PM PDT 24
Finished Jun 27 05:14:40 PM PDT 24
Peak memory 258640 kb
Host smart-695ebf7a-5676-4635-b926-c7e186667001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066313483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.3
066313483
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.3558475065
Short name T586
Test name
Test status
Simulation time 23673700 ps
CPU time 15.65 seconds
Started Jun 27 05:14:13 PM PDT 24
Finished Jun 27 05:14:30 PM PDT 24
Peak memory 275332 kb
Host smart-186e9a5d-0485-402d-a7b2-871a7112466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558475065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3558475065
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.2998692672
Short name T585
Test name
Test status
Simulation time 25953000 ps
CPU time 22.13 seconds
Started Jun 27 05:14:08 PM PDT 24
Finished Jun 27 05:14:31 PM PDT 24
Peak memory 273964 kb
Host smart-51bf3f59-3188-4f9b-92c9-6423cdfd0054
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998692672 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.2998692672
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.271987223
Short name T72
Test name
Test status
Simulation time 3415921000 ps
CPU time 2177.51 seconds
Started Jun 27 05:14:05 PM PDT 24
Finished Jun 27 05:50:23 PM PDT 24
Peak memory 263232 kb
Host smart-52119208-5c56-4007-87c7-ab3f99cea2ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=271987223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.271987223
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.980967667
Short name T561
Test name
Test status
Simulation time 701869000 ps
CPU time 897.12 seconds
Started Jun 27 05:14:05 PM PDT 24
Finished Jun 27 05:29:04 PM PDT 24
Peak memory 270808 kb
Host smart-2940ea2d-5f81-467a-a7a5-ee0ba56424f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980967667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.980967667
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.182092669
Short name T1097
Test name
Test status
Simulation time 351598300 ps
CPU time 28.92 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:14:36 PM PDT 24
Peak memory 262756 kb
Host smart-6ca0d7af-e51d-4b32-86d2-8b101a3db89b
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182092669 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_fetch_code.182092669
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1760600370
Short name T182
Test name
Test status
Simulation time 10020014300 ps
CPU time 77.51 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:15:26 PM PDT 24
Peak memory 307268 kb
Host smart-43f30855-e0ba-4045-861f-406405b107d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760600370 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.1760600370
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.1293659589
Short name T3
Test name
Test status
Simulation time 18892000 ps
CPU time 13.8 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:14:21 PM PDT 24
Peak memory 258916 kb
Host smart-6a0ff1c6-8da1-49e5-999a-0c6162bc6bff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293659589 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.1293659589
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.3703371084
Short name T887
Test name
Test status
Simulation time 40124698300 ps
CPU time 826.91 seconds
Started Jun 27 05:13:52 PM PDT 24
Finished Jun 27 05:27:40 PM PDT 24
Peak memory 264156 kb
Host smart-4e40d042-ddde-4579-88f2-7538f6e22459
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703371084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.3703371084
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2362804254
Short name T433
Test name
Test status
Simulation time 5778507300 ps
CPU time 198.65 seconds
Started Jun 27 05:13:50 PM PDT 24
Finished Jun 27 05:17:09 PM PDT 24
Peak memory 261260 kb
Host smart-43148d9a-c6c0-419b-8e07-645eccdc056e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362804254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.2362804254
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2045193451
Short name T971
Test name
Test status
Simulation time 23376179100 ps
CPU time 272.2 seconds
Started Jun 27 05:14:14 PM PDT 24
Finished Jun 27 05:18:47 PM PDT 24
Peak memory 290172 kb
Host smart-ff002aa5-45e4-442a-9925-fbdd4aef8dbc
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045193451 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.2045193451
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3348441801
Short name T1088
Test name
Test status
Simulation time 2586782800 ps
CPU time 79.42 seconds
Started Jun 27 05:14:08 PM PDT 24
Finished Jun 27 05:15:28 PM PDT 24
Peak memory 265472 kb
Host smart-20e2d6bc-4349-454d-aef0-ad070314e3d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348441801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3348441801
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2327863315
Short name T1
Test name
Test status
Simulation time 18511055800 ps
CPU time 157.51 seconds
Started Jun 27 05:14:05 PM PDT 24
Finished Jun 27 05:16:43 PM PDT 24
Peak memory 260004 kb
Host smart-0713c659-5f3b-4eb8-ac74-5e33245832b5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232
7863315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2327863315
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3293183176
Short name T919
Test name
Test status
Simulation time 3881004200 ps
CPU time 60.71 seconds
Started Jun 27 05:14:13 PM PDT 24
Finished Jun 27 05:15:15 PM PDT 24
Peak memory 261164 kb
Host smart-4b971d85-e0d3-4585-9052-2a11c662ee89
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293183176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3293183176
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.779064756
Short name T282
Test name
Test status
Simulation time 80706300 ps
CPU time 13.71 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:14:21 PM PDT 24
Peak memory 260288 kb
Host smart-c7e83ebc-d4c9-42cb-8518-5e9c58f13fc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779064756 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.779064756
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2212879620
Short name T137
Test name
Test status
Simulation time 13515679700 ps
CPU time 577.54 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:23:46 PM PDT 24
Peak memory 275160 kb
Host smart-c7cdd5f5-959d-4250-b20c-50490b883ed6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212879620 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.2212879620
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.3026135659
Short name T77
Test name
Test status
Simulation time 141587600 ps
CPU time 132.38 seconds
Started Jun 27 05:13:49 PM PDT 24
Finished Jun 27 05:16:02 PM PDT 24
Peak memory 264596 kb
Host smart-0113728d-2b4c-4f69-b8db-d22a917c12dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026135659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.3026135659
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1742285610
Short name T869
Test name
Test status
Simulation time 966138100 ps
CPU time 164.33 seconds
Started Jun 27 05:13:49 PM PDT 24
Finished Jun 27 05:16:34 PM PDT 24
Peak memory 263372 kb
Host smart-d4109f44-fcdf-49c7-8e83-2cd071a52124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742285610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1742285610
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.728057750
Short name T606
Test name
Test status
Simulation time 62843800 ps
CPU time 14.93 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:14:22 PM PDT 24
Peak memory 260284 kb
Host smart-4125cd64-b6ee-442b-b8c7-5b8a851df20d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728057750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.flash_ctrl_prog_reset.728057750
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.2206921289
Short name T695
Test name
Test status
Simulation time 111694700 ps
CPU time 284.21 seconds
Started Jun 27 05:13:49 PM PDT 24
Finished Jun 27 05:18:34 PM PDT 24
Peak memory 282256 kb
Host smart-f10a7156-4751-4d9c-a955-21364997d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206921289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2206921289
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.4140937903
Short name T922
Test name
Test status
Simulation time 77898200 ps
CPU time 32.98 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:14:42 PM PDT 24
Peak memory 278280 kb
Host smart-018cfa7b-54c8-481e-817a-42fcc83fbd97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140937903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.4140937903
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2401111232
Short name T782
Test name
Test status
Simulation time 845075100 ps
CPU time 115.72 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:16:05 PM PDT 24
Peak memory 297744 kb
Host smart-a910207e-e9e9-4a7c-878f-337d5a0faea5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401111232 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2401111232
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1441950378
Short name T187
Test name
Test status
Simulation time 2413391400 ps
CPU time 155.57 seconds
Started Jun 27 05:14:08 PM PDT 24
Finished Jun 27 05:16:45 PM PDT 24
Peak memory 282756 kb
Host smart-c68df1f9-4b0d-4d7d-8a73-d34659e481f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1441950378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1441950378
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.1684524663
Short name T918
Test name
Test status
Simulation time 588149000 ps
CPU time 124.58 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:16:13 PM PDT 24
Peak memory 282348 kb
Host smart-eb77a78e-c008-4a15-b880-2aa0c3ce1357
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684524663 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.1684524663
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.917554846
Short name T1046
Test name
Test status
Simulation time 2863513900 ps
CPU time 493.5 seconds
Started Jun 27 05:14:08 PM PDT 24
Finished Jun 27 05:22:23 PM PDT 24
Peak memory 314480 kb
Host smart-36ec5b54-014a-42a4-9ee6-370671bf14fe
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917554846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_rw.917554846
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.2668443534
Short name T658
Test name
Test status
Simulation time 40351800 ps
CPU time 31.1 seconds
Started Jun 27 05:14:13 PM PDT 24
Finished Jun 27 05:14:45 PM PDT 24
Peak memory 275900 kb
Host smart-0084ca0f-48eb-4035-a8bd-d939e434cded
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668443534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.2668443534
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.4033422981
Short name T52
Test name
Test status
Simulation time 113198400 ps
CPU time 31.2 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:14:39 PM PDT 24
Peak memory 275852 kb
Host smart-e9a7bc1d-f700-45e7-8642-b313a2e724ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033422981 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.4033422981
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.490055160
Short name T988
Test name
Test status
Simulation time 3556609800 ps
CPU time 67.12 seconds
Started Jun 27 05:14:07 PM PDT 24
Finished Jun 27 05:15:16 PM PDT 24
Peak memory 265488 kb
Host smart-07550cd3-6a3c-4e63-80c5-685de48aa78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490055160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.490055160
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.3074779082
Short name T798
Test name
Test status
Simulation time 25200000 ps
CPU time 76.11 seconds
Started Jun 27 05:13:52 PM PDT 24
Finished Jun 27 05:15:09 PM PDT 24
Peak memory 275476 kb
Host smart-c1c79daa-f1e5-49c1-82d2-59bc6edcc6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074779082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.3074779082
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.183031246
Short name T459
Test name
Test status
Simulation time 4306199300 ps
CPU time 184.63 seconds
Started Jun 27 05:14:06 PM PDT 24
Finished Jun 27 05:17:11 PM PDT 24
Peak memory 259728 kb
Host smart-4a77d845-c640-44a1-b086-65ebdbffaae9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183031246 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_wo.183031246
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.1132775984
Short name T968
Test name
Test status
Simulation time 48009500 ps
CPU time 15.92 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 284840 kb
Host smart-1fe3dc58-aefb-4984-bbb6-4ee674bb3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132775984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1132775984
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.540784289
Short name T874
Test name
Test status
Simulation time 159724300 ps
CPU time 130.97 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:25:03 PM PDT 24
Peak memory 260428 kb
Host smart-6936cd31-35c7-4402-9b68-864f457672ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540784289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.540784289
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3859481781
Short name T613
Test name
Test status
Simulation time 105855200 ps
CPU time 15.67 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 284804 kb
Host smart-6b75117c-db8f-4961-802d-db6468173a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859481781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3859481781
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1244220605
Short name T933
Test name
Test status
Simulation time 54581600 ps
CPU time 13.86 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:23:06 PM PDT 24
Peak memory 284720 kb
Host smart-c71e6982-43d8-4785-b63f-ddacb9954deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244220605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1244220605
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.608845930
Short name T842
Test name
Test status
Simulation time 164542800 ps
CPU time 132.03 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:25:12 PM PDT 24
Peak memory 260588 kb
Host smart-782dbf39-0c12-4ca0-b0b5-e5bd77cf0b21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608845930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot
p_reset.608845930
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.3000678972
Short name T855
Test name
Test status
Simulation time 39158400 ps
CPU time 13.51 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:23:13 PM PDT 24
Peak memory 275136 kb
Host smart-0651039a-74ae-41ca-8e58-cc4db7b85d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000678972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.3000678972
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.2303062814
Short name T428
Test name
Test status
Simulation time 64709500 ps
CPU time 131.42 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:25:10 PM PDT 24
Peak memory 260324 kb
Host smart-2a453561-f079-42d3-9a84-518d3f5d4960
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303062814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.2303062814
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1529166684
Short name T810
Test name
Test status
Simulation time 68253500 ps
CPU time 13.69 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 275468 kb
Host smart-c89a4b00-3735-4aa4-9c80-e9260805cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529166684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1529166684
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.3540724503
Short name T1059
Test name
Test status
Simulation time 436883700 ps
CPU time 111.19 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:24:45 PM PDT 24
Peak memory 261540 kb
Host smart-d25389b8-57dd-4a6c-a4f4-5becbce195a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540724503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.3540724503
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.288340088
Short name T626
Test name
Test status
Simulation time 45297800 ps
CPU time 16.01 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:23:08 PM PDT 24
Peak memory 275232 kb
Host smart-09b4401e-8f00-48e8-b513-e2862eeb3a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288340088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.288340088
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.472961789
Short name T997
Test name
Test status
Simulation time 39930400 ps
CPU time 131.94 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:25:04 PM PDT 24
Peak memory 260736 kb
Host smart-7a5eb4ac-e1ae-4406-873c-67a16226a915
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472961789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.472961789
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.1481997530
Short name T721
Test name
Test status
Simulation time 52809600 ps
CPU time 15.84 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 275396 kb
Host smart-e857f995-4777-4910-83ea-93ade0681543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481997530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1481997530
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2567724339
Short name T169
Test name
Test status
Simulation time 35973700 ps
CPU time 132.57 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 260288 kb
Host smart-e01b34c8-c46f-4c4e-9a50-b7e4bb192f08
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567724339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2567724339
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1834904519
Short name T584
Test name
Test status
Simulation time 28838100 ps
CPU time 16.11 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:14 PM PDT 24
Peak memory 275268 kb
Host smart-23db72d3-d85d-42a0-868e-b4cd0db603c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834904519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1834904519
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.3740029401
Short name T882
Test name
Test status
Simulation time 39682100 ps
CPU time 112.6 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:24:45 PM PDT 24
Peak memory 265328 kb
Host smart-c407dc5e-8190-4717-8e8a-dad4a72ff07e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740029401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.3740029401
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1498923670
Short name T489
Test name
Test status
Simulation time 43694700 ps
CPU time 15.95 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:10 PM PDT 24
Peak memory 275316 kb
Host smart-c8fc08f5-6307-4c16-bba3-45cb3b668245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498923670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1498923670
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.2698976437
Short name T318
Test name
Test status
Simulation time 35146400 ps
CPU time 112.85 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:24:52 PM PDT 24
Peak memory 260888 kb
Host smart-25470516-627f-41cf-915e-861e58d5f733
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698976437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.2698976437
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.997503051
Short name T302
Test name
Test status
Simulation time 28473400 ps
CPU time 13.37 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 275428 kb
Host smart-4777358e-c445-4c5b-8271-a65ac653ebb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997503051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.997503051
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3693244045
Short name T766
Test name
Test status
Simulation time 36672500 ps
CPU time 13.89 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:15:02 PM PDT 24
Peak memory 258640 kb
Host smart-e2340cf0-6ac2-4ee4-b347-4b814addb2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693244045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
693244045
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.4104582014
Short name T619
Test name
Test status
Simulation time 22555400 ps
CPU time 15.9 seconds
Started Jun 27 05:14:48 PM PDT 24
Finished Jun 27 05:15:05 PM PDT 24
Peak memory 275428 kb
Host smart-308c37bb-7219-4675-8383-41d94d7cf786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104582014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.4104582014
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.579098932
Short name T807
Test name
Test status
Simulation time 17082100 ps
CPU time 20.93 seconds
Started Jun 27 05:14:49 PM PDT 24
Finished Jun 27 05:15:11 PM PDT 24
Peak memory 274024 kb
Host smart-ffc79550-fc47-40e9-ac3c-f0f86448338e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579098932 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.579098932
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.320994107
Short name T880
Test name
Test status
Simulation time 23963309100 ps
CPU time 2304.02 seconds
Started Jun 27 05:14:25 PM PDT 24
Finished Jun 27 05:52:50 PM PDT 24
Peak memory 265368 kb
Host smart-f7e613cb-53b2-4138-b1f4-f1984ac1b4d3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=320994107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.320994107
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.3759843167
Short name T803
Test name
Test status
Simulation time 1228647900 ps
CPU time 760.94 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:27:06 PM PDT 24
Peak memory 273320 kb
Host smart-68b9be93-be0c-4b4e-a72d-23aea31e67ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759843167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.3759843167
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.4169957988
Short name T48
Test name
Test status
Simulation time 1381655200 ps
CPU time 25.96 seconds
Started Jun 27 05:14:31 PM PDT 24
Finished Jun 27 05:14:58 PM PDT 24
Peak memory 262904 kb
Host smart-845ecdae-e21c-4f42-b238-4c469484fce5
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169957988 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_fetch_code.4169957988
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.82954175
Short name T1107
Test name
Test status
Simulation time 10035338900 ps
CPU time 53.74 seconds
Started Jun 27 05:14:46 PM PDT 24
Finished Jun 27 05:15:41 PM PDT 24
Peak memory 283828 kb
Host smart-ffc84286-02d0-4566-98ce-38247fe09e7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82954175 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.82954175
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.4262974411
Short name T280
Test name
Test status
Simulation time 47293800 ps
CPU time 13.94 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:15:01 PM PDT 24
Peak memory 259128 kb
Host smart-86f9f33b-83be-425c-8886-bce4e07bd9c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262974411 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.4262974411
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.4005375505
Short name T162
Test name
Test status
Simulation time 80152789600 ps
CPU time 837.56 seconds
Started Jun 27 05:14:26 PM PDT 24
Finished Jun 27 05:28:24 PM PDT 24
Peak memory 264588 kb
Host smart-cb63ec92-6b54-4c22-9a7f-3330caa1f695
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005375505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.4005375505
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.264142882
Short name T970
Test name
Test status
Simulation time 921098200 ps
CPU time 70.03 seconds
Started Jun 27 05:14:26 PM PDT 24
Finished Jun 27 05:15:37 PM PDT 24
Peak memory 263752 kb
Host smart-35fb07da-4442-47ea-89d2-7e5f53022404
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264142882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw
_sec_otp.264142882
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.3403713086
Short name T344
Test name
Test status
Simulation time 9301271600 ps
CPU time 205.47 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:18:13 PM PDT 24
Peak memory 291760 kb
Host smart-22f87617-1a57-4859-8b92-2237c4c17f46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403713086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.3403713086
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3787428644
Short name T345
Test name
Test status
Simulation time 39970259000 ps
CPU time 151.37 seconds
Started Jun 27 05:14:48 PM PDT 24
Finished Jun 27 05:17:21 PM PDT 24
Peak memory 290188 kb
Host smart-0b65121f-bd91-4746-a678-01bac94dbf4b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787428644 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3787428644
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3226145155
Short name T30
Test name
Test status
Simulation time 5469919900 ps
CPU time 75.88 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:16:04 PM PDT 24
Peak memory 260972 kb
Host smart-fab18fef-3f32-4823-8289-f5e94c3b555d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226145155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3226145155
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4077614139
Short name T496
Test name
Test status
Simulation time 49600754000 ps
CPU time 199.51 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:18:08 PM PDT 24
Peak memory 260704 kb
Host smart-137fd927-e52c-4671-aeae-418fe5bc2e91
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407
7614139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.4077614139
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3630478102
Short name T283
Test name
Test status
Simulation time 15541400 ps
CPU time 13.38 seconds
Started Jun 27 05:14:46 PM PDT 24
Finished Jun 27 05:14:59 PM PDT 24
Peak memory 265624 kb
Host smart-d73f1b35-4c66-4813-8306-3224763a648b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630478102 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3630478102
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3413474113
Short name T685
Test name
Test status
Simulation time 52097752400 ps
CPU time 606.66 seconds
Started Jun 27 05:14:30 PM PDT 24
Finished Jun 27 05:24:38 PM PDT 24
Peak memory 274560 kb
Host smart-2f9ddcec-01a9-44c2-b79c-6e23befb64e3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413474113 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.3413474113
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.189290365
Short name T168
Test name
Test status
Simulation time 71265800 ps
CPU time 113.73 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:16:18 PM PDT 24
Peak memory 265608 kb
Host smart-1eb4e6f2-fce1-4b0c-b069-a7093e9f5bc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189290365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp
_reset.189290365
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.179992336
Short name T620
Test name
Test status
Simulation time 102722600 ps
CPU time 68.6 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:15:33 PM PDT 24
Peak memory 263400 kb
Host smart-b3fe849b-edda-4cd0-bd0e-05cbed890cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179992336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.179992336
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.1537505165
Short name T794
Test name
Test status
Simulation time 71360100 ps
CPU time 13.83 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:15:02 PM PDT 24
Peak memory 265596 kb
Host smart-a96441d3-6435-4087-ad7d-976cea016765
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537505165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.flash_ctrl_prog_reset.1537505165
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.3558366620
Short name T1099
Test name
Test status
Simulation time 853148400 ps
CPU time 533.8 seconds
Started Jun 27 05:14:23 PM PDT 24
Finished Jun 27 05:23:17 PM PDT 24
Peak memory 285272 kb
Host smart-a015f44b-663d-4924-a8e5-7faefb0b694c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558366620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3558366620
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3209257542
Short name T362
Test name
Test status
Simulation time 69985400 ps
CPU time 35 seconds
Started Jun 27 05:14:46 PM PDT 24
Finished Jun 27 05:15:23 PM PDT 24
Peak memory 273340 kb
Host smart-36d4c4ff-efce-4c11-a58c-9b6a3bc1c16f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209257542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3209257542
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.282387765
Short name T632
Test name
Test status
Simulation time 2190814900 ps
CPU time 107.47 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:16:12 PM PDT 24
Peak memory 289724 kb
Host smart-ccd2914c-7473-4273-8d3d-ec4df9694d63
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282387765 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_ro.282387765
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.2212004836
Short name T811
Test name
Test status
Simulation time 632953300 ps
CPU time 125.48 seconds
Started Jun 27 05:14:25 PM PDT 24
Finished Jun 27 05:16:31 PM PDT 24
Peak memory 282284 kb
Host smart-28e3e9f4-19ab-46d5-a803-dc774150c3ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2212004836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2212004836
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3223580507
Short name T274
Test name
Test status
Simulation time 2363404100 ps
CPU time 115.47 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:16:21 PM PDT 24
Peak memory 293440 kb
Host smart-7682ed9b-45af-4bfa-9c43-828ceff0f33a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223580507 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3223580507
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.60435834
Short name T857
Test name
Test status
Simulation time 3510849400 ps
CPU time 652.83 seconds
Started Jun 27 05:14:24 PM PDT 24
Finished Jun 27 05:25:18 PM PDT 24
Peak memory 310040 kb
Host smart-d7c3245c-fb31-4b49-bb2f-8c6117237bdc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60435834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.60435834
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.3426872454
Short name T902
Test name
Test status
Simulation time 14093322800 ps
CPU time 669.68 seconds
Started Jun 27 05:14:49 PM PDT 24
Finished Jun 27 05:25:59 PM PDT 24
Peak memory 333112 kb
Host smart-0fb7c572-e1af-4760-9d37-340294380213
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426872454 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.3426872454
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3894589126
Short name T1000
Test name
Test status
Simulation time 39080200 ps
CPU time 31.46 seconds
Started Jun 27 05:14:48 PM PDT 24
Finished Jun 27 05:15:21 PM PDT 24
Peak memory 275920 kb
Host smart-10ccd3df-d19a-4e0e-8603-87a3e522b7b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894589126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3894589126
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3957375760
Short name T475
Test name
Test status
Simulation time 52951600 ps
CPU time 28.66 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:15:17 PM PDT 24
Peak memory 275880 kb
Host smart-e14e71fe-c0f4-4a87-87e4-50185bff0ce2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957375760 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3957375760
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.597618572
Short name T403
Test name
Test status
Simulation time 1201178200 ps
CPU time 60.61 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:15:48 PM PDT 24
Peak memory 263784 kb
Host smart-7a231c2a-aaa7-4cb2-a3ce-55b00a74ae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597618572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.597618572
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.2239588978
Short name T444
Test name
Test status
Simulation time 57243200 ps
CPU time 49.48 seconds
Started Jun 27 05:14:23 PM PDT 24
Finished Jun 27 05:15:13 PM PDT 24
Peak memory 271692 kb
Host smart-96801635-36b6-459a-8f5b-7112b4ba8faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239588978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2239588978
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.922043793
Short name T515
Test name
Test status
Simulation time 11853862100 ps
CPU time 260.97 seconds
Started Jun 27 05:14:25 PM PDT 24
Finished Jun 27 05:18:47 PM PDT 24
Peak memory 265560 kb
Host smart-89f708d8-3896-4fff-925d-d8ed086c8336
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922043793 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_wo.922043793
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3184186132
Short name T548
Test name
Test status
Simulation time 17464300 ps
CPU time 16.04 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 284820 kb
Host smart-8856e2db-00a2-401a-b4cc-26ac0321753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184186132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3184186132
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.1501858811
Short name T661
Test name
Test status
Simulation time 66369100 ps
CPU time 113.09 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:24:50 PM PDT 24
Peak memory 260744 kb
Host smart-fe587c71-2631-4a00-ba86-18171ac49c26
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501858811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.1501858811
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1453903692
Short name T913
Test name
Test status
Simulation time 77548600 ps
CPU time 15.88 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 275340 kb
Host smart-80af5018-9d35-4de4-b5eb-179179bab21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453903692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1453903692
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2447083140
Short name T734
Test name
Test status
Simulation time 228144900 ps
CPU time 133.52 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 261436 kb
Host smart-8b8f2a40-ceca-45f2-ab86-57457eeeb97b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447083140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2447083140
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2184458999
Short name T687
Test name
Test status
Simulation time 24252700 ps
CPU time 16.89 seconds
Started Jun 27 05:22:53 PM PDT 24
Finished Jun 27 05:23:11 PM PDT 24
Peak memory 275208 kb
Host smart-38cd251b-6c95-41ed-9667-c2351b5d7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184458999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2184458999
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.2044068401
Short name T609
Test name
Test status
Simulation time 36640400 ps
CPU time 133.25 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:25:13 PM PDT 24
Peak memory 265300 kb
Host smart-7898b024-7246-47e2-afd5-e67509037ca8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044068401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.2044068401
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3652007526
Short name T538
Test name
Test status
Simulation time 15452400 ps
CPU time 13.42 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:10 PM PDT 24
Peak memory 275420 kb
Host smart-41ec98f4-52fc-4faf-a419-dbf04268b285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652007526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3652007526
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.455848457
Short name T984
Test name
Test status
Simulation time 88148500 ps
CPU time 130.24 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:25:07 PM PDT 24
Peak memory 260568 kb
Host smart-d90ed0d4-372a-4d1b-b8da-b4e1d9c2551a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455848457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.455848457
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1023791023
Short name T508
Test name
Test status
Simulation time 24177100 ps
CPU time 16.06 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:14 PM PDT 24
Peak memory 275416 kb
Host smart-7207d11e-f2b9-4ffc-a1b0-aca3935374bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023791023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1023791023
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.1243809212
Short name T905
Test name
Test status
Simulation time 144443900 ps
CPU time 136.38 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:25:15 PM PDT 24
Peak memory 260848 kb
Host smart-16eec325-06b7-4663-b7da-f9c4127f7a58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243809212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.1243809212
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3933258696
Short name T499
Test name
Test status
Simulation time 51654700 ps
CPU time 16.19 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 284824 kb
Host smart-a1a02968-dbb2-456a-9809-ff6325119378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933258696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3933258696
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.1204145008
Short name T13
Test name
Test status
Simulation time 44301200 ps
CPU time 112.86 seconds
Started Jun 27 05:22:51 PM PDT 24
Finished Jun 27 05:24:45 PM PDT 24
Peak memory 260336 kb
Host smart-ef0f0b53-0f78-44b2-8692-72f54e3705e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204145008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.1204145008
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1426298208
Short name T1095
Test name
Test status
Simulation time 75434900 ps
CPU time 15.81 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:23:14 PM PDT 24
Peak memory 275676 kb
Host smart-f2d0a157-bc43-4aba-8563-4a3d426f905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426298208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1426298208
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3264289943
Short name T397
Test name
Test status
Simulation time 64572000 ps
CPU time 129.51 seconds
Started Jun 27 05:22:53 PM PDT 24
Finished Jun 27 05:25:05 PM PDT 24
Peak memory 265152 kb
Host smart-5ee37ae0-7c71-4425-8d9b-1b290f8d03a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264289943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3264289943
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1482105313
Short name T476
Test name
Test status
Simulation time 39739000 ps
CPU time 13.58 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 284868 kb
Host smart-e3d27e02-8f0c-462c-b3e5-10675af1730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482105313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1482105313
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3077807476
Short name T1032
Test name
Test status
Simulation time 43353000 ps
CPU time 130.79 seconds
Started Jun 27 05:22:57 PM PDT 24
Finished Jun 27 05:25:10 PM PDT 24
Peak memory 261360 kb
Host smart-303f28b5-02b6-414c-ab1d-73d07def2d3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077807476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3077807476
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2286387485
Short name T140
Test name
Test status
Simulation time 15038100 ps
CPU time 13.6 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:10 PM PDT 24
Peak memory 284868 kb
Host smart-3a6c7fba-a110-44af-a015-38f664cd863f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286387485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2286387485
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2525551832
Short name T523
Test name
Test status
Simulation time 108204400 ps
CPU time 109.29 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:24:48 PM PDT 24
Peak memory 260568 kb
Host smart-c54ad93a-0ea7-4f9e-ba7e-47d95c0cea0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525551832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2525551832
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3601049959
Short name T884
Test name
Test status
Simulation time 60826800 ps
CPU time 15.72 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:23:12 PM PDT 24
Peak memory 284824 kb
Host smart-19d118a5-8b11-40ea-a98c-d87c9ab1c103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601049959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3601049959
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.894333220
Short name T566
Test name
Test status
Simulation time 538714900 ps
CPU time 131.74 seconds
Started Jun 27 05:22:58 PM PDT 24
Finished Jun 27 05:25:12 PM PDT 24
Peak memory 265348 kb
Host smart-49420a46-91af-4ed2-8e07-33eab0a213e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894333220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot
p_reset.894333220
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.4019804580
Short name T742
Test name
Test status
Simulation time 41244100 ps
CPU time 13.79 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:15:30 PM PDT 24
Peak memory 258528 kb
Host smart-74070cd5-bb57-468e-95cf-aec643d3e7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019804580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.4
019804580
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2666740566
Short name T388
Test name
Test status
Simulation time 42614300 ps
CPU time 15.92 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:15:32 PM PDT 24
Peak memory 275128 kb
Host smart-5c0dc14f-893e-4d33-a6d6-aca2a99ea477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666740566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2666740566
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.1822371826
Short name T879
Test name
Test status
Simulation time 15239000 ps
CPU time 21.55 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:15:37 PM PDT 24
Peak memory 265564 kb
Host smart-a5e41f37-dde8-4753-8c44-7326ba1c7228
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822371826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.1822371826
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3370363686
Short name T73
Test name
Test status
Simulation time 14697361600 ps
CPU time 2450.21 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:56:07 PM PDT 24
Peak memory 263152 kb
Host smart-f2f8803d-813a-4ff7-b67d-57442d94b8b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3370363686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.3370363686
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.619540428
Short name T682
Test name
Test status
Simulation time 3875883600 ps
CPU time 1115.78 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:33:51 PM PDT 24
Peak memory 273636 kb
Host smart-63187e19-fb4e-49e5-b10e-ca65005801df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619540428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.619540428
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1095692611
Short name T54
Test name
Test status
Simulation time 221513100 ps
CPU time 22.18 seconds
Started Jun 27 05:15:13 PM PDT 24
Finished Jun 27 05:15:37 PM PDT 24
Peak memory 262884 kb
Host smart-c945db28-4d69-4d99-80cd-bd7701aade7c
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095692611 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_fetch_code.1095692611
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2167761162
Short name T180
Test name
Test status
Simulation time 10012114100 ps
CPU time 106.05 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:17:03 PM PDT 24
Peak memory 293716 kb
Host smart-830db722-8591-49d9-be51-5726447f7705
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167761162 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2167761162
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1274773160
Short name T352
Test name
Test status
Simulation time 85570000 ps
CPU time 13.66 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:15:31 PM PDT 24
Peak memory 265212 kb
Host smart-fa1edb38-6a40-4138-a84f-aba963200a45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274773160 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1274773160
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1403455278
Short name T181
Test name
Test status
Simulation time 40130241700 ps
CPU time 843.92 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:29:21 PM PDT 24
Peak memory 261224 kb
Host smart-ad37c580-7f7c-4cd5-bff5-16e493a3a0c7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403455278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.1403455278
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.2505363580
Short name T1005
Test name
Test status
Simulation time 3492403400 ps
CPU time 68.08 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:16:24 PM PDT 24
Peak memory 261256 kb
Host smart-04fd7a82-ed03-45a0-a4c6-2a9a5aacaabe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505363580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.2505363580
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.686107246
Short name T349
Test name
Test status
Simulation time 1824928700 ps
CPU time 195 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:18:32 PM PDT 24
Peak memory 291680 kb
Host smart-b7f8774f-b34f-4ec1-9d97-f276f887bf3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686107246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.686107246
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4023911247
Short name T547
Test name
Test status
Simulation time 74702100900 ps
CPU time 309.54 seconds
Started Jun 27 05:15:17 PM PDT 24
Finished Jun 27 05:20:27 PM PDT 24
Peak memory 292268 kb
Host smart-e6955be0-fe46-4bae-95ac-03a3e9a8bab9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023911247 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.4023911247
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.1352139034
Short name T815
Test name
Test status
Simulation time 35498944000 ps
CPU time 79.29 seconds
Started Jun 27 05:15:13 PM PDT 24
Finished Jun 27 05:16:33 PM PDT 24
Peak memory 265288 kb
Host smart-50b07fbc-c7ef-429d-9cc4-d285c3865b27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352139034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.1352139034
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3946801904
Short name T519
Test name
Test status
Simulation time 79271931200 ps
CPU time 164.3 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:17:59 PM PDT 24
Peak memory 265504 kb
Host smart-59f98a2b-23f6-4686-9d0e-820d1b51a90f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394
6801904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3946801904
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.4217233430
Short name T639
Test name
Test status
Simulation time 3884827900 ps
CPU time 94.16 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:16:51 PM PDT 24
Peak memory 263644 kb
Host smart-b97465a9-4493-4a8a-a789-1a691dfafc8c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217233430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.4217233430
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2984729503
Short name T972
Test name
Test status
Simulation time 24848500 ps
CPU time 13.97 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:15:30 PM PDT 24
Peak memory 265184 kb
Host smart-18c8081b-3fc6-4e70-8d97-774a18736d98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984729503 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2984729503
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2798610093
Short name T219
Test name
Test status
Simulation time 1504588000 ps
CPU time 151.54 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:17:47 PM PDT 24
Peak memory 263728 kb
Host smart-c83c6def-bbdd-48a1-8411-0bda9beec1a3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798610093 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.2798610093
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.4069157981
Short name T719
Test name
Test status
Simulation time 68962600 ps
CPU time 131.9 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:17:28 PM PDT 24
Peak memory 261372 kb
Host smart-cd1dd76c-5200-4582-bd9c-1606b50d1cf2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069157981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.4069157981
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.3384866186
Short name T939
Test name
Test status
Simulation time 696339200 ps
CPU time 204.06 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:18:13 PM PDT 24
Peak memory 263496 kb
Host smart-15b2c0eb-63fc-4219-bd05-33209110c235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384866186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.3384866186
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.4264704802
Short name T391
Test name
Test status
Simulation time 17316516600 ps
CPU time 171.27 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:18:08 PM PDT 24
Peak memory 260960 kb
Host smart-5b96d767-6475-451b-b361-466ffc63ea09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264704802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.flash_ctrl_prog_reset.4264704802
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.1315877613
Short name T856
Test name
Test status
Simulation time 43474200 ps
CPU time 244.48 seconds
Started Jun 27 05:14:47 PM PDT 24
Finished Jun 27 05:18:53 PM PDT 24
Peak memory 277520 kb
Host smart-d486b1c6-481b-4956-8a40-73b62b499124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315877613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1315877613
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3650115020
Short name T740
Test name
Test status
Simulation time 1871638400 ps
CPU time 142.95 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:17:39 PM PDT 24
Peak memory 291940 kb
Host smart-409cfae1-f65a-427d-8b01-2b1784469bbb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650115020 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.3650115020
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1829528111
Short name T188
Test name
Test status
Simulation time 3579718300 ps
CPU time 149.67 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:17:47 PM PDT 24
Peak memory 282264 kb
Host smart-de21a9bd-2591-49a6-bdb0-f8d7b823d4fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1829528111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1829528111
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.3542537613
Short name T190
Test name
Test status
Simulation time 510850500 ps
CPU time 128.97 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:17:26 PM PDT 24
Peak memory 295748 kb
Host smart-2ff09f77-3848-4e84-a407-28121383b63f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542537613 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3542537613
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1951828094
Short name T788
Test name
Test status
Simulation time 27043748300 ps
CPU time 631.14 seconds
Started Jun 27 05:15:15 PM PDT 24
Finished Jun 27 05:25:48 PM PDT 24
Peak memory 309944 kb
Host smart-345d8697-c71d-4e95-b319-09406df6068d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951828094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.1951828094
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.1139876007
Short name T367
Test name
Test status
Simulation time 44010300 ps
CPU time 31.37 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:15:46 PM PDT 24
Peak memory 275844 kb
Host smart-962c1f39-d7f8-4b23-8de0-3e9471886e09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139876007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.1139876007
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1901125556
Short name T531
Test name
Test status
Simulation time 42910200 ps
CPU time 28.69 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:15:46 PM PDT 24
Peak memory 277084 kb
Host smart-9e69c7fe-9ff3-4492-a22b-4ae41a562827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901125556 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1901125556
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1405761723
Short name T752
Test name
Test status
Simulation time 4199131000 ps
CPU time 606.35 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:25:22 PM PDT 24
Peak memory 321180 kb
Host smart-053380f4-5ef4-47bf-bc15-b20e3a6b1e9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405761723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1405761723
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.1247194330
Short name T31
Test name
Test status
Simulation time 9160793800 ps
CPU time 71.12 seconds
Started Jun 27 05:15:13 PM PDT 24
Finished Jun 27 05:16:26 PM PDT 24
Peak memory 263756 kb
Host smart-96fe14b1-bc91-4864-a2c4-dae390296b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247194330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.1247194330
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3744779521
Short name T1042
Test name
Test status
Simulation time 20473200 ps
CPU time 75.76 seconds
Started Jun 27 05:14:46 PM PDT 24
Finished Jun 27 05:16:02 PM PDT 24
Peak memory 276764 kb
Host smart-a40e29b0-c9a2-4518-bddf-1b363b89a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744779521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3744779521
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3081581193
Short name T509
Test name
Test status
Simulation time 2502601500 ps
CPU time 214.26 seconds
Started Jun 27 05:15:14 PM PDT 24
Finished Jun 27 05:18:50 PM PDT 24
Peak memory 265208 kb
Host smart-bd95f65f-0dac-440c-9ae9-cdcefa7f704e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081581193 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3081581193
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1216271024
Short name T645
Test name
Test status
Simulation time 16917400 ps
CPU time 16.89 seconds
Started Jun 27 05:22:55 PM PDT 24
Finished Jun 27 05:23:14 PM PDT 24
Peak memory 284716 kb
Host smart-23920431-aaf7-4e1f-8392-c75492e573c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216271024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1216271024
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1233718839
Short name T306
Test name
Test status
Simulation time 151429100 ps
CPU time 131.17 seconds
Started Jun 27 05:22:53 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 261432 kb
Host smart-d1a65291-2322-48dd-b0db-f3915f2d1094
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233718839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1233718839
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.1078747311
Short name T492
Test name
Test status
Simulation time 52694000 ps
CPU time 15.76 seconds
Started Jun 27 05:22:52 PM PDT 24
Finished Jun 27 05:23:09 PM PDT 24
Peak memory 275308 kb
Host smart-65229a3b-b646-4f02-9bd8-3b22e20c3e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078747311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1078747311
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.2192588214
Short name T1093
Test name
Test status
Simulation time 149970000 ps
CPU time 132.14 seconds
Started Jun 27 05:22:54 PM PDT 24
Finished Jun 27 05:25:08 PM PDT 24
Peak memory 261548 kb
Host smart-c75f796e-c12c-4b66-939d-b506194d4d24
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192588214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.2192588214
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1114910309
Short name T756
Test name
Test status
Simulation time 26290000 ps
CPU time 15.84 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:23:39 PM PDT 24
Peak memory 284776 kb
Host smart-9a2f68d1-59b6-4fb9-8262-296142fb33d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114910309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1114910309
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3219776450
Short name T1064
Test name
Test status
Simulation time 152664600 ps
CPU time 131.76 seconds
Started Jun 27 05:22:56 PM PDT 24
Finished Jun 27 05:25:10 PM PDT 24
Peak memory 261336 kb
Host smart-2a78d444-fd70-4924-ae95-da29e6182294
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219776450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3219776450
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3002493794
Short name T580
Test name
Test status
Simulation time 41523000 ps
CPU time 15.87 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:23:30 PM PDT 24
Peak memory 284900 kb
Host smart-3942f6ea-1075-4bf2-8cf5-4a27af5fb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002493794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3002493794
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3750109912
Short name T172
Test name
Test status
Simulation time 69282300 ps
CPU time 112.56 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:25:07 PM PDT 24
Peak memory 260532 kb
Host smart-4e693597-7c68-4bd6-87e9-adc8d7e84d03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750109912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3750109912
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.3467312899
Short name T454
Test name
Test status
Simulation time 42735000 ps
CPU time 15.77 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:23:29 PM PDT 24
Peak memory 284696 kb
Host smart-5bb0644e-66fb-4dd2-97ee-e0f41afb37e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467312899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3467312899
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.3841449711
Short name T449
Test name
Test status
Simulation time 108990600 ps
CPU time 129.95 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:25:25 PM PDT 24
Peak memory 260436 kb
Host smart-8662d8e7-98a3-45db-b619-8af7653ce2be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841449711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.3841449711
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.2039384994
Short name T692
Test name
Test status
Simulation time 13922600 ps
CPU time 13.33 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:23:27 PM PDT 24
Peak memory 275192 kb
Host smart-88efa1b8-cf26-4a41-aa0d-3c058ab9301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039384994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2039384994
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.955374146
Short name T1048
Test name
Test status
Simulation time 44291100 ps
CPU time 133.7 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:25:28 PM PDT 24
Peak memory 265596 kb
Host smart-815d66b4-d6b9-4c40-821d-b76f0d9cfd67
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955374146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot
p_reset.955374146
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.997689707
Short name T974
Test name
Test status
Simulation time 28005300 ps
CPU time 13.6 seconds
Started Jun 27 05:23:18 PM PDT 24
Finished Jun 27 05:23:32 PM PDT 24
Peak memory 275236 kb
Host smart-1d82b8e9-6d92-402c-9a84-aa2334cd1199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997689707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.997689707
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.2147063523
Short name T398
Test name
Test status
Simulation time 296541500 ps
CPU time 130.5 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:25:25 PM PDT 24
Peak memory 260456 kb
Host smart-42dc7edc-5320-4300-b0a8-73847f7bb229
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147063523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.2147063523
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.851565103
Short name T797
Test name
Test status
Simulation time 39334300 ps
CPU time 15.69 seconds
Started Jun 27 05:23:20 PM PDT 24
Finished Jun 27 05:23:37 PM PDT 24
Peak memory 275336 kb
Host smart-76f256ad-6723-4328-81ee-cc9432c8c8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851565103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.851565103
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.2593648864
Short name T1072
Test name
Test status
Simulation time 147575600 ps
CPU time 134.56 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:25:29 PM PDT 24
Peak memory 261484 kb
Host smart-9877f5c9-7360-4e4d-9a01-ab987226de39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593648864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.2593648864
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.3910919604
Short name T963
Test name
Test status
Simulation time 49430100 ps
CPU time 13.47 seconds
Started Jun 27 05:23:13 PM PDT 24
Finished Jun 27 05:23:29 PM PDT 24
Peak memory 284700 kb
Host smart-d0f6ff85-ffe7-400c-96f7-2b8049582577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910919604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3910919604
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.3644296330
Short name T681
Test name
Test status
Simulation time 42854500 ps
CPU time 132.66 seconds
Started Jun 27 05:23:14 PM PDT 24
Finished Jun 27 05:25:28 PM PDT 24
Peak memory 264608 kb
Host smart-af73de62-3f4a-4b5f-8a5b-3f85b987a42c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644296330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.3644296330
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.4184787711
Short name T917
Test name
Test status
Simulation time 21885600 ps
CPU time 13.71 seconds
Started Jun 27 05:23:12 PM PDT 24
Finished Jun 27 05:23:28 PM PDT 24
Peak memory 275272 kb
Host smart-67538991-6792-4c2b-a2e1-4ad37055c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184787711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.4184787711
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.2462037186
Short name T505
Test name
Test status
Simulation time 116531200 ps
CPU time 111.8 seconds
Started Jun 27 05:23:21 PM PDT 24
Finished Jun 27 05:25:15 PM PDT 24
Peak memory 260680 kb
Host smart-01215153-3216-4cd8-8d36-935145ef9549
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462037186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.2462037186
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.938214428
Short name T806
Test name
Test status
Simulation time 62559000 ps
CPU time 13.6 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:15:51 PM PDT 24
Peak memory 258696 kb
Host smart-648d1219-4297-4ee6-b691-2dda04794a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938214428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.938214428
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.2460788344
Short name T608
Test name
Test status
Simulation time 13655500 ps
CPU time 13.67 seconds
Started Jun 27 05:15:38 PM PDT 24
Finished Jun 27 05:15:52 PM PDT 24
Peak memory 275328 kb
Host smart-bfe0cbbd-cfa1-4632-beed-3c8143d19808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460788344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2460788344
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.2856841219
Short name T1079
Test name
Test status
Simulation time 22058500 ps
CPU time 21.51 seconds
Started Jun 27 05:15:39 PM PDT 24
Finished Jun 27 05:16:01 PM PDT 24
Peak memory 273964 kb
Host smart-509c93c6-b037-4b63-b4c9-7bb899d76b3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856841219 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.2856841219
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.685434745
Short name T767
Test name
Test status
Simulation time 7547762300 ps
CPU time 2400.32 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:55:34 PM PDT 24
Peak memory 263272 kb
Host smart-83ce8e58-d26a-4f98-8444-4ccce6fe9feb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=685434745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.685434745
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3179981973
Short name T285
Test name
Test status
Simulation time 1656785500 ps
CPU time 942.89 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:31:18 PM PDT 24
Peak memory 273828 kb
Host smart-bda30604-da56-48d8-9de7-809b3a4ca976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179981973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3179981973
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.1178861143
Short name T610
Test name
Test status
Simulation time 127543800 ps
CPU time 24.93 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:15:59 PM PDT 24
Peak memory 263980 kb
Host smart-b2d86bb3-b36a-45e7-b5d7-78b29788d2ae
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178861143 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_fetch_code.1178861143
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1182076027
Short name T698
Test name
Test status
Simulation time 10012747500 ps
CPU time 132.2 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:17:50 PM PDT 24
Peak memory 351404 kb
Host smart-80f46fde-ed61-455e-9f47-a5923683baa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182076027 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1182076027
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.881508347
Short name T156
Test name
Test status
Simulation time 26621100 ps
CPU time 13.34 seconds
Started Jun 27 05:15:36 PM PDT 24
Finished Jun 27 05:15:51 PM PDT 24
Peak memory 265676 kb
Host smart-0980c3ae-dd9a-4a1d-822d-0739b2b1ecba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881508347 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.881508347
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.302067933
Short name T549
Test name
Test status
Simulation time 270196676100 ps
CPU time 959.61 seconds
Started Jun 27 05:15:31 PM PDT 24
Finished Jun 27 05:31:32 PM PDT 24
Peak memory 265432 kb
Host smart-80f7a1f1-e9e9-41f7-9afa-747a3cd08486
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302067933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.302067933
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2370113826
Short name T1040
Test name
Test status
Simulation time 1380987000 ps
CPU time 188.38 seconds
Started Jun 27 05:15:32 PM PDT 24
Finished Jun 27 05:18:41 PM PDT 24
Peak memory 286284 kb
Host smart-505f959b-147f-4833-9542-5006ac274535
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370113826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2370113826
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3305653868
Short name T850
Test name
Test status
Simulation time 59103265000 ps
CPU time 251.98 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:19:47 PM PDT 24
Peak memory 292176 kb
Host smart-c787ea78-f6ee-4edf-9d59-289931992257
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305653868 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3305653868
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.430926587
Short name T530
Test name
Test status
Simulation time 5328080100 ps
CPU time 70.25 seconds
Started Jun 27 05:15:36 PM PDT 24
Finished Jun 27 05:16:47 PM PDT 24
Peak memory 265500 kb
Host smart-f8095265-ad94-4824-8df9-4abfffe19c35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430926587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.430926587
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.4110134481
Short name T597
Test name
Test status
Simulation time 82660831200 ps
CPU time 220.04 seconds
Started Jun 27 05:15:36 PM PDT 24
Finished Jun 27 05:19:17 PM PDT 24
Peak memory 260560 kb
Host smart-07c31285-05fa-40d8-b9bd-408e4ae76cc4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411
0134481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.4110134481
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.1866894794
Short name T770
Test name
Test status
Simulation time 2456141400 ps
CPU time 66.27 seconds
Started Jun 27 05:15:32 PM PDT 24
Finished Jun 27 05:16:39 PM PDT 24
Peak memory 263064 kb
Host smart-baa02d9a-43ef-4b42-9843-26b56c90bab9
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866894794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1866894794
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.557208864
Short name T901
Test name
Test status
Simulation time 29790529800 ps
CPU time 514.77 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:24:09 PM PDT 24
Peak memory 275384 kb
Host smart-6c9da61c-ec2f-4b40-bb5a-d57ab0888575
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557208864 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.557208864
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.463714601
Short name T78
Test name
Test status
Simulation time 66846500 ps
CPU time 111.79 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:17:25 PM PDT 24
Peak memory 265260 kb
Host smart-6e1e8aa8-e2df-4d73-866e-6524e92fcf1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463714601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.463714601
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.996711911
Short name T1003
Test name
Test status
Simulation time 2999493700 ps
CPU time 390.08 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:22:05 PM PDT 24
Peak memory 263392 kb
Host smart-542d3868-31a8-4669-b51b-2f924cf1e343
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996711911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.996711911
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3072477741
Short name T394
Test name
Test status
Simulation time 109449100 ps
CPU time 13.44 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:15:51 PM PDT 24
Peak memory 259236 kb
Host smart-dcde56c1-850c-4004-b1c1-db1d151168c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072477741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.flash_ctrl_prog_reset.3072477741
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2705250124
Short name T603
Test name
Test status
Simulation time 1055181100 ps
CPU time 816.63 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:28:54 PM PDT 24
Peak memory 286200 kb
Host smart-e6eaebe1-dbb5-48ad-90f9-66931e78f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705250124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2705250124
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1401605528
Short name T768
Test name
Test status
Simulation time 115917300 ps
CPU time 31.19 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:16:06 PM PDT 24
Peak memory 275780 kb
Host smart-4d5a761a-fcfd-48e4-be82-0a0fb42b3e34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401605528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1401605528
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1907058803
Short name T540
Test name
Test status
Simulation time 1198064600 ps
CPU time 99.37 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:17:14 PM PDT 24
Peak memory 289504 kb
Host smart-15a8d301-84ca-40e1-bb00-1c90b8dea702
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907058803 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.1907058803
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2916111764
Short name T664
Test name
Test status
Simulation time 702444700 ps
CPU time 182.21 seconds
Started Jun 27 05:15:33 PM PDT 24
Finished Jun 27 05:18:36 PM PDT 24
Peak memory 282360 kb
Host smart-384cf82b-668d-42cd-bc7a-8e930d1c8ad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2916111764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2916111764
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.430212459
Short name T671
Test name
Test status
Simulation time 4686049900 ps
CPU time 138.88 seconds
Started Jun 27 05:15:35 PM PDT 24
Finished Jun 27 05:17:54 PM PDT 24
Peak memory 295296 kb
Host smart-ed791482-61d5-42d3-9a2e-bcbb5766e885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430212459 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.430212459
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1548474932
Short name T838
Test name
Test status
Simulation time 14400827000 ps
CPU time 567.15 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:25:02 PM PDT 24
Peak memory 318216 kb
Host smart-a5621d01-ba6e-4c46-b303-27cc42d7c699
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548474932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.1548474932
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.3797600998
Short name T814
Test name
Test status
Simulation time 46790600 ps
CPU time 31.55 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:16:10 PM PDT 24
Peak memory 275896 kb
Host smart-74230734-fee9-4d13-9f73-ead76f10ef13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797600998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.3797600998
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3210254706
Short name T937
Test name
Test status
Simulation time 68829500 ps
CPU time 30.86 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:16:09 PM PDT 24
Peak memory 275888 kb
Host smart-e8f67d29-5f2a-4484-b5e7-561d18bbe0fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210254706 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3210254706
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3881124217
Short name T704
Test name
Test status
Simulation time 1466410100 ps
CPU time 68.91 seconds
Started Jun 27 05:15:37 PM PDT 24
Finished Jun 27 05:16:47 PM PDT 24
Peak memory 264092 kb
Host smart-e571f5dd-3e3b-480d-927e-1a4e44751c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881124217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3881124217
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.474010774
Short name T1063
Test name
Test status
Simulation time 34111000 ps
CPU time 122.07 seconds
Started Jun 27 05:15:16 PM PDT 24
Finished Jun 27 05:17:19 PM PDT 24
Peak memory 276916 kb
Host smart-2f60f586-2885-4faa-b4dc-331bb548404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474010774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.474010774
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.4153830952
Short name T113
Test name
Test status
Simulation time 2866840600 ps
CPU time 233.78 seconds
Started Jun 27 05:15:34 PM PDT 24
Finished Jun 27 05:19:29 PM PDT 24
Peak memory 265564 kb
Host smart-141bb3a6-3ec6-4242-bccf-efe451aac244
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153830952 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.4153830952
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.3717139509
Short name T750
Test name
Test status
Simulation time 28595300 ps
CPU time 13.82 seconds
Started Jun 27 05:16:08 PM PDT 24
Finished Jun 27 05:16:23 PM PDT 24
Peak memory 258588 kb
Host smart-469cb03e-41dc-439e-95fd-fb0d3272ddf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717139509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3
717139509
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.435505425
Short name T451
Test name
Test status
Simulation time 15739300 ps
CPU time 14 seconds
Started Jun 27 05:16:09 PM PDT 24
Finished Jun 27 05:16:24 PM PDT 24
Peak memory 284788 kb
Host smart-158c1571-f71c-49a0-a919-0b63db15dda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435505425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.435505425
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.3104573431
Short name T387
Test name
Test status
Simulation time 11647300 ps
CPU time 21.2 seconds
Started Jun 27 05:16:07 PM PDT 24
Finished Jun 27 05:16:29 PM PDT 24
Peak memory 265624 kb
Host smart-60eec661-6a99-4f71-8133-bb073aaef53c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104573431 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.3104573431
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1337864325
Short name T135
Test name
Test status
Simulation time 60405271300 ps
CPU time 2316.21 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:54:28 PM PDT 24
Peak memory 263224 kb
Host smart-d434bf08-2dc9-4156-b80e-fdbd2170dd48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part
ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1337864325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.1337864325
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3303845212
Short name T286
Test name
Test status
Simulation time 957075000 ps
CPU time 1067.1 seconds
Started Jun 27 05:15:51 PM PDT 24
Finished Jun 27 05:33:40 PM PDT 24
Peak memory 270828 kb
Host smart-5bac79aa-2fd7-43ef-b94d-501db72a0990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303845212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3303845212
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.2009602726
Short name T53
Test name
Test status
Simulation time 1322745300 ps
CPU time 27.21 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:16:19 PM PDT 24
Peak memory 262868 kb
Host smart-771c9524-094a-4bb6-bbd2-16f793958830
User root
Command /workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009602726 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_fetch_code.2009602726
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4165131966
Short name T727
Test name
Test status
Simulation time 10012120500 ps
CPU time 86.5 seconds
Started Jun 27 05:16:07 PM PDT 24
Finished Jun 27 05:17:35 PM PDT 24
Peak memory 273956 kb
Host smart-1a06df93-107c-4d49-a365-186e78c7f8b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165131966 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.4165131966
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.375674685
Short name T804
Test name
Test status
Simulation time 43723500 ps
CPU time 13.59 seconds
Started Jun 27 05:16:10 PM PDT 24
Finished Jun 27 05:16:24 PM PDT 24
Peak memory 258700 kb
Host smart-c5a29879-19e2-4712-b56f-803108513f38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375674685 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.375674685
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.982157675
Short name T464
Test name
Test status
Simulation time 90154378600 ps
CPU time 908 seconds
Started Jun 27 05:15:49 PM PDT 24
Finished Jun 27 05:30:58 PM PDT 24
Peak memory 261600 kb
Host smart-ba062630-efe6-4d05-8826-256ffc9930aa
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982157675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.flash_ctrl_hw_rma_reset.982157675
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2549615015
Short name T309
Test name
Test status
Simulation time 8914268000 ps
CPU time 63.72 seconds
Started Jun 27 05:15:51 PM PDT 24
Finished Jun 27 05:16:56 PM PDT 24
Peak memory 262640 kb
Host smart-c70b366b-0d15-4524-b8d6-d147141ecfd3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549615015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.2549615015
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.4292428239
Short name T748
Test name
Test status
Simulation time 9998500800 ps
CPU time 245.37 seconds
Started Jun 27 05:15:48 PM PDT 24
Finished Jun 27 05:19:54 PM PDT 24
Peak memory 284940 kb
Host smart-5d9b3c53-9f6c-490f-a095-f075fa54b7ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292428239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.4292428239
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.787417879
Short name T833
Test name
Test status
Simulation time 19798983400 ps
CPU time 82.43 seconds
Started Jun 27 05:16:06 PM PDT 24
Finished Jun 27 05:17:29 PM PDT 24
Peak memory 261008 kb
Host smart-9c088440-88b1-4d83-80f6-8732e2b0294f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787417879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 9.flash_ctrl_intr_wr.787417879
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.810746372
Short name T783
Test name
Test status
Simulation time 56310751300 ps
CPU time 238.56 seconds
Started Jun 27 05:16:08 PM PDT 24
Finished Jun 27 05:20:07 PM PDT 24
Peak memory 260744 kb
Host smart-79335f11-508b-4cde-bc86-cb9f1d5a682c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810
746372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.810746372
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1845123955
Short name T132
Test name
Test status
Simulation time 14728456700 ps
CPU time 70.54 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:17:02 PM PDT 24
Peak memory 263940 kb
Host smart-e6dc1692-1006-4c50-9bc0-2e9cf0fbe6ad
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845123955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1845123955
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.4016250133
Short name T307
Test name
Test status
Simulation time 19720000 ps
CPU time 13.99 seconds
Started Jun 27 05:16:06 PM PDT 24
Finished Jun 27 05:16:21 PM PDT 24
Peak memory 260240 kb
Host smart-016b33a8-3db1-4cef-ae86-30f5c35f3dff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016250133 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.4016250133
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.1430483413
Short name T852
Test name
Test status
Simulation time 65158100 ps
CPU time 131.65 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:18:04 PM PDT 24
Peak memory 260340 kb
Host smart-26a25b04-b8c7-4612-8009-e73446bb6231
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430483413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.1430483413
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1952357018
Short name T206
Test name
Test status
Simulation time 122687000 ps
CPU time 449.6 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:23:21 PM PDT 24
Peak memory 263508 kb
Host smart-2bc68826-bf6c-423d-a037-19c0ae6ea7fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952357018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1952357018
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.2253159942
Short name T675
Test name
Test status
Simulation time 248515600 ps
CPU time 13.93 seconds
Started Jun 27 05:16:10 PM PDT 24
Finished Jun 27 05:16:25 PM PDT 24
Peak memory 259676 kb
Host smart-ece5cb5a-1bdb-4383-8579-b6065ee3fb1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253159942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.flash_ctrl_prog_reset.2253159942
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.892207391
Short name T41
Test name
Test status
Simulation time 64480100 ps
CPU time 463.07 seconds
Started Jun 27 05:15:36 PM PDT 24
Finished Jun 27 05:23:20 PM PDT 24
Peak memory 283368 kb
Host smart-611b8d13-0fe0-4f61-a460-94fa105c3ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892207391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.892207391
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.1476509542
Short name T356
Test name
Test status
Simulation time 392347200 ps
CPU time 34.33 seconds
Started Jun 27 05:16:06 PM PDT 24
Finished Jun 27 05:16:41 PM PDT 24
Peak memory 275944 kb
Host smart-bd3b1086-33ca-497f-bb34-0e542115be65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476509542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.1476509542
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.985899006
Short name T796
Test name
Test status
Simulation time 923377200 ps
CPU time 107.76 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:17:39 PM PDT 24
Peak memory 281460 kb
Host smart-18850b91-7ba1-40c7-92d0-8f14bc212e72
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985899006 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_ro.985899006
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.968444456
Short name T935
Test name
Test status
Simulation time 722070200 ps
CPU time 136.91 seconds
Started Jun 27 05:15:48 PM PDT 24
Finished Jun 27 05:18:06 PM PDT 24
Peak memory 282248 kb
Host smart-586cd198-0187-4160-8acb-c57b3d935fc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
968444456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.968444456
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1216798355
Short name T453
Test name
Test status
Simulation time 684887500 ps
CPU time 139.7 seconds
Started Jun 27 05:15:49 PM PDT 24
Finished Jun 27 05:18:10 PM PDT 24
Peak memory 282236 kb
Host smart-ca28e877-a83d-4716-beb6-bea74dc50c28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216798355 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1216798355
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.2616418661
Short name T208
Test name
Test status
Simulation time 8578188900 ps
CPU time 553.42 seconds
Started Jun 27 05:15:51 PM PDT 24
Finished Jun 27 05:25:06 PM PDT 24
Peak memory 318148 kb
Host smart-f9506074-90c1-43da-8a93-b68b2c7cf4db
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616418661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.2616418661
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3335289896
Short name T999
Test name
Test status
Simulation time 3852866500 ps
CPU time 633.22 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:26:24 PM PDT 24
Peak memory 324748 kb
Host smart-f07ccbdf-8081-40c8-b542-01be12d9d3fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335289896 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.3335289896
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.4240894765
Short name T849
Test name
Test status
Simulation time 29527500 ps
CPU time 31 seconds
Started Jun 27 05:16:07 PM PDT 24
Finished Jun 27 05:16:39 PM PDT 24
Peak memory 275848 kb
Host smart-49032d47-847b-44ed-83ff-e31cad0bf49b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240894765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.4240894765
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.2848109926
Short name T1091
Test name
Test status
Simulation time 27847400 ps
CPU time 28.56 seconds
Started Jun 27 05:16:07 PM PDT 24
Finished Jun 27 05:16:36 PM PDT 24
Peak memory 275796 kb
Host smart-386911e8-109d-44c7-bc36-13327b54ad5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848109926 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.2848109926
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.1555706754
Short name T714
Test name
Test status
Simulation time 14404442300 ps
CPU time 717.25 seconds
Started Jun 27 05:15:48 PM PDT 24
Finished Jun 27 05:27:47 PM PDT 24
Peak memory 321380 kb
Host smart-99d0dc2f-13ed-48ae-8a3c-8315080a1481
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555706754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.1555706754
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.3906996941
Short name T915
Test name
Test status
Simulation time 3160079500 ps
CPU time 77.96 seconds
Started Jun 27 05:16:09 PM PDT 24
Finished Jun 27 05:17:28 PM PDT 24
Peak memory 263600 kb
Host smart-b5320bee-f601-4fbe-8e8f-ced32608559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906996941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3906996941
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.3358777842
Short name T512
Test name
Test status
Simulation time 20697700 ps
CPU time 148.37 seconds
Started Jun 27 05:15:36 PM PDT 24
Finished Jun 27 05:18:06 PM PDT 24
Peak memory 278040 kb
Host smart-cc3d381b-127c-4ff3-9cff-30059e7ed990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358777842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3358777842
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2915618599
Short name T392
Test name
Test status
Simulation time 10024287300 ps
CPU time 207.26 seconds
Started Jun 27 05:15:50 PM PDT 24
Finished Jun 27 05:19:19 PM PDT 24
Peak memory 265652 kb
Host smart-0ec510f5-f365-4c06-ba1c-db0f486469ee
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915618599 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2915618599
Directory /workspace/9.flash_ctrl_wo/latest
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