Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	247788	1		T1	2		T2	2		T3	1
all_values[1]	247788	1		T1	2		T2	2		T3	1
all_values[2]	247788	1		T1	2		T2	2		T3	1
all_values[3]	247788	1		T1	2		T2	2		T3	1
all_values[4]	247788	1		T1	2		T2	2		T3	1
all_values[5]	247788	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	501930	1		T1	12		T2	12		T3	6
auto[1]	984798	1		T5	8176		T39	13656		T23	10092

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	721190	1		T1	7		T2	7		T3	4
auto[1]	765538	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	247640	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	148	1		T258	1		T259	3		T260	4
all_values[1]	auto[0]	auto[1]	247628	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	160	1		T258	3		T259	4		T260	5
all_values[2]	auto[0]	auto[0]	1597	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	46	1		T258	1		T259	4		T344	1
all_values[2]	auto[1]	auto[0]	246074	1		T5	2044		T39	3414		T23	2523
all_values[2]	auto[1]	auto[1]	71	1		T258	1		T259	1		T260	1
all_values[3]	auto[0]	auto[0]	1633	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	58	1		T259	3		T260	1		T344	4
all_values[3]	auto[1]	auto[0]	84012	1		T5	487		T39	1707		T23	200
all_values[3]	auto[1]	auto[1]	162085	1		T5	1557		T39	1707		T23	2323
all_values[4]	auto[0]	auto[0]	1130	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	525	1		T1	1		T2	1		T17	1
all_values[4]	auto[1]	auto[0]	139145	1		T5	1509		T39	1707		T23	1955
all_values[4]	auto[1]	auto[1]	106988	1		T5	535		T39	1707		T23	568
all_values[5]	auto[0]	auto[0]	1535	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	138	1		T40	4		T41	1		T42	1
all_values[5]	auto[1]	auto[0]	246064	1		T5	2044		T39	3414		T23	2523
all_values[5]	auto[1]	auto[1]	51	1		T344	2		T345	1		T346	1