Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	240573	1		T3	9		T5	284		T4	1344
auto[FlashEraseBank]	267192	1		T2	2		T3	6		T5	251

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256787	1		T3	14		T5	535		T4	668
auto[FlashOpProgram]	231805	1		T2	2		T3	1		T4	338
auto[FlashOpErase]	15173	1		T4	338		T17	1		T18	1
auto[FlashOpInvalid]	4000	1		T193	200		T194	200		T133	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256787	1		T3	14		T5	535		T4	668
op[FlashOpProgram]	231805	1		T2	2		T3	1		T4	338
op[FlashOpErase]	15173	1		T4	338		T17	1		T18	1
read_erase_read	509	1		T26	7		T47	1		T34	3
read_prog_read	876	1		T3	1		T17	1		T12	4

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372405	1		T3	2		T17	8		T11	1
auto[FlashPartInfo]	131515	1		T2	2		T3	12		T5	535
auto[FlashPartInfo1]	824	1		T6	2		T26	1		T45	4
auto[FlashPartInfo2]	3021	1		T3	1		T6	3		T26	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189827	1		T3	2		T17	3		T11	1
auto[FlashPartData]	auto[FlashOpProgram]	175045	1		T17	4		T12	27		T48	1
auto[FlashPartData]	auto[FlashOpErase]	3609	1		T17	1		T12	9		T26	21
auto[FlashPartData]	auto[FlashOpInvalid]	3924	1		T193	200		T194	198		T133	198
auto[FlashPartInfo]	auto[FlashOpRead]	64278	1		T3	11		T5	535		T4	668
auto[FlashPartInfo]	auto[FlashOpProgram]	55646	1		T2	2		T3	1		T4	338
auto[FlashPartInfo]	auto[FlashOpErase]	11527	1		T4	338		T18	1		T26	23
auto[FlashPartInfo]	auto[FlashOpInvalid]	64	1		T194	2		T133	2		T431	2
auto[FlashPartInfo1]	auto[FlashOpRead]	658	1		T6	2		T26	1		T45	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T76	32		T135	1		T432	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T135	1		T127	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T135	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	2024	1		T3	1		T6	3		T26	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	952	1		T122	9		T47	4		T59	9
auto[FlashPartInfo2]	auto[FlashOpErase]	35	1		T131	3		T141	1		T367	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T141	2		T433	2		T434	2