Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29853	1		T4	684		T12	4		T26	20
auto[1]	12	1		T94	4		T366	1		T367	1
auto[2]	63	1		T181	1		T27	4		T199	1
auto[3]	293	1		T43	1		T313	1		T44	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7550	1		T4	171		T12	1		T26	5
evic_idx[1]	7545	1		T4	171		T12	1		T26	5
evic_idx[2]	7557	1		T4	171		T12	1		T26	5
evic_idx[3]	7569	1		T4	171		T12	1		T26	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	29283	1		T4	684		T49	664		T110	16
evic_op[2]	318	1		T34	4		T93	20		T110	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	[evic_op[1]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7251	1		T4	171		T49	166		T110	4
evic_idx[0]	evic_op[1]	auto[1]	2	1		T367	1		T368	1		-	-
evic_idx[0]	evic_op[1]	auto[2]	7	1		T191	3		T369	2		T370	2
evic_idx[0]	evic_op[1]	auto[3]	65	1		T371	1		T131	8		T372	3
evic_idx[0]	evic_op[2]	auto[0]	61	1		T34	1		T93	5		T110	4
evic_idx[0]	evic_op[2]	auto[1]	1	1		T94	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T373	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	7	1		T190	1		T374	1		T281	1
evic_idx[1]	evic_op[1]	auto[0]	7251	1		T4	171		T49	166		T110	4
evic_idx[1]	evic_op[1]	auto[1]	1	1		T368	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	6	1		T131	1		T191	2		T369	2
evic_idx[1]	evic_op[1]	auto[3]	54	1		T371	4		T131	4		T372	3
evic_idx[1]	evic_op[2]	auto[0]	62	1		T34	1		T93	5		T110	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T94	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T375	1		T376	1		T377	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T43	1		T44	1		T314	1
evic_idx[2]	evic_op[1]	auto[0]	7249	1		T4	171		T49	166		T110	4
evic_idx[2]	evic_op[1]	auto[1]	1	1		T368	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	7	1		T191	3		T369	3		T370	1
evic_idx[2]	evic_op[1]	auto[3]	64	1		T371	1		T131	7		T372	3
evic_idx[2]	evic_op[2]	auto[0]	66	1		T34	1		T93	5		T110	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T94	1		T378	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	5	1		T276	1		T377	2		T379	1
evic_idx[2]	evic_op[2]	auto[3]	8	1		T277	1		T278	1		T380	1
evic_idx[3]	evic_op[1]	auto[0]	7250	1		T4	171		T49	166		T110	4
evic_idx[3]	evic_op[1]	auto[2]	8	1		T191	4		T369	2		T370	2
evic_idx[3]	evic_op[1]	auto[3]	67	1		T371	1		T131	5		T372	3
evic_idx[3]	evic_op[2]	auto[0]	63	1		T34	1		T93	5		T110	4
evic_idx[3]	evic_op[2]	auto[1]	4	1		T94	1		T366	1		T381	1
evic_idx[3]	evic_op[2]	auto[2]	5	1		T181	1		T199	1		T375	1
evic_idx[3]	evic_op[2]	auto[3]	17	1		T313	1		T198	1		T382	1