Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	1094	1		T352	1094		-	-		-	-
rd_lvl[2]	6308	1		T284	1179		T352	2522		T353	2607
rd_lvl[3]	7999	1		T23	845		T219	1308		T284	537
rd_lvl[4]	42809	1		T23	855		T219	5757		T284	51
rd_lvl[5]	12596	1		T5	968		T23	79		T219	1044
rd_lvl[6]	18046	1		T5	242		T23	184		T284	214
rd_lvl[7]	5901	1		T5	1		T354	251		T355	65
rd_lvl[8]	15793	1		T5	47		T23	1		T356	2721
rd_lvl[9]	5815	1		T356	463		T357	596		T358	468
rd_lvl[10]	12491	1		T218	1358		T36	707		T37	360
rd_lvl[11]	5829	1		T5	48		T39	462		T218	307
rd_lvl[12]	3826	1		T39	1245		T284	222		T359	1132
rd_lvl[13]	4057	1		T23	183		T36	31		T37	15
rd_lvl[14]	9509	1		T202	264		T360	66		T323	62
rd_lvl[15]	2984	1		T38	57		T202	113		T361	165