Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	247788	1		T1	2		T2	2		T3	1
all_pins[1]	247788	1		T1	2		T2	2		T3	1
all_pins[2]	247788	1		T1	2		T2	2		T3	1
all_pins[3]	247788	1		T1	2		T2	2		T3	1
all_pins[4]	247788	1		T1	2		T2	2		T3	1
all_pins[5]	247788	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1213641	1		T1	12		T2	12		T3	6
values[0x1]	273087	1		T5	1879		T39	3414		T23	2749
transitions[0x0=>0x1]	243162	1		T5	1793		T39	3414		T23	2374
transitions[0x1=>0x0]	243149	1		T5	1793		T39	3414		T23	2374

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	247640	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	148	1		T258	1		T259	3		T260	4
all_pins[0]	transitions[0x0=>0x1]	67	1		T258	1		T259	2		T344	1
all_pins[0]	transitions[0x1=>0x0]	79	1		T258	3		T259	3		T260	1
all_pins[1]	values[0x0]	247628	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	160	1		T258	3		T259	4		T260	5
all_pins[1]	transitions[0x0=>0x1]	114	1		T258	3		T259	3		T260	4
all_pins[1]	transitions[0x1=>0x0]	3342	1		T38	15		T202	2		T361	280
all_pins[2]	values[0x0]	244400	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	3388	1		T38	15		T202	2		T361	280
all_pins[2]	transitions[0x0=>0x1]	57	1		T258	1		T259	1		T260	1
all_pins[2]	transitions[0x1=>0x0]	155355	1		T5	1306		T39	1707		T23	2147
all_pins[3]	values[0x0]	89102	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	158686	1		T5	1306		T39	1707		T23	2147
all_pins[3]	transitions[0x0=>0x1]	132260	1		T5	1220		T39	1707		T23	1772
all_pins[3]	transitions[0x1=>0x0]	84228	1		T5	487		T39	1707		T23	227
all_pins[4]	values[0x0]	137134	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	110654	1		T5	573		T39	1707		T23	602
all_pins[4]	transitions[0x0=>0x1]	110641	1		T5	573		T39	1707		T23	602
all_pins[4]	transitions[0x1=>0x0]	38	1		T344	2		T345	1		T350	2
all_pins[5]	values[0x0]	247737	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	51	1		T344	2		T345	1		T346	1
all_pins[5]	transitions[0x0=>0x1]	23	1		T344	2		T346	1		T349	1
all_pins[5]	transitions[0x1=>0x0]	107	1		T258	1		T259	3		T260	3