Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::sw_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mp_err	1	0	1	100.00	100	1	1	0
cp_op_err	1	0	1	100.00	100	1	1	0
cp_prog_err	1	0	1	100.00	100	1	1	0
cp_prog_type_err	1	0	1	100.00	100	1	1	0
cp_prog_win_err	1	0	1	100.00	100	1	1	0
cp_rd_err	1	0	1	100.00	100	1	1	0
cp_update_err	1	1	0	0.00	100	1	1	0

Summary for Variable cp_mp_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mp_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	63111	1		T41	1642		T42	4136		T104	1593

---

Summary for Variable cp_op_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_op_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	4000	1		T193	200		T194	200		T133	200

---

Summary for Variable cp_prog_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_prog_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	15	1		T10	5		T20	5		T21	5

---

Summary for Variable cp_prog_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_prog_type_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	514	1		T96	87		T97	125		T98	127

---

Summary for Variable cp_prog_win_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_prog_win_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	265	1		T64	29		T175	15		T176	26

---

Summary for Variable cp_rd_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_rd_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
seen	24496	1		T3	1		T30	1		T41	761

---

Summary for Variable cp_update_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for cp_update_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
seen	0	1	1