Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 260 1 T258 4 T259 7 T260 4
all_values[1] 260 1 T258 4 T259 7 T260 4
all_values[2] 260 1 T258 4 T259 7 T260 4
all_values[3] 260 1 T258 4 T259 7 T260 4
all_values[4] 260 1 T258 4 T259 7 T260 4
all_values[5] 260 1 T258 4 T259 7 T260 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 830 1 T258 16 T259 20 T260 10
auto[1] 730 1 T258 8 T259 22 T260 14



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 509 1 T258 7 T259 14 T260 11
auto[1] 1051 1 T258 17 T259 28 T260 13



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 932 1 T258 16 T259 25 T260 17
auto[1] 628 1 T258 8 T259 17 T260 7



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 84 1 T258 2 T259 2 T260 1
all_values[0] auto[0] auto[1] auto[1] 68 1 T259 3 T260 1 T344 2
all_values[0] auto[1] auto[0] auto[1] 57 1 T258 2 T344 3 T345 1
all_values[0] auto[1] auto[1] auto[1] 51 1 T259 2 T260 2 T345 1
all_values[1] auto[0] auto[0] auto[1] 92 1 T258 2 T259 2 T344 1
all_values[1] auto[0] auto[1] auto[1] 78 1 T258 2 T259 3 T260 2
all_values[1] auto[1] auto[0] auto[1] 49 1 T259 1 T260 1 T344 3
all_values[1] auto[1] auto[1] auto[1] 41 1 T259 1 T260 1 T344 1
all_values[2] auto[0] auto[0] auto[0] 67 1 T258 2 T260 1 T344 2
all_values[2] auto[0] auto[1] auto[0] 76 1 T259 2 T260 2 T344 2
all_values[2] auto[1] auto[0] auto[1] 59 1 T258 1 T259 4 T260 1
all_values[2] auto[1] auto[1] auto[1] 58 1 T258 1 T259 1 T344 2
all_values[3] auto[0] auto[0] auto[0] 87 1 T258 1 T259 2 T260 2
all_values[3] auto[0] auto[1] auto[0] 67 1 T258 2 T259 1 T260 1
all_values[3] auto[1] auto[0] auto[1] 61 1 T258 1 T259 2 T260 1
all_values[3] auto[1] auto[1] auto[1] 45 1 T259 2 T344 1 T345 1
all_values[4] auto[0] auto[0] auto[0] 47 1 T258 1 T259 2 T260 1
all_values[4] auto[0] auto[0] auto[1] 27 1 T259 1 T346 1 T347 1
all_values[4] auto[0] auto[1] auto[0] 60 1 T259 2 T344 4 T348 4
all_values[4] auto[0] auto[1] auto[1] 29 1 T258 2 T260 2 T346 2
all_values[4] auto[1] auto[0] auto[1] 51 1 T258 1 T259 1 T344 1
all_values[4] auto[1] auto[1] auto[1] 46 1 T259 1 T260 1 T344 1
all_values[5] auto[0] auto[0] auto[0] 56 1 T258 1 T259 2 T260 2
all_values[5] auto[0] auto[0] auto[1] 26 1 T258 1 T344 1 T345 1
all_values[5] auto[0] auto[1] auto[0] 49 1 T259 3 T260 2 T346 2
all_values[5] auto[0] auto[1] auto[1] 19 1 T349 2 T350 1 T351 1
all_values[5] auto[1] auto[0] auto[1] 67 1 T258 1 T259 1 T344 3
all_values[5] auto[1] auto[1] auto[1] 43 1 T258 1 T259 1 T344 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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