| T1086 |
/workspace/coverage/default/2.flash_ctrl_error_prog_win.1113096371 |
|
|
Jun 28 05:43:59 PM PDT 24 |
Jun 28 05:58:11 PM PDT 24 |
320895700 ps |
| T1087 |
/workspace/coverage/default/33.flash_ctrl_rw_evict.3489368784 |
|
|
Jun 28 05:47:34 PM PDT 24 |
Jun 28 05:48:08 PM PDT 24 |
70051900 ps |
| T1088 |
/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1340937294 |
|
|
Jun 28 05:44:49 PM PDT 24 |
Jun 28 05:47:27 PM PDT 24 |
18516096400 ps |
| T1089 |
/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3182358244 |
|
|
Jun 28 05:44:04 PM PDT 24 |
Jun 28 05:47:34 PM PDT 24 |
24037400700 ps |
| T1090 |
/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.797053514 |
|
|
Jun 28 05:44:06 PM PDT 24 |
Jun 28 05:44:30 PM PDT 24 |
27250700 ps |
| T1091 |
/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1106744627 |
|
|
Jun 28 05:47:09 PM PDT 24 |
Jun 28 05:51:45 PM PDT 24 |
47497547200 ps |
| T1092 |
/workspace/coverage/default/35.flash_ctrl_rw_evict.1122157231 |
|
|
Jun 28 05:47:50 PM PDT 24 |
Jun 28 05:48:22 PM PDT 24 |
53792000 ps |
| T1093 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3678010324 |
|
|
Jun 28 05:48:00 PM PDT 24 |
Jun 28 05:50:25 PM PDT 24 |
8364320300 ps |
| T1094 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.2672667516 |
|
|
Jun 28 05:43:58 PM PDT 24 |
Jun 28 05:47:58 PM PDT 24 |
3335529300 ps |
| T1095 |
/workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1817905883 |
|
|
Jun 28 05:47:17 PM PDT 24 |
Jun 28 05:47:49 PM PDT 24 |
44173400 ps |
| T1096 |
/workspace/coverage/default/53.flash_ctrl_otp_reset.1058659050 |
|
|
Jun 28 05:48:32 PM PDT 24 |
Jun 28 05:50:49 PM PDT 24 |
36155000 ps |
| T1097 |
/workspace/coverage/default/32.flash_ctrl_connect.676800999 |
|
|
Jun 28 05:47:34 PM PDT 24 |
Jun 28 05:47:49 PM PDT 24 |
81835600 ps |
| T1098 |
/workspace/coverage/default/24.flash_ctrl_prog_reset.1914638954 |
|
|
Jun 28 05:46:53 PM PDT 24 |
Jun 28 05:47:08 PM PDT 24 |
38937900 ps |
| T1099 |
/workspace/coverage/default/12.flash_ctrl_rw_evict.2242279361 |
|
|
Jun 28 05:45:14 PM PDT 24 |
Jun 28 05:45:47 PM PDT 24 |
121030300 ps |
| T1100 |
/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2104269571 |
|
|
Jun 28 05:46:07 PM PDT 24 |
Jun 28 05:51:23 PM PDT 24 |
50365606000 ps |
| T1101 |
/workspace/coverage/default/21.flash_ctrl_prog_reset.104394830 |
|
|
Jun 28 05:46:33 PM PDT 24 |
Jun 28 05:46:48 PM PDT 24 |
89274200 ps |
| T1102 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.3208901835 |
|
|
Jun 28 05:43:51 PM PDT 24 |
Jun 28 05:47:29 PM PDT 24 |
1960362800 ps |
| T1103 |
/workspace/coverage/default/59.flash_ctrl_otp_reset.2908267443 |
|
|
Jun 28 05:48:31 PM PDT 24 |
Jun 28 05:50:26 PM PDT 24 |
42162000 ps |
| T1104 |
/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1470711264 |
|
|
Jun 28 05:46:34 PM PDT 24 |
Jun 28 05:47:07 PM PDT 24 |
32270100 ps |
| T1105 |
/workspace/coverage/default/74.flash_ctrl_connect.2982967677 |
|
|
Jun 28 05:48:40 PM PDT 24 |
Jun 28 05:48:55 PM PDT 24 |
35820900 ps |
| T1106 |
/workspace/coverage/default/4.flash_ctrl_ro.1437644598 |
|
|
Jun 28 05:44:08 PM PDT 24 |
Jun 28 05:46:08 PM PDT 24 |
553437900 ps |
| T1107 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.302409675 |
|
|
Jun 28 05:44:07 PM PDT 24 |
Jun 28 06:12:42 PM PDT 24 |
6460110800 ps |
| T1108 |
/workspace/coverage/default/1.flash_ctrl_invalid_op.2157579800 |
|
|
Jun 28 05:43:51 PM PDT 24 |
Jun 28 05:45:01 PM PDT 24 |
2925289300 ps |
| T1109 |
/workspace/coverage/default/35.flash_ctrl_connect.3465017312 |
|
|
Jun 28 05:47:43 PM PDT 24 |
Jun 28 05:47:58 PM PDT 24 |
39889200 ps |
| T1110 |
/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2155411933 |
|
|
Jun 28 05:48:30 PM PDT 24 |
Jun 28 05:50:23 PM PDT 24 |
10777591100 ps |
| T1111 |
/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1786146892 |
|
|
Jun 28 05:44:02 PM PDT 24 |
Jun 28 05:47:02 PM PDT 24 |
23611292100 ps |
| T1112 |
/workspace/coverage/default/67.flash_ctrl_connect.2501960143 |
|
|
Jun 28 05:48:47 PM PDT 24 |
Jun 28 05:49:03 PM PDT 24 |
42515300 ps |
| T396 |
/workspace/coverage/default/22.flash_ctrl_disable.728774927 |
|
|
Jun 28 05:46:43 PM PDT 24 |
Jun 28 05:47:06 PM PDT 24 |
55873300 ps |
| T167 |
/workspace/coverage/default/0.flash_ctrl_rma_err.2326055005 |
|
|
Jun 28 05:43:51 PM PDT 24 |
Jun 28 05:59:34 PM PDT 24 |
81630967800 ps |
| T1113 |
/workspace/coverage/default/28.flash_ctrl_prog_reset.1321688972 |
|
|
Jun 28 05:47:10 PM PDT 24 |
Jun 28 05:47:25 PM PDT 24 |
134815000 ps |
| T1114 |
/workspace/coverage/default/1.flash_ctrl_host_dir_rd.693381328 |
|
|
Jun 28 05:43:50 PM PDT 24 |
Jun 28 05:44:34 PM PDT 24 |
27423100 ps |
| T1115 |
/workspace/coverage/default/5.flash_ctrl_rand_ops.2888267889 |
|
|
Jun 28 05:44:05 PM PDT 24 |
Jun 28 05:50:38 PM PDT 24 |
187322500 ps |
| T1116 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1525189564 |
|
|
Jun 28 05:45:42 PM PDT 24 |
Jun 28 05:46:16 PM PDT 24 |
31538500 ps |
| T1117 |
/workspace/coverage/default/29.flash_ctrl_smoke.3855008191 |
|
|
Jun 28 05:47:16 PM PDT 24 |
Jun 28 05:49:45 PM PDT 24 |
48656600 ps |
| T1118 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2314523509 |
|
|
Jun 28 05:44:02 PM PDT 24 |
Jun 28 05:45:34 PM PDT 24 |
10019968300 ps |
| T1119 |
/workspace/coverage/default/35.flash_ctrl_disable.4200532739 |
|
|
Jun 28 05:47:43 PM PDT 24 |
Jun 28 05:48:07 PM PDT 24 |
21653700 ps |
| T397 |
/workspace/coverage/default/0.flash_ctrl_disable.3280899524 |
|
|
Jun 28 05:43:50 PM PDT 24 |
Jun 28 05:44:17 PM PDT 24 |
16383100 ps |
| T1120 |
/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.4150630760 |
|
|
Jun 28 05:44:33 PM PDT 24 |
Jun 28 05:57:47 PM PDT 24 |
180182294200 ps |
| T1121 |
/workspace/coverage/default/26.flash_ctrl_smoke.827974022 |
|
|
Jun 28 05:47:01 PM PDT 24 |
Jun 28 05:49:02 PM PDT 24 |
28004300 ps |
| T1122 |
/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.536178952 |
|
|
Jun 28 05:47:01 PM PDT 24 |
Jun 28 05:49:37 PM PDT 24 |
5126851200 ps |
| T1123 |
/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2210240636 |
|
|
Jun 28 05:47:26 PM PDT 24 |
Jun 28 05:47:57 PM PDT 24 |
44744000 ps |
| T24 |
/workspace/coverage/default/0.flash_ctrl_access_after_disable.315771122 |
|
|
Jun 28 05:43:48 PM PDT 24 |
Jun 28 05:44:08 PM PDT 24 |
12430800 ps |
| T398 |
/workspace/coverage/default/20.flash_ctrl_disable.1139328289 |
|
|
Jun 28 05:46:38 PM PDT 24 |
Jun 28 05:47:00 PM PDT 24 |
16846600 ps |
| T1124 |
/workspace/coverage/default/7.flash_ctrl_rw_derr.1649548479 |
|
|
Jun 28 05:44:21 PM PDT 24 |
Jun 28 05:54:42 PM PDT 24 |
3193646900 ps |
| T1125 |
/workspace/coverage/default/13.flash_ctrl_wo.2731307516 |
|
|
Jun 28 05:45:31 PM PDT 24 |
Jun 28 05:47:51 PM PDT 24 |
3952506000 ps |
| T65 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2587336690 |
|
|
Jun 28 05:41:54 PM PDT 24 |
Jun 28 05:42:37 PM PDT 24 |
330519600 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.38040628 |
|
|
Jun 28 05:42:14 PM PDT 24 |
Jun 28 05:43:41 PM PDT 24 |
2633177900 ps |
| T258 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2366618157 |
|
|
Jun 28 05:42:27 PM PDT 24 |
Jun 28 05:42:51 PM PDT 24 |
18414300 ps |
| T259 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3616957868 |
|
|
Jun 28 05:42:04 PM PDT 24 |
Jun 28 05:42:25 PM PDT 24 |
24281300 ps |
| T1126 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1934352254 |
|
|
Jun 28 05:42:13 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
41804700 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1988765967 |
|
|
Jun 28 05:42:17 PM PDT 24 |
Jun 28 05:42:45 PM PDT 24 |
20727100 ps |
| T229 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1385615964 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:22 PM PDT 24 |
30689600 ps |
| T114 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1165881196 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
97606300 ps |
| T111 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1730418641 |
|
|
Jun 28 05:42:16 PM PDT 24 |
Jun 28 05:42:46 PM PDT 24 |
257852100 ps |
| T112 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1283257414 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
271961400 ps |
| T113 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1532229546 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:21 PM PDT 24 |
157555600 ps |
| T1127 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1963053946 |
|
|
Jun 28 05:42:17 PM PDT 24 |
Jun 28 05:42:41 PM PDT 24 |
14306200 ps |
| T244 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.725236953 |
|
|
Jun 28 05:42:29 PM PDT 24 |
Jun 28 05:42:58 PM PDT 24 |
992050000 ps |
| T245 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.907738082 |
|
|
Jun 28 05:42:28 PM PDT 24 |
Jun 28 05:42:56 PM PDT 24 |
117324400 ps |
| T1128 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2682209316 |
|
|
Jun 28 05:41:43 PM PDT 24 |
Jun 28 05:42:02 PM PDT 24 |
14853700 ps |
| T246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2494822209 |
|
|
Jun 28 05:42:08 PM PDT 24 |
Jun 28 05:42:51 PM PDT 24 |
423555700 ps |
| T260 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.4000636882 |
|
|
Jun 28 05:42:08 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
17346500 ps |
| T1129 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3613759785 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:16 PM PDT 24 |
14690600 ps |
| T344 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1297249695 |
|
|
Jun 28 05:42:16 PM PDT 24 |
Jun 28 05:42:40 PM PDT 24 |
27026900 ps |
| T254 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.503057933 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:49 PM PDT 24 |
140359900 ps |
| T1130 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1361198627 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:09 PM PDT 24 |
46723700 ps |
| T206 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2957585641 |
|
|
Jun 28 05:41:51 PM PDT 24 |
Jun 28 05:54:33 PM PDT 24 |
1483255000 ps |
| T207 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3092294128 |
|
|
Jun 28 05:42:18 PM PDT 24 |
Jun 28 05:42:45 PM PDT 24 |
67561900 ps |
| T208 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3857942369 |
|
|
Jun 28 05:42:21 PM PDT 24 |
Jun 28 05:55:19 PM PDT 24 |
2749349200 ps |
| T223 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.4160302434 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:13 PM PDT 24 |
50156000 ps |
| T224 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1021592607 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
237747700 ps |
| T299 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3528228728 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:31 PM PDT 24 |
57604300 ps |
| T1131 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2521302988 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:16 PM PDT 24 |
38878100 ps |
| T209 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2473809043 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:54:34 PM PDT 24 |
329571300 ps |
| T210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3126973918 |
|
|
Jun 28 05:41:55 PM PDT 24 |
Jun 28 05:42:18 PM PDT 24 |
118524100 ps |
| T225 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.407901442 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:42:21 PM PDT 24 |
194407100 ps |
| T345 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2416203223 |
|
|
Jun 28 05:41:52 PM PDT 24 |
Jun 28 05:42:07 PM PDT 24 |
19758100 ps |
| T346 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2949119324 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
15880800 ps |
| T348 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1309050282 |
|
|
Jun 28 05:41:54 PM PDT 24 |
Jun 28 05:42:10 PM PDT 24 |
47954700 ps |
| T247 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1822370433 |
|
|
Jun 28 05:41:52 PM PDT 24 |
Jun 28 05:42:13 PM PDT 24 |
313892100 ps |
| T226 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4240531221 |
|
|
Jun 28 05:42:19 PM PDT 24 |
Jun 28 05:42:50 PM PDT 24 |
195490000 ps |
| T248 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1355569083 |
|
|
Jun 28 05:42:08 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
124103500 ps |
| T1132 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4131648006 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:25 PM PDT 24 |
11548100 ps |
| T1133 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1455018725 |
|
|
Jun 28 05:41:43 PM PDT 24 |
Jun 28 05:42:01 PM PDT 24 |
22180600 ps |
| T261 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.368864849 |
|
|
Jun 28 05:41:55 PM PDT 24 |
Jun 28 05:42:15 PM PDT 24 |
69665100 ps |
| T349 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2224995894 |
|
|
Jun 28 05:41:41 PM PDT 24 |
Jun 28 05:41:58 PM PDT 24 |
52276600 ps |
| T262 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1128923512 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:36 PM PDT 24 |
52385000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1982765935 |
|
|
Jun 28 05:41:49 PM PDT 24 |
Jun 28 05:42:05 PM PDT 24 |
18623400 ps |
| T1135 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.4039388858 |
|
|
Jun 28 05:42:25 PM PDT 24 |
Jun 28 05:42:53 PM PDT 24 |
42294700 ps |
| T1136 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3116668804 |
|
|
Jun 28 05:42:12 PM PDT 24 |
Jun 28 05:42:40 PM PDT 24 |
167201200 ps |
| T249 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3383487411 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:31 PM PDT 24 |
34661900 ps |
| T263 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1483360309 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
57630600 ps |
| T250 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2241496149 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:15 PM PDT 24 |
123835500 ps |
| T347 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.319143240 |
|
|
Jun 28 05:42:05 PM PDT 24 |
Jun 28 05:42:26 PM PDT 24 |
52620400 ps |
| T350 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.4081185551 |
|
|
Jun 28 05:42:23 PM PDT 24 |
Jun 28 05:42:49 PM PDT 24 |
57230500 ps |
| T1137 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4265407514 |
|
|
Jun 28 05:42:12 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
14584300 ps |
| T1138 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1910082145 |
|
|
Jun 28 05:41:59 PM PDT 24 |
Jun 28 05:42:19 PM PDT 24 |
11772300 ps |
| T1139 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.817222235 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:22 PM PDT 24 |
37068000 ps |
| T351 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2955155315 |
|
|
Jun 28 05:42:20 PM PDT 24 |
Jun 28 05:42:45 PM PDT 24 |
55728500 ps |
| T1140 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4242585990 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:45 PM PDT 24 |
256877700 ps |
| T1141 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1043945126 |
|
|
Jun 28 05:42:07 PM PDT 24 |
Jun 28 05:43:21 PM PDT 24 |
3396777100 ps |
| T265 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4042620141 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:48:49 PM PDT 24 |
380164700 ps |
| T272 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3544913032 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:43 PM PDT 24 |
116983300 ps |
| T1142 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3824748229 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:31 PM PDT 24 |
110689300 ps |
| T270 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1546657367 |
|
|
Jun 28 05:41:55 PM PDT 24 |
Jun 28 05:54:41 PM PDT 24 |
823930700 ps |
| T383 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3105960437 |
|
|
Jun 28 05:41:42 PM PDT 24 |
Jun 28 05:56:50 PM PDT 24 |
434087600 ps |
| T1143 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2577632264 |
|
|
Jun 28 05:42:16 PM PDT 24 |
Jun 28 05:42:41 PM PDT 24 |
26833100 ps |
| T300 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1179070173 |
|
|
Jun 28 05:42:18 PM PDT 24 |
Jun 28 05:43:06 PM PDT 24 |
789555200 ps |
| T1144 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3201491051 |
|
|
Jun 28 05:42:10 PM PDT 24 |
Jun 28 05:42:32 PM PDT 24 |
51151900 ps |
| T1145 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1659297502 |
|
|
Jun 28 05:41:44 PM PDT 24 |
Jun 28 05:42:02 PM PDT 24 |
159512800 ps |
| T1146 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.3171734601 |
|
|
Jun 28 05:42:13 PM PDT 24 |
Jun 28 05:42:36 PM PDT 24 |
55939300 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2060738543 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:14 PM PDT 24 |
102279100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2904250083 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
17647100 ps |
| T1149 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1410573704 |
|
|
Jun 28 05:41:41 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
1691565200 ps |
| T1150 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1217486971 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
180586600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3058315178 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:21 PM PDT 24 |
16726600 ps |
| T274 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.986351688 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:57:29 PM PDT 24 |
673059400 ps |
| T1152 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1607408753 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:15 PM PDT 24 |
152008100 ps |
| T1153 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1956602046 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
13683300 ps |
| T271 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3964228870 |
|
|
Jun 28 05:42:14 PM PDT 24 |
Jun 28 05:42:42 PM PDT 24 |
81841000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1891553748 |
|
|
Jun 28 05:42:21 PM PDT 24 |
Jun 28 05:42:48 PM PDT 24 |
18995700 ps |
| T1155 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3826066067 |
|
|
Jun 28 05:42:10 PM PDT 24 |
Jun 28 05:42:58 PM PDT 24 |
79128400 ps |
| T1156 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2208000270 |
|
|
Jun 28 05:42:21 PM PDT 24 |
Jun 28 05:42:47 PM PDT 24 |
46991800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1814177536 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
19365700 ps |
| T1158 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.310937435 |
|
|
Jun 28 05:42:12 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
55394800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3808549074 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:22 PM PDT 24 |
131904900 ps |
| T1160 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1301274468 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
37980200 ps |
| T301 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1453106391 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:24 PM PDT 24 |
62093100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3172092089 |
|
|
Jun 28 05:41:56 PM PDT 24 |
Jun 28 05:42:12 PM PDT 24 |
19575200 ps |
| T264 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1879563639 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:18 PM PDT 24 |
206894200 ps |
| T255 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3753304105 |
|
|
Jun 28 05:41:49 PM PDT 24 |
Jun 28 05:42:09 PM PDT 24 |
100876400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1157518378 |
|
|
Jun 28 05:42:17 PM PDT 24 |
Jun 28 05:42:44 PM PDT 24 |
142367900 ps |
| T266 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3497876129 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:26 PM PDT 24 |
161319900 ps |
| T302 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.527670587 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:43 PM PDT 24 |
168483100 ps |
| T1163 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2427636829 |
|
|
Jun 28 05:42:14 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
14595200 ps |
| T303 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.232489531 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:24 PM PDT 24 |
195229400 ps |
| T1164 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1395759691 |
|
|
Jun 28 05:41:55 PM PDT 24 |
Jun 28 05:42:14 PM PDT 24 |
27839900 ps |
| T304 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.425124696 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
210461600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.4253274397 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
181729400 ps |
| T1166 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1533665803 |
|
|
Jun 28 05:41:52 PM PDT 24 |
Jun 28 05:42:12 PM PDT 24 |
73841300 ps |
| T394 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2393030785 |
|
|
Jun 28 05:41:50 PM PDT 24 |
Jun 28 05:49:33 PM PDT 24 |
1665653500 ps |
| T1167 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1716285968 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:28 PM PDT 24 |
63936600 ps |
| T1168 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2187333179 |
|
|
Jun 28 05:41:59 PM PDT 24 |
Jun 28 05:42:17 PM PDT 24 |
40925200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1523765049 |
|
|
Jun 28 05:42:25 PM PDT 24 |
Jun 28 05:42:50 PM PDT 24 |
40492600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2914480819 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:41 PM PDT 24 |
95830400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3658467611 |
|
|
Jun 28 05:42:17 PM PDT 24 |
Jun 28 05:42:42 PM PDT 24 |
15380900 ps |
| T230 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2198494758 |
|
|
Jun 28 05:41:56 PM PDT 24 |
Jun 28 05:42:12 PM PDT 24 |
48676100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2780003603 |
|
|
Jun 28 05:42:18 PM PDT 24 |
Jun 28 05:42:42 PM PDT 24 |
43782000 ps |
| T1173 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1353595335 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
58946600 ps |
| T267 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2113770469 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
463473600 ps |
| T305 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2138318957 |
|
|
Jun 28 05:42:00 PM PDT 24 |
Jun 28 05:43:25 PM PDT 24 |
13660264900 ps |
| T268 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.351905057 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:29 PM PDT 24 |
361493100 ps |
| T306 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2489341649 |
|
|
Jun 28 05:41:55 PM PDT 24 |
Jun 28 05:43:21 PM PDT 24 |
6525573200 ps |
| T385 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3249065774 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:57:39 PM PDT 24 |
3217979800 ps |
| T1174 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1816077369 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:42:55 PM PDT 24 |
1224260900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1525989608 |
|
|
Jun 28 05:42:13 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
16989700 ps |
| T1176 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.873952339 |
|
|
Jun 28 05:42:07 PM PDT 24 |
Jun 28 05:42:32 PM PDT 24 |
111257200 ps |
| T307 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3058198578 |
|
|
Jun 28 05:41:44 PM PDT 24 |
Jun 28 05:42:03 PM PDT 24 |
133859500 ps |
| T1177 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3000368889 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
14608700 ps |
| T1178 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2364972491 |
|
|
Jun 28 05:42:10 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
77052600 ps |
| T1179 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3370498067 |
|
|
Jun 28 05:42:13 PM PDT 24 |
Jun 28 05:42:35 PM PDT 24 |
194908600 ps |
| T1180 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3760315358 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:43 PM PDT 24 |
112827100 ps |
| T1181 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.696313245 |
|
|
Jun 28 05:42:18 PM PDT 24 |
Jun 28 05:42:43 PM PDT 24 |
18142700 ps |
| T1182 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4127114937 |
|
|
Jun 28 05:42:13 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
15450100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.62254849 |
|
|
Jun 28 05:42:29 PM PDT 24 |
Jun 28 05:42:53 PM PDT 24 |
17003700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1746037607 |
|
|
Jun 28 05:41:42 PM PDT 24 |
Jun 28 05:42:00 PM PDT 24 |
18906200 ps |
| T1185 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2467486843 |
|
|
Jun 28 05:41:52 PM PDT 24 |
Jun 28 05:42:10 PM PDT 24 |
73826100 ps |
| T386 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3020237351 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:55:06 PM PDT 24 |
332907500 ps |
| T1186 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3923247418 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
47836900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3301824336 |
|
|
Jun 28 05:42:14 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
32274000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3215681218 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:42:18 PM PDT 24 |
115588900 ps |
| T1189 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3939937727 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
18305900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1526677171 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:21 PM PDT 24 |
43907900 ps |
| T1191 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2877165518 |
|
|
Jun 28 05:42:10 PM PDT 24 |
Jun 28 05:42:35 PM PDT 24 |
14490300 ps |
| T1192 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2196812191 |
|
|
Jun 28 05:42:10 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
24785100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.797276899 |
|
|
Jun 28 05:42:05 PM PDT 24 |
Jun 28 05:42:27 PM PDT 24 |
92917600 ps |
| T308 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.814868661 |
|
|
Jun 28 05:42:24 PM PDT 24 |
Jun 28 05:43:07 PM PDT 24 |
1036633500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3515959255 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:42:31 PM PDT 24 |
95204900 ps |
| T1195 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2683758123 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:48:39 PM PDT 24 |
508097500 ps |
| T1196 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3733431945 |
|
|
Jun 28 05:42:19 PM PDT 24 |
Jun 28 05:42:44 PM PDT 24 |
22069000 ps |
| T1197 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1074082968 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:16 PM PDT 24 |
24666600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2488087118 |
|
|
Jun 28 05:41:44 PM PDT 24 |
Jun 28 05:42:02 PM PDT 24 |
29793800 ps |
| T256 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4066193469 |
|
|
Jun 28 05:42:22 PM PDT 24 |
Jun 28 05:42:54 PM PDT 24 |
174546300 ps |
| T1199 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.407724176 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
155914500 ps |
| T231 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3584561704 |
|
|
Jun 28 05:42:04 PM PDT 24 |
Jun 28 05:42:25 PM PDT 24 |
18614400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1800178094 |
|
|
Jun 28 05:41:56 PM PDT 24 |
Jun 28 05:42:13 PM PDT 24 |
93240800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3144294087 |
|
|
Jun 28 05:42:05 PM PDT 24 |
Jun 28 05:42:48 PM PDT 24 |
104412200 ps |
| T1202 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3247616618 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:14 PM PDT 24 |
67151800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3154694418 |
|
|
Jun 28 05:41:51 PM PDT 24 |
Jun 28 05:42:11 PM PDT 24 |
349354200 ps |
| T269 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2007032475 |
|
|
Jun 28 05:42:20 PM PDT 24 |
Jun 28 05:42:49 PM PDT 24 |
131060000 ps |
| T1204 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.272868608 |
|
|
Jun 28 05:42:25 PM PDT 24 |
Jun 28 05:42:54 PM PDT 24 |
155258700 ps |
| T1205 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1630269484 |
|
|
Jun 28 05:41:43 PM PDT 24 |
Jun 28 05:42:03 PM PDT 24 |
45020200 ps |
| T390 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.800045419 |
|
|
Jun 28 05:42:19 PM PDT 24 |
Jun 28 05:55:06 PM PDT 24 |
3233560000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2484563088 |
|
|
Jun 28 05:42:17 PM PDT 24 |
Jun 28 05:42:44 PM PDT 24 |
46477800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2953971236 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
16584600 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.43697489 |
|
|
Jun 28 05:41:41 PM PDT 24 |
Jun 28 05:41:57 PM PDT 24 |
14769900 ps |
| T273 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2470226143 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:44 PM PDT 24 |
54819200 ps |
| T1208 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3804028295 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:16 PM PDT 24 |
11943600 ps |
| T1209 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3088111761 |
|
|
Jun 28 05:41:59 PM PDT 24 |
Jun 28 05:42:22 PM PDT 24 |
52193200 ps |
| T391 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2911060642 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:49:44 PM PDT 24 |
184722300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2934688833 |
|
|
Jun 28 05:42:24 PM PDT 24 |
Jun 28 05:42:49 PM PDT 24 |
19807700 ps |
| T309 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.438058009 |
|
|
Jun 28 05:41:59 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
254056600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3355427922 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:42:17 PM PDT 24 |
631752800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1244584065 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
43566400 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1323480666 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
43674600 ps |
| T1214 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.114237110 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:45 PM PDT 24 |
809552000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3593474121 |
|
|
Jun 28 05:42:20 PM PDT 24 |
Jun 28 05:42:46 PM PDT 24 |
38724800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.619830396 |
|
|
Jun 28 05:42:03 PM PDT 24 |
Jun 28 05:42:23 PM PDT 24 |
14345500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1552094652 |
|
|
Jun 28 05:41:42 PM PDT 24 |
Jun 28 05:42:15 PM PDT 24 |
48571100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.904265146 |
|
|
Jun 28 05:42:11 PM PDT 24 |
Jun 28 05:42:36 PM PDT 24 |
98750200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3106743679 |
|
|
Jun 28 05:41:54 PM PDT 24 |
Jun 28 05:48:23 PM PDT 24 |
202845000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2542906023 |
|
|
Jun 28 05:42:12 PM PDT 24 |
Jun 28 05:42:36 PM PDT 24 |
53209200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2791179407 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:42:34 PM PDT 24 |
209997300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2437492844 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:40 PM PDT 24 |
59269300 ps |
| T1223 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2502233510 |
|
|
Jun 28 05:42:12 PM PDT 24 |
Jun 28 05:42:36 PM PDT 24 |
13576000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.639314131 |
|
|
Jun 28 05:42:25 PM PDT 24 |
Jun 28 05:42:50 PM PDT 24 |
17850400 ps |
| T1225 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.458561059 |
|
|
Jun 28 05:42:31 PM PDT 24 |
Jun 28 05:42:53 PM PDT 24 |
64694500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1092027421 |
|
|
Jun 28 05:42:22 PM PDT 24 |
Jun 28 05:42:47 PM PDT 24 |
22389700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3115027036 |
|
|
Jun 28 05:42:06 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
354902400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.876498878 |
|
|
Jun 28 05:41:46 PM PDT 24 |
Jun 28 05:42:01 PM PDT 24 |
31754000 ps |
| T384 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.4071812101 |
|
|
Jun 28 05:42:16 PM PDT 24 |
Jun 28 05:50:14 PM PDT 24 |
367004600 ps |
| T392 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1488375589 |
|
|
Jun 28 05:41:44 PM PDT 24 |
Jun 28 05:56:43 PM PDT 24 |
336935900 ps |
| T1229 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1623291250 |
|
|
Jun 28 05:42:25 PM PDT 24 |
Jun 28 05:42:50 PM PDT 24 |
14380300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2109566842 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:42:16 PM PDT 24 |
69316700 ps |
| T257 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1535794184 |
|
|
Jun 28 05:41:43 PM PDT 24 |
Jun 28 05:42:05 PM PDT 24 |
60463200 ps |
| T1231 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.563939433 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:21 PM PDT 24 |
25581200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2885205390 |
|
|
Jun 28 05:42:20 PM PDT 24 |
Jun 28 05:42:48 PM PDT 24 |
36871100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4117549001 |
|
|
Jun 28 05:42:19 PM PDT 24 |
Jun 28 05:42:44 PM PDT 24 |
92040200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3826832185 |
|
|
Jun 28 05:42:24 PM PDT 24 |
Jun 28 05:42:50 PM PDT 24 |
16292800 ps |
| T1235 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2339335894 |
|
|
Jun 28 05:42:01 PM PDT 24 |
Jun 28 05:42:24 PM PDT 24 |
289705000 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.103664275 |
|
|
Jun 28 05:41:41 PM PDT 24 |
Jun 28 05:41:57 PM PDT 24 |
14591400 ps |
| T1237 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3525086918 |
|
|
Jun 28 05:42:20 PM PDT 24 |
Jun 28 05:42:51 PM PDT 24 |
86728800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.690790522 |
|
|
Jun 28 05:42:16 PM PDT 24 |
Jun 28 05:42:42 PM PDT 24 |
65747900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2347820055 |
|
|
Jun 28 05:42:04 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
194289000 ps |
| T387 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.197820244 |
|
|
Jun 28 05:41:46 PM PDT 24 |
Jun 28 05:49:27 PM PDT 24 |
3519594300 ps |
| T393 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1293206743 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:54:52 PM PDT 24 |
872795200 ps |
| T233 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3305933775 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
45354000 ps |
| T1240 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3028619233 |
|
|
Jun 28 05:41:57 PM PDT 24 |
Jun 28 05:42:18 PM PDT 24 |
390943000 ps |
| T1241 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2108994681 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:30 PM PDT 24 |
15706200 ps |
| T1242 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3224669035 |
|
|
Jun 28 05:42:23 PM PDT 24 |
Jun 28 05:42:48 PM PDT 24 |
50720200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2506232509 |
|
|
Jun 28 05:41:53 PM PDT 24 |
Jun 28 05:43:11 PM PDT 24 |
11347539800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1705500294 |
|
|
Jun 28 05:41:46 PM PDT 24 |
Jun 28 05:42:41 PM PDT 24 |
3319118300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2977905055 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:42:15 PM PDT 24 |
34210900 ps |
| T388 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.743836045 |
|
|
Jun 28 05:41:58 PM PDT 24 |
Jun 28 05:54:50 PM PDT 24 |
338883900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1918102881 |
|
|
Jun 28 05:42:09 PM PDT 24 |
Jun 28 05:42:33 PM PDT 24 |
25351600 ps |
| T1247 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.373927534 |
|
|
Jun 28 05:42:02 PM PDT 24 |
Jun 28 05:42:24 PM PDT 24 |
21210200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.560447171 |
|
|
Jun 28 05:42:15 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
18317200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1756938081 |
|
|
Jun 28 05:41:59 PM PDT 24 |
Jun 28 05:42:38 PM PDT 24 |
63946600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.983177933 |
|
|
Jun 28 05:42:18 PM PDT 24 |
Jun 28 05:42:42 PM PDT 24 |
23330100 ps |
| T1251 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2192670306 |
|
|
Jun 28 05:42:07 PM PDT 24 |
Jun 28 05:42:28 PM PDT 24 |
17774400 ps |