Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343422	1		T1	2		T2	2		T3	2
all_values[1]	343422	1		T1	2		T2	2		T3	2
all_values[2]	343422	1		T1	2		T2	2		T3	2
all_values[3]	343422	1		T1	2		T2	2		T3	2
all_values[4]	343422	1		T1	2		T2	2		T3	2
all_values[5]	343422	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	693004	1		T1	12		T2	12		T3	12
auto[1]	1367528	1		T26	25600		T27	13936		T28	14128

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1008424	1		T1	7		T2	7		T3	7
auto[1]	1052108	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	343263	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	159	1		T268	3		T270	5		T334	3
all_values[1]	auto[0]	auto[1]	343260	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	162	1		T268	3		T269	3		T270	6
all_values[2]	auto[0]	auto[0]	1532	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	73	1		T268	1		T269	1		T270	2
all_values[2]	auto[1]	auto[0]	341766	1		T26	6400		T27	3484		T28	3532
all_values[2]	auto[1]	auto[1]	51	1		T269	1		T270	1		T334	1
all_values[3]	auto[0]	auto[0]	1574	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	62	1		T268	3		T269	1		T270	2
all_values[3]	auto[1]	auto[0]	71564	1		T27	1742		T28	1766		T22	1612
all_values[3]	auto[1]	auto[1]	270222	1		T26	6400		T27	1742		T28	1766
all_values[4]	auto[0]	auto[0]	1100	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	507	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	247674	1		T26	4800		T27	1742		T28	1766
all_values[4]	auto[1]	auto[1]	94141	1		T26	1600		T27	1742		T28	1766
all_values[5]	auto[0]	auto[0]	1484	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	149	1		T38	1		T19	1		T20	1
all_values[5]	auto[1]	auto[0]	341730	1		T26	6400		T27	3484		T28	3532
all_values[5]	auto[1]	auto[1]	59	1		T270	1		T337	1		T338	2