Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246891	1		T1	37		T2	464		T3	4
auto[FlashEraseBank]	270733	1		T1	26		T3	4		T10	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	254090	1		T1	35		T2	8		T3	7
auto[FlashOpProgram]	243186	1		T1	24		T2	448		T3	1
auto[FlashOpErase]	16348	1		T1	4		T2	8		T10	10
auto[FlashOpInvalid]	4000	1		T128	200		T130	200		T131	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	254090	1		T1	35		T2	8		T3	7
op[FlashOpProgram]	243186	1		T1	24		T2	448		T3	1
op[FlashOpErase]	16348	1		T1	4		T2	8		T10	10
read_erase_read	508	1		T1	1		T35	1		T25	14
read_prog_read	900	1		T1	6		T3	1		T19	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	369510	1		T1	33		T3	8		T10	389
auto[FlashPartInfo]	144714	1		T1	15		T2	464		T10	583
auto[FlashPartInfo1]	839	1		T1	9		T5	1		T38	1
auto[FlashPartInfo2]	2561	1		T1	6		T15	6		T5	8

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	178672	1		T1	15		T3	7		T10	257
auto[FlashPartData]	auto[FlashOpProgram]	183281	1		T1	16		T3	1		T10	128
auto[FlashPartData]	auto[FlashOpErase]	3641	1		T1	2		T10	4		T56	2
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T128	198		T130	198		T131	198
auto[FlashPartInfo]	auto[FlashOpRead]	73060	1		T1	7		T2	8		T10	385
auto[FlashPartInfo]	auto[FlashOpProgram]	58909	1		T1	6		T2	448		T10	192
auto[FlashPartInfo]	auto[FlashOpErase]	12671	1		T1	2		T2	8		T10	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	74	1		T128	2		T130	2		T131	2
auto[FlashPartInfo1]	auto[FlashOpRead]	673	1		T1	9		T5	1		T38	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T112	1		T134	1		T116	1
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T239	1		T137	1		T350	1
auto[FlashPartInfo2]	auto[FlashOpRead]	1685	1		T1	4		T5	8		T38	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	833	1		T1	2		T15	6		T19	3
auto[FlashPartInfo2]	auto[FlashOpErase]	33	1		T31	2		T32	1		T112	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T351	2		T352	2		T140	2